Design Of Sequential Circuits Research Articles

Design of Reversible Serial Adder Based on EPOE Expressions for Computational Applications

Considering the growing trend toward reducing the size of electronic devices, reducing power consumption has become one of the major concerns of circuit designers. One of the solutions to reduce power consumption is the design of reversible circuits. This paper proposed the design of a low-cost self-control serial adder system. In the proposed circuit, EPOE expressions have been used for the direct and compact design of sequential circuits to reduce the fixed inputs of sequential logic circuits. In addition, to reduce the quantum cost, common terms between the outputs are optimally used. Also, limiting the use of Tofoli gates with a size larger than three inputs in the implementation of the final circuit will reduce the quantum cost of the resulting circuit. The results and comparisons showed that the proposed design has improved efficiency measures including quantum cost, garbage outputs, and fixed inputs compared to existing works.

Design and analysis of fault-tolerant sequential logic circuits for safety-critical applications

Safety-critical systems used in applications that demand high levels of dependability, efficiency, and fault-tolerance often use sequential logic circuits in its design and implementation. The safety-critical digital system typically uses latches, flip-flops, and other memory elements, which are prone to the effects of natural faults and single event upsets (SEUs) caused by radiation-induced effects. The faults can lead to subsystem failures due to the continuous advancement in the realization of the small size transistor. To design a reliable digital-based system, it is essential to develop new fault-tolerance approaches that are integrated into the design of sequential logic circuits. This work proposes a novel fault-tolerant approach based on the redundancy of sequential logic circuit, which consists of a variety of design components, D flip-flop storage elements linked to a fault injection unit, a duplicate modular redundancy, and data monitoring units with a switching circuit. The experimental simulation results using a five-state Markov chain analysis model prove that the proposed fault-tolerant system can achieve 0.99999998 for reliability of the fault detection coverage (C) which equal to 0.99999. Finally, we believe that using this new approach of fault-tolerance and redundancy would improve the dependability and reliability of next generation safety-critical applications.

Integrated circuit design based on CMOS technology principle and its application in GPU

In today's society, the application of integrated circuit technology can be seen everywhere, especially in the past two decades. This paper mainly studies the principle and design of CMOS devices in IC technology and discusses the research and analysis of the acceleration algorithm of IC design. This paper adopts the research method of literature review and analysis to summarize the existing research results. This paper first introduces the development background of integrated circuit technology and the importance of CMOS technology. Subsequently, the concept and interconnection principle of CMOS device, and the combined circuit design and sequential logic circuit design principle of dynamic and static CMOS are explained in detail. Then, the application principle of CMOS technology in GPU is analyzed, and its specific application in GPU acceleration algorithm is analyzed. Finally, the application of CMOS technology in integrated circuits and its application and acceleration effect are summarized.

Programmable Synchronous 2-Bit Counter in Quantum-Dot Cellular Automata

Quantum-dot Cellular Automata (QCA) is a newly-developed nanoscale electron device that has the potential to replace the conventional transistor in the future. Owing to the unique field-coupling mechanism of QCA, several constraints must be fulfilled during the design of QCA sequential circuits, which makes the construction of sequential circuits a relatively intractable issue in QCA research. In this paper, a programmable synchronous 2-bit counter in QCA is proposed, which is consisted of combinational logic and falling edge-triggered JK flip-flops. The count mode of the programmable counter can be changed on-demand by mode control signals. Moreover, an initial state setting method of the QCA circuit is also proposed during the design of the counter so that the effects of random initial states can be avoided. Simulation with QCADesigner software demonstrates the validity of the proposed counter.

Methodology for Automated Design of Quantum-Dot Cellular Automata Circuits

Quantum-dot Cellular Automata (QCA) provide very high scale integration potential, very high switching frequency, and have extremely low power demands, which make the QCA technology quite attractive for the design and implementation of large-scale, high-performance nanoelectronic circuits. However, state-of-the-art QCA circuit designs were not derived by following a set of universal design rules, as is the case of CMOS circuits, and, as a result, it is either impossible or very difficult to combine QCA circuit blocks in effective large-scale circuits. In this paper, we introduce a novel automated design methodology, which builds upon a QCA specific universal design rules set. The proposed methodology assumes the availability of a generic QCA crossbar architecture and provides the means to customize it in order to implement any given logic function. The programming principles and the flow of the proposed automated design tool for crossbar QCA circuits are described analytically and we apply the proposed automated design method for the design of both combinatorial and sequential circuits. The obtained designs demonstrate that the proposed method is functional, easy to use, and provides the desired QCA circuit design unification.

Incorporating programming languages for enhancing the learning process of sequential logic circuit design

Logic circuits in digital electronics can generally be classified two categories-combinational and sequential logic circuits.There are several software-based applications and hardware description languages to describe the structure and behavior of electronic circuits.Although it is an easy to construct a state transition table from the state transition diagram,creating an excitation table according to the memory element type in the sequential circuit design is a very laborious and time-consuming task.After the logic functions extracted from the state transition tables are obtained,logic design verification can be carried out by a conventional simulator.This will require time and persistence much like learning any other skill.Computer science degrees include courses focused mainly on programming languages.There’s a strong case to be made for use of skills acquired in programming courses to shorten the learning curve.Thus, this work has proposed a method for the implementation of the circuit only the state equations of the sequential circuit without dealing with excitation tables.This eliminates the process of constructing the circuit schematically, since it does not require flip-flop selection.In this method, since the state equations can be expressed through buttonbox,checkbox,textbox etc.which are the basic elements of the programming language,the behavior of the circuit can be observed in a very short time.

An effective GDI (Gate Diffusion Input) Based 16- bit Shift Register Design for Power and Area Optimization

Abstract: Sequential circuit design is heavily influenced by power consumption and area reduction. Mainly consisted is shown here. Rather than using flip flops, pulsed latches are used to limit the amount of space these utilize. The shift register uses a minimal number of pulsed clock signals by combining the latches into numerous sub shifter registers and using Multiplexer and additional temporary storage latches. Multiple non-overlap delayed pulsed clock signal schemes are presented for data synchronization in a multi bit shift register to decrease power consumption. In order to maintain the current system, Tanner SEDIT will be used with Taiwan Semiconductor (TSMC) 0.18mm technology. Designing low-power digital combinational circuits using Gate Diffusion Input(GDI) is a common practice nowadays. When used in particular operating conditions, the GDI approach restores the in-cell swing by implementing sophisticated logic functions on two transistors. This method reduces power consumption, propagation latency, and digital circuit size while maintaining low complexity of logic design. Dual Edge Triggered Flip Flop(DETFF) implementation using GDI technology is introduced as an improvement to the shift register design. This idea also takes into account time restrictions, which can be reduced with the least amount of management. Keywords: Shift Register, Thermometer Code, Gate Diffusion Input, Dual Edge Triggered Flip-Flop, Propagation latency.

Algorithmic Method for the Design of Sequential Circuits with the Use of Logic Elements

This article presents issues related to the design of sequential control systems. The algorithmic design method of sequential control systems is discussed, which allows the design of a diagram of any sequential system. The algorithmic method uses the description in the form of a connection formula. The connection formula defines the order of actuations of driver elements, in this case actuators. The algorithmic method is used, among others, for systems with actuators cooperating with distributors controlled electrically on both sides. The process of creating a system graph has been characterized. The operation of the system has been shown graphically. On the basis of the created graph describing the functions of signal processing, a method for rapid programming of sequential electro-pneumatic systems with the use of logic elements has been provided. A separate dedicated timing unit has been used to perform memory functions. Its operation is based on successive states, in such a way that the next state deletes the previous one. Graph-based systems have been validated through simulation using Festo’s FluidSim computer-aided design software.

Design and Implementation of Electro-Pneumatic/Hydraulic Sequential Circuits / Concepção e Implementação de Circuitos Sequenciais Electro-Pneumáticos/Hidráulicos

Electro-pneumatic and hydraulic sequential circuits are one of the industrial automation cornerstones. Programmable Logic Controllers (PLC) are one of the main components of these circuits; however, its application is highly dependent on programmer’s skills. Different methods are found in the literature to design those systems, but they involve complex analyses and intuitive strategies in cases that the actuators extend and retract more than once within the cycle of movements, and within simultaneous movements. The design of sequential circuit is a challenge, despite the fact it is a discrete event system, and, most of times, there are mandatory hardware restrictions. As a consequence, the resulting circuits mostly require a large number of valves and electronic components and it depends on user expertise in order to be implemented. The objective of this work is to describe a novel method that can be applied in the design and implementation of circuits using PLC's, eliminating intuitive solutions. Examples are presented to illustrate the theoretical procedures and experimental tests performed to validate the method. The results prove the generality of this work, the simplicity of its implementation, and introduce a bridge between design and implementation of electro pneumatics and electro/hydraulics circuits with PLC's.

Comparative Review on Efficient Design of Reversible Sequential Circuits based on Optimization Parameters

Reversible computing, a well known research area in the field of computer science. One of the aims of reversible computing is to design low power digital circuits that dissipates no energy to heat. The main challenge of designing reversible circuits is to optimize the parameters which make the design costly. In this paper, we review different designs of efficient reversible sequential circuits and prepare a comparative statement based on eight optimization parameters such as Quantum Cost (QC), Delay (del), Garbage Output (GO), Constant Input (CI), Gate Level (GL), Number of Gate (NoG), Type of Gate (ToG), Hardware Complexity (HC) of Circuit.

Efficient designs of reversible sequential circuits

Recently, the synthesis of reversible sequential circuits has attracted researchers’ attention for implementing low-power logic designs. So far, the direct and replacement techniques have been used in the reversible sequential circuits design. The replacement technique leads to high quantum cost. There is the principle to look for efficient reversible circuits composed of Clifford + T gates by optimizing quantum cost, the number of T gates, and particularly the T-depth of the circuit, which depends on the type and layout of the reversible gates used in the function. This paper has proposed an optimized version of direct feedback technique without any flip-flops and is performed on several samples of reversible circuits design, such as counters and shift registers. It has been shown that by partial changes in the direct technique, quantum cost and other cost metrics have been improved. It has also displayed some efficient designs of the reversible parallel-to-serial converter with parity capability and low-cost design of the control unit for a reversible self-controlled serial adder system. The analysis and comparison depict that all new proposed designs have optimized the existing works in terms of performance variables, including quantum cost, number of T gates, and T-depth of the circuit.

Analysis and optimal design of johnson counter

The power consumption and propagation delay in a digital system is mainly due to sequential circuits. VLSI designers were primarily focused with low power, decreased latency and area efficient sequential circuit design. In the fulfillment of these objectives, the application of optimum design technology is essential. A counter comprises of the sequential circuit, having a broad variety of applications, including PLL, Digital to Analog, Signal Generators, Signal Synthesizers, etc. In this study a 4-bit Johnson counter is proposed for low power, high speed and cost efficient. The flip flop circuit utilized 14 transistors to produce a master D flip flop operation that triggered negative edge. The proposed counter is similar to the conventional counter's performance and price. With 43.22 percent less power dissipation than conventional versions, the suggested design has been found 48.86 percent faster. In the proposed counter, the transistor requirements are also 69.5 percent reduced, giving them an optimal area design.

A design of sequential reversible circuits by reversible gates

Reversible logic has become increasingly important in the design of low power CMOS circuits, quantum computing and nanotechnology. In this article we work on recent sequential circuits namely RS Flip Flop JK Flop Flip Flop Flop Flip Flop Master Slave Flip Flop using some reversible gates FG (Feyman Gate), FRG (Fredkin Gate), NG (New Gate) , PG (Peres Gate), BJN (New BJN Gate), while modifying them to obtain new circuits keeping their same functionality and increasing their performances.

Design and Implementation of Sequential Circuit Based on Reversible Gate in Emerging Technologies for HCI

Affective computing is a growing research area used to develop the system in such a way to recognize, interpret, process and simulate the human emotions in a systematic manner. The main application of Affective computing is the human computer interaction, in which the communication between the human and the machine enhances by giving an appropriate response to the user in an effective and empathic manner. This paper mainly concentrates on the systems which can extract the previous, past and present information based on sequential circuit. Design sequential circuit (SC) with the help of reversible gate (RG) because RG is an emerging technology and consume low power and area. The SC is implemented Xilinx software and calculates parameters.

General Method to Design Reversible Universal n-Bit Up/Down Counters

With the growing trend towards reducing the size of electronic devices, reducing power consumption has become one of the major concerns of circuit designers, and designing reversible circuits is one of the approaches proposed for reducing power consumption. Although several studies have been done in the field of synthesizing combinational reversible circuits, little work has been done for designing reversible sequential circuits. Furthermore, many researches in this context use traditional designs which replace latches, flip-flops and associated combinational gates with their reversible counterparts. This traditional technique is not very promising, because it leads to high quantum cost (QC) and garbage outputs. Recently, researchers have proposed direct design of reversible sequential circuits using Reed Muller expressions to obtain next state output. Since most sequential circuits have multiple outputs, using common product terms between multiple outputs might decrease QC significantly. In this paper, a modular and low QC design for a synchronous reversible [Formula: see text]-bit up/down counter with parallel load capability is presented. In this design, the common terms among multiple outputs are used efficiently, which leads to a low QC for the counter. A general formula to evaluate the QC of our proposed reversible counter is presented. This result shows that in our proposed design by increasing the number of bits of counter ([Formula: see text], the QC increases linearly, while in previous works by increasing the number of bits of counter, the QC increases exponentially.

Parity-preserving reversible flip-flops with low quantum cost in nanoscale

In recent years, reversible logic has attracted high importance because of its in-cognitive property of reduction in energy dissipation which is the main requirement in low-power digital circuits. Reversible logic is one of emerging fields of research, which is used in various fields such as low-power CMOS, DNA computing, quantum computing, fault tolerance and nanotechnology. A circuit is reversible if it has the same number of inputs and outputs, and there is a one-to-one correspondence between them. A reversible circuit is parity-preserving if the EXOR of the inputs is equal to the EXOR of the outputs. Flip-flops are considered as one of the most important digital designs that are widely used as building blocks in the design of sequential circuits. In this paper, two new 4 × 4 parity-preserving reversible blocks are first proposed, called PNM1 and PNM2, respectively. Quantum syntheses of the proposed blocks are carried out using the Miller et al. method. In the following, effective designs of parity-preserving reversible D, T and J-K flip-flops along with their master–slave versions are introduced using the proposed parity-preserving reversible blocks and DFG gates. Finally, a 4-bit asynchronous up-counter is designed using the proposed parity-preserving reversible D flip-flop and FRG gate. The results of the comparisons show that although the proposed structures are close to previous designs in terms of gate count, constant input and garbage output criteria, they are superior in terms of quantum cost.

An Optimized Counter Design using T Flip-Flop in Quantum-Dot Cellular Automata Technology

Conventional CMOS technology have lot of limitations and serious challenges threat this technology when scaled to a nano-level. Several alternative technologies have been proposed as solutions to overcome limitations and challenges encountered by CMOS. Quantum dot-cellular automata (QCA) is an emerging nanotechnology for the development of logic circuits such as combinational and sequential circuits.QCA seems to be best alternative to the conventional complementary metal-oxide semiconductor (CMOS) technology.QCA is a new computing paradigm in nanotechnology that can implement digital circuits with outstanding features such as ultralow power consumption, faster switching speed and extremely density structure . In this paper , a novel area efficient and optimized QCA layout design of sequential circuit T flip flop is proposed by which the QCA layout area has reduced by 57% , cell count improved by 56% in comparison with the earlier best designs. The use of proposed T flip flop in designing sequential circuits like synchronous 2 bit up counter,3 bit up counter and 4 bit up counter has reduced the QCA layout area by 65%,64% and 68% respectively where as QCA cell count are reduced by 53%, 62% and 59%.. The sequential circuits flip flop and counters are designed using three input XOR gate and are implemented by QCA layout. The paper also present the use of proposed T flip flop designed with 3 input XOR gate in designing not only synchronous binary up counters but also in synchronous binary down counter provides a significant reduction in the hardware and complexity than the existing methods. These circuits are simulated using computer aided design tool QCA Designer 2.0.3, which is a design and simulation tool for quantum dot cellular automata. The aim is to maximize the circuit density and focus on a QCA layout that uses minimal number of cells

Efficient designs of reversible latches with low quantum cost

Reversible computing is one of the most promising technologies in the design of low-power digital circuits, optical information processing, quantum computing, DNA computing, digital signal processing, and nanotechnology. The main purpose of the design of reversible circuits is to reduce the energy consumption that occurs due to the loss of input bits in irreversible circuits. A gate/block is reversible if the number of inputs and the number of outputs are equal and there is one-to-one correspondence between them. Latches are considered as one of the most important digital structures that are widely used as building blocks in the design of sequential circuits. Here, eight new reversible blocks are first offered. Then using some of them, several effective designs of reversible D, T, and J-K latches are proposed. The results of the evaluations indicate that the proposed latches are superior in terms of quantum cost (QC) than previous designs. Moreover, they are very close to or better than the best previous designs in terms of criteria such as gate count (GC), constant inputs (CI), and garbage outputs (GO).

Dynamic signal driving strategy based high speed and low powered dual edge triggered flip flop design used memory applications

Power utilization assumes a massive part in any of the integrated circuits, and it’s rundown as a standout amongst essential difficulties in the universal innovation guide into semiconductors. Generally in integrated circuit, flip-flop and clock distribution system consume a lot of energy since they make and utilize the most extreme number of internal transitions. In the clock distribution system, the clock signal circulates from a typical point to every one of the components that required for the circuit. However this capacity is more important to the synchronous framework, much consideration needs to provide for the attributes of these clock signals. In the sequential circuits, a clock distribution system spends a lot of power given the high operating frequency of high capacitance. An existing approach to reducing the limits of a clock signal is based on the quantity of clocked transistors. In this, an advanced procedure is proposed and evaluated by utilizing Dual-Edge Triggered Flip-Flop (DETFF) depends on the Dynamic Signal Driving (DSD) strategy. This DETFF is executed in sequential circuits that have been ordered using Tanner Electronic Design Automation (EDA) tool which is used to simulate and examine control by using Dynamic Signal Driving (DSD) strategy. The outcomes demonstrate that the total power utilization is decreased in sequential benchmark circuit design. A number of Flip flops have been designed by various technologies such as reducing area, delay, and power, but this proposed dynamic signal driving scheme can be used for any integrated circuit- that can be reduced to all these three parameters to give the best trade-off for a particular ASIC platform.

Statistical data analysis for harmonic reduction in 3Ø -fragmented source using novel fuzzy digital logic switching technique

Purpose The purpose of this paper is to analyze the Luo super boost converter coupled fragmented source inversion system (LC-FSIS) and the progress of a controller structure for energy stored. The inversion system is characterized by a diode arm structure and can be easily amassed into a conversion system for high/medium- power conversion systems.Design/methodology/approach The investigation is based on the practice of a simplified circuit established as common anode/common cathode, where all the diodes in each arm are connected to a renewable DC voltage source. In this proposed work, a novel fuzzy digital logic switching technique (FDLST) for three-phase fragmented source inversion (FSI) for enhancement in power excellence is measured to enterprise the novel fuzzy digital logic switching technique to authorize operative voltage utilization and enhanced harmonic spectrum.Findings Sequential circuit design using flip-flops is used in the analysis of fuzzy digital logic switching technique.Originality/value The three-phase fragmented source configuration is designed using a split DC source which is obtained from the Opto-electric source and is implemented using MOSFET. The procedure of novel FDLST reduces the Statistical Harmonic Reduction (SHR). Simulation and results are carried out to prove the dominance of designed FDLST.