Sequencer Chip Research Articles

The complete mitochondrial genome of the endemic and threatened killifish Orestias ascotanensis Parenti, 1984 (Cyprinodontiformes, Cyprinodontidae) from the High Andes

The killifish Orestias ascotanensis is endemic to the small isolated springs of Ascotán salt pan in the Central High Andes, Chile. Due to small populations, mining activity, and increasing aridity, this species is catalogued in danger of extinction. The complete mitochondrial genome of O. ascotanesis was assembled with an Ion Torrent sequencer (chip 318) that produced 2.61 million of reads. The 16 617 bp of the entire genome consisted of 22 transfer RNAs, 2 ribosomal RNAs, 13 protein-coding genes, and a control region, showing that the gene composition and arrangement match to that reported for most fishes.

Developing a Broadband Amplifier for Analysis of DNA Structural and Molecular Characteristics

The recent emergence of DNA-based diagnostics increases the need for rapid DNA sequencing technologies. One method to achieve this is to pass DNA through a nanopore, recording the trans-membrane current with a low-noise current amplifier. The challenge presented in this method is that the bandwidth of commercially available current amplifiers is limited to 100kHz, which is not fast enough to resolve the signals present in DNA sequencing. To overcome this problem, researchers have developed a custom amplifier that has reached a bandwidth of approximately 1MHz, being able to reveal additional information during the DNA translocation events through a nanopore.We will demonstrate a design of a custom amplifier that offers a wider bandwidth than the current designs, enabling the study of DNA translocation without the need to limit the speed of translocation. In addition, an amplifier with a bandwidth larger than 1MHz allows discoveries to be made about information that might be present in a higher range of frequencies, enabling measurements at a higher time resolution than what was previously possible. The amplifier will be designed to allow direct integration of a micro- or nanopore sensing area on the same physical substrate, eliminating the need for external electrode wiring. The outcomes from this research open up the possibility of an integrated high-speed DNA sequencer chip enabling rapid disease diagnostics.

Architecture design for regulating and scheduling user's traffic in ATM networks

The asynchronous transfer mode (ATM) technique provides a standardized and flexible scheme to transport and switch traffic effectively for different services. To provide satisfactory quality of service (QOS) to all users on the network, it is necessary to control the user's traffic so that network resources can be efficiently and fairly utilized by all the users while still meeting the individual QOS requirement. In this paper, we propose to control the user's traffic at two places in the network: at the user-network interface (UNI) by a traffic shaper or a traffic enforcer, and at the network-node interface (NNI) by a traffic regulator and a traffic scheduler. The traffic shaper/enforcer adopted in our work contains a buffer to delay and shape the violating cells that do not comply with some agreed-upon traffic parameters. The traffic regulator regulates cells at each network node to avoid long bursts being formed which may increase the network congestion probability. A traffic scheduler that follows the traffic regulator schedules the cells' departure sequences based on their delay priorites. We have proposed a general, feasible architecture to implement the traffic shaper, regulator, and scheduler, at various places in the network. A key component, the Sequencer chip, which contains 150k CMOS transistors, has been implemented to realize the architecture.

A 2-D integer cosine transform chip set and its applications

An integer cosine transform denoted ICT (10,9,6,2,9,3) has been shown to be a promising alternative discrete cosine transform (DCT) for its implementation simplicity, close performance, and compatibility to the DCT. The authors describe a hardware realization of the 2D-ICT (10,9,6,2,9,3) using two custom designed chips, referred to as the ICT chip and a data sequencer chip. Both chips were implemented on a 3- mu m gate array with 2800 gates. The chip set can compute 2D order-8 ICT in less than 19 mu s. The speed can be even faster in inverse transform if high-sequence coefficients are truncated. An image processing unit based on this chip set has also been developed which is useful in image archiving systems such as electronic albums.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A VLSI sequencer chip for ATM traffic shaper and queue manager

The authors propose to control user traffic at two places in an asynchronous transfer model (ATM) network: at the user-network interface (UNI) by a traffic enforcer, and at the network-node interface (NNI) by a queue manager. The traffic enforcer adopted in this work contains a buffer to delay and reshape the violating cells that do not comply with some agreed-upon traffic parameters, and thus is also called a traffic shaper. The queue manager manages the queued cells in network nodes in such a way that higher priority cells are always served first, low-priority cells are discarded when the queue is full, and any interference between same-priority cells is prevented. Architectures for the traffic shaper and the queue manager are proposed. A key component, called the sequencer chip, has been implemented and tested to realize both architectures. The sequencer chip uses 1.2- mu m CMOS technology. It contains about 150 K transistors, has a die size of 7.5 mm*8.3 mm, and is packages in a 223-pin ceramic pin-grid-array (PGA) carrier.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A digital color CCD imaging system using custom VLSI circuits

The authors describe a prototype digital imaging system that can be configured as a single-sensor video camera or a film-to-video converter. The system includes a CCD (charge-coupled device) image sensor with a 3G color filter pattern, two full-custom CMOS digital video signal processing chips, and a custom electronically programmable sequencer chip. The CMOS VLSI digital circuits offer real-time operation while meeting the size, power, and cost constraints of one-chip cameras and fill-to-video converters. System timing and design methodology are discussed. >