Sensitive Amplifier Research Articles

Dynamic Compression of the Signal in a Charge Sensitive Amplifier: Experimental Results

This paper is concerned with the experimental characterization of a charge sensitive amplifier featuring dynamic signal compression, fast recovery time, low noise, and reduced area occupancy. The device takes the advantage of the nonlinear characteristic of a feedback transistor that behaves like a voltage-controlled capacitance. This property has been exploited to fit a wide input dynamic range into the available output swing. The charge amplifier can be operated in synchronous mode at high frame rates, of the order of few megahertz, thanks to a wide bandwidth, an improved output stage, and a fast reset network. Thanks to the small area occupancy, the amplifier is suitable for integration in a $100\times 100\,\,\mu \text {m}^{2}$ pixel area. All these features make the device a good candidate for applications where a fast front end with a nonlinear response is required, such as in imaging instrumentation for free electron laser experiments. The aim of this paper is to present and discuss the experimental results coming from the characterization of the first prototype of the circuit, which has been designed in a 65-nm CMOS technology. This paper has been carried out in the frame of the PixFEL Project funded by the Istituto Nazionale di Fisica Nucleare, Italy.

СБИС для микроэлектронного координатно-чувствительного детектора нового поколения с расширенным полем анализа для масс-спектрометрии

The authors have developed a custom VLSI chip for the new generation of MCSD devices — multichip detectors with an extended analysis field and higher technical characteristics, which can be used in elemental analysis devices to simultaneously determine the elements that make up the material with high sensitivity and accuracy in real time. VLSI chip contains 384 channels with a spatial resolution of 25 microns has been integrated onto a single chip, each channel has a metal anode to collect the electrons as they emerge from the microchannel plate electron multiplier (MCP); a charge sensitive amplifier to produce a digital signal in response to the electron pulse and a 16-bit counter associated with it to accumulate the counts as they arrive and circuitry to read out the data sequentially from all channels in the microcircuit. The VLSI chip is designed according to the design rules standard 1,0 µm CMOS process. The speed of the microcircuit in the counting mode is at least 15 MHz, in the mode of reading information from the counters — more than 10 MHz. The output from the 16-bit counters on the detectors is presented via an 8-bit port and is read into the control electronics sequentially from each counter in turn in low-byte, high-byte order. The circuit has been designed in such a way that an arbitrary number of detector chips may be abutted together on a substrate behind the MCP, allowing for long focal plane detectors to be built, limited only by the size of MCPs available.

Development of monolithic pixel detector with SOI technology for the ILC vertex detector

We have been developing a monolithic pixel sensor for the International Linear Collider (ILC) vertex detector with the 0.2 μm FD-SOI CMOS process by LAPIS Semiconductor Co., Ltd. We aim to achieve a 3 μm single-point resolution required for the ILC with a 20×20 μm2 pixel. Beam bunch crossing at the ILC occurs every 554 ns in 1-msec-long bunch trains with an interval of 200 ms. Each pixel must record the charge and time stamp of a hit to identify a collision bunch for event reconstruction. Necessary functions include the amplifier, comparator, shift register, analog memory and time stamp implementation in each pixel, and column ADC and Zero-suppression logic on the chip. We tested the first prototype sensor, SOFIST ver.1, with a 120 GeV proton beam at the Fermilab Test Beam Facility in January 2017. SOFIST ver.1 has a charge sensitive amplifier and two analog memories in each pixel, and an 8-bit Wilkinson-type ADC is implemented for each column on the chip. We measured the residual of the hit position to the reconstructed track. The standard deviation of the residual distribution fitted by a Gaussian is better than 3 μm.

Performance of Pad Front-End Board for Small-Strip Thin Gap Chamber With Cosmic Ray Muons

We report on the characterization of pad front-end board (pFEB) for small-strip thin gap chamber (sTGC) prototype. The pFEB is based on field programmable gate array (FPGA) and application-specific integrated circuit. It has been built to verify the capabilities of the sTGC detector for the ATLAS Phase-I new small wheel upgrade. The pFEB consists of three VMM2 front-end chips, two Kintex-7 FPGAs used to buffer the VMM2 data, a gigabit ethernet transceiver (GET), and all the required connectors. The VMM2, designed at Brookhaven National Laboratory, is composed of 64 linear front-end channels. Each channel integrates a charge sensitive amplifier, a shaper, a stable band-gap referenced baseline, several analog-to-digital converters, and other functions. The GET works at physical layer of the network. The mini-serial attached SCSI connector accepts three external signals (40-MHz clock, reset, and trigger), which are used for synchronization of several pFEBs. In addition, the pFEB can work in the case of self-trigger mode and external trigger mode. The specific characteristics and implementations are described in detail. Also, the performance of this new type of sTGC detector has been studied with cosmic ray muons.

On the Design of Wideband Transformer-Based Fourth Order Matching Networks for ${E}$ -Band Receivers in 28-nm CMOS

This paper discusses the design of on-chip transformer-based fourth order filters, suitable for mm-Wave highly sensitive broadband low-noise amplifiers (LNAs) and receivers (RXs) implemented in deep-scaled CMOS. Second order effects due to layout parasitics are analyzed and new design techniques are introduced to further enhance the gain-bandwidth product of this class of filters. The design and measurements of a broadband 28-nm bulk CMOS LNA and a sliding-IF RX tailored for ${E}$ -band (i.e., 71–76-GHz and 81–86-GHz) point-to-point communication links are presented. Leveraging the proposed design methodologies, the ${E}$ -band LNA achieves a figure of merit $\approx 10.5$ -dB better than state-of-the-art designs in the same band and comparable to LNAs at lower frequencies. The RX achieves 30.8-dB conversion gain with ${E}$ -band with wide margin.

Design of a charge sensitive spectroscopy amplifier for Compton camera

SynopsisA charge sensitive spectroscopy amplifier has been designed to couple with the silicon strip detector of a Compton camera. The amplifier was optimized by using a wave form generator and the output gain of 1012V/C was achieved when the shaping time is 1μs.

A New Imaging System for Real-Time Process Control

In this paper, a new tomography technique called electrical charge tomography for two-phase flow imaging is presented. The probe consists of few pair of electrodes which are electrically energized to generate electrical charges within the fluid under test. The intensity of these charges depends on the chemical and physical properties of the fluid, as well as to its molecular distribution. Another group of electrodes surrounding the cross section of the fluid under test are used to capture the induced electrical charges. These are then converted into an electrical signal using a high sensitive charge amplifier. A postprocessing unit which consists of an analog to digital converter, followed by an field programmable gate array (FPGA) module is then used for high level signal processing (i.e., a dedicated dynamic thresholding algorithm) and image reconstruction. Experimental results demonstrate the capability of the system to accurately generate 2-D cross-sectional images, where the error is lower by up to 14% when using another electrical capacitance (ECT) tomography probe. The other advantage of this technique over ECT is the reduced data acquisition time, since in ECT a minimum time is required for the charge and discharge of the capacitance in order to achieve acceptable accuracy. This makes the probe another attractive concept for future tomography systems targeting real-time applications.

A High-Voltage Closed-Loop SC Interface for a ± 50 g Capacitive Micro-Accelerometer With 112.4 dB Dynamic Range

A low-noise high-linearity switched capacitor interface implemented in a 0.35$\mu \text {m}$ 3.3 V/15 V CMOS process is presented in this paper for a ±50g capacitive micro-accelerometer. The sensing element is enclosed in an optimized closed loop with proportional-integral compensation, improving the linearity significantly. In order to suppress the flicker noise of the front-end at the lowest cost, a novel switched capacitor PI controller combined with a charge sensitive amplifier using correlated double sampling is proposed. Furthermore, a detailed noise analysis of the proposed CSA-PIC combination with a final goal of achieving 120 dB dynamic range is also presented. The theoretical analysis is verified by the consistency between calculated results and PNoise simulation results. The sensor output can be read in analogue domain from a sample-and-hold buffer or in digital domain from a back-end 2-1 MASH $\Sigma$ -$\Delta$ ADC. The fabricated prototype circuit measures 11.75 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and operates under 15-V and 3.3-V supplies at a sampling clock of 111 KHz. Meanwhile, a sensitivity of 99.7 mV/g is achieved with a dynamic range of 112.4 dB over a 200-Hz bandwidth. The accelerometer has a DC nonlinearity of 0.623 in the range of -18 g to +14 g measured in self-test mode and the bias instability is 200 $\mu \text {g}$ .

All-Optical Phase Quantization with High Accuracy Based on a Multiwave Interference Phase Sensitive Amplifier

A scheme of all-optical multilevel phase quantization with high accuracy based on multiwave interference is proposed. The influences of the amplitude ratios of the conjugate ( N − 1 )th and ( N + 1 )th harmonics to the signal on phase quantization accuracy are researched. The characteristics of the phase quantization output with the amplitude ratios variation are discovered. By using the proposed scheme, the output phase is more concentrated than that of the traditional method for multilevel phase quantization. The simulations show the effectiveness of the scheme for the three levels quantization and the application of four levels quantization to the quadrature phase shift keying signal regeneration.

Development of a multi frequency impedance measurement system for use in MEMS flow cytometers

A novel MEMS based system for flow cytometry is presented based on a multispectral approach. The solution provides the ability to concurrently generate, detect and analyse the response from a biological cell using multiple narrow band signals with a frequency separation sufficient to evoke different cellular responses. The narrow band approach limits the energy required and provides an improved signal to noise ratio for a given transmitter energy, avoiding wide band signal power dissipation and dilution issues. It requires only a single transmitter and receiver interface to the MEMS device with no duplication of analogue signal paths. The design has the ability to generate a complex multi frequency waveform with a wide frequency separation. A digital approach based on the CORDIC algorithm (Volder, IRE Trans Electron Comput EC-8:330–334, 1959) was used to generate the required sinusoidal waveforms. The digital section of the design was implemented on an FPGA. It utilised a modified digital phase sensitive amplifier to provide enhanced signal to noise performance and harmonic rejection. A novel hybrid, cross channel electrode structure to implement the stimulus and response analysis sub-system has been designed. A fully functional macroscopic test bench has been constructed to demonstrate the viability of the approach. Both physical measurements and finite element data has been used to demonstrate the potential for migration into a MEMS based system.

SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades

This paper presents the test results of the second prototype of SAMPA, the ASIC designed for the upgrade of read-out front end electronics of the ALICE Time Projection Chamber (TPC) and Muon Chamber (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25 V nominal voltage supply and provides 32 channels, with selectable input polarity, and three possible combinations of shaping time and sensitivity. Each channel consists of a Charge Sensitive Amplifier, a semi-Gaussian shaper and a 10-bit ADC; a Digital Signal Processor provides digital filtering and compression capability. In the second prototype run both full chip and single test blocks were fabricated, allowing block characterization and full system behaviour studies. Experimental results are here presented showing agreement with requirements for both the blocks and the full chip.

A fast, low power and low noise charge sensitive amplifier ASIC for a UV imaging single photon detector

NASA has funded, through their Strategic Astrophysics Technology (SAT) program, the development of a cross strip (XS) microchannel plate (MCP) detector with the intention to increase its technology readiness level (TRL), enabling prototyping for future NASA missions. One aspect of the development is to convert the large and high powered laboratory Parallel Cross Strip (PXS) readout electronics into application specific integrated circuits (ASICs) to decrease their mass, volume, and power consumption (all limited resources in space) and to make them more robust to the environments of rocket launch and space. The redesign also foresees to increase the overall readout event rate, and decrease the noise contribution of the readout system. This work presents the design and verification of the first stage for the new readout system, the 16 channel charge sensitive amplifier ASIC, called the CSAv3. The single channel amplifier is composed of a charge sensitive amplifier (pre-amplifier), a pole zero cancellation circuit and a shaping amplifier. An additional output stage buffer allows polarity selection of the output analog signal. The operation of the amplifier is programmable via serial bus. It provides an equivalent noise charge (ENC) of around 600 e^− and a baseline gain of 10 mV/fC. The full scale pulse shaped output signal is confined within 100 ns, without long recovery tails, enabling up to 10 MHz periodic event rates without signal pile up. This ASIC was designed and fabricated in 130 nm, TSMC CMOS 1.2 V technology. In addition, we briefly discuss the construction of the readout system and plans for the future work.

Theoretical Investigation of Longitudinal Dispersion Fluctuations on All-Fiber Phase-Sensitive Parametric Optical Switch

A fiber-based all-optical switch accomplished by pump depletion in a single-pump phase sensitive (PS) amplifier is theoretically investigated using an inhomogeneous fiber model including the zero-dispersion wavelength (ZDW) fluctuations. We find that the off -state (maximum pump depletion) of the PS all-optical switch is very sensitive to the ZDW fluctuations, whereas the on -state (minimum pump depletion) is more robust. Meanwhile, the nonreciprocal transmission characteristic of the PS all-optical switch induced by the ZDW fluctuations is investigated with the help of the proposed inhomogeneous fiber model. Our theoretical results are useful to optimize the experimental implementation of PS all-optical switch.

Fast sensitive amplifier for two-probe conductance measurements in single molecule break junctions.

We demonstrate an amplifier based on the Wheatstone bridge designed specifically for use in single molecule break junctions. This amplifier exhibits superior performance due to its large bandwidth, flat frequency response, and high sensitivity. The amplifier is capable of measuring conductance values from 102 to 10-6G0 (G0 = 2e2/h), while maintaining a bandwidth in excess of 20 kHz, and shows remarkable resolution in the molecular conductance regime of 10-2 to 10-5 G0.

Characterization of the column-based priority logic readout of Topmetal-II− CMOS pixel direct charge sensor

We present the detailed study of the digital readout of Topmetal-II- CMOS pixel direct charge sensor. Topmetal-II- is an integrated sensor with an array of 72×72 pixels each capable of directly collecting external charge through exposed metal electrodes in the topmost metal layer. In addition to the time-shared multiplexing readout of the analog output from Charge Sensitive Amplifiers in each pixel, hits are also generated through comparators in each pixel with individually adjustable thresholds. The hits are read out via a column-based priority logic structure, retaining both hit location and time information. The in-array column-based priority logic features with a full clock-less circuitry hence there is no continuously running clock distributed in the pixel and matrix logic. These characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments. We studied the detailed working behavior and performance of this readout, and demonstrated its functional validity and potential in imaging applications.

System-level considerations for the front-end readout ASIC in the CBM experiment from the power supply perspective

New fixed target experiments using high intensity beams with energy up to 10 AGeV from the SIS100 synchrotron presently being constructed at FAIR/GSI are under preparation. Most of the readout electronics and power supplies are expected to be exposed to a very high flux of nuclear reaction products and have to be radiation tolerant up to 3 MRad (TID) and sustain up to 1014/cm2 of 1 MeV neutron equivalent in their life time. Moreover, the mostly minimum ionising particles under investigation leave very little signal in the sensors. Therefore very low noise level amplitude measurements are required by the front-end electronics for effective tracking. Sensor and interconnecting micro-cable capacitance and series resistance in conjunction with intrinsic noise of the charge sensitive amplifier are dominant noise sources in the system. However, the single-ended architecture of the amplifiers employed for the charge processing channels implies a potential problem with noise contributions from power supply sources. Strict system-level constraints leave very little freedom in selecting a power supply structure optimal with respect to: power efficiency, cooling capabilities and power density on modules, but also noise injection to the front-end via the power supply lines. Design of the power supply and distribution system of the Silicon Tracking System in the CBM experiment together with details on the front-end ASICs (STS -XYTER2) and measurement results of power supply and conditioning electronics (selected DC/DC converter and LDO regulators) are presented.

Simulation approach to charge sharing compensation algorithms with experimental cross-check

Hybrid pixel detectors for X-ray imaging, working in a single photon counting mode, find applications in a variety of fields, such as medical imaging, material science or industry. However, charge sharing, which occurs when a photon hits a detector in the area between two or four pixels, becomes more significant with decreasing pixel size. If the charge generated when a photon interacts with a detector is collected by more than one pixel, the photon energy and the event position may be improperly detected. Therefore, algorithms for minimization of the impact of charge sharing on a pixel detector for X-ray detection need to be implemented. Firstly, such algorithms must be assessed on a simulation level. The goal is to implement the simulations in such a way that the simulation accuracy and simulation time are optimized. A model should be flexible enough so that it can be quickly adapted for other uses. We propose behavioral models implemented in the Cadence® Virtuoso® environment. This is a solution that enables fast validation of the system at the higher level of abstraction allowing deep verification. A readout channel of a chip is represented using parameterized behavioral blocks of different functionality, such as, a charge sensitive amplifier, shapers, discriminators, comparators. The inter-pixel connections are taken into account. This approach enables top-down design and optimization of parameters. The model was implemented in particular to test the C8P1 algorithm used in the Chase Jr. chip, however, due to its modular implementation, it can be easily adjusted to further test of the algorithms. The simulation approach is described and the simulation results are presented together with the experimental data obtained during synchrotron measurements for the Chase Jr. chip with the C8P1 algorithm implemented.

Energy-correction photon counting pixel for photon energy extraction under pulse pile-up

A photon counting detector (PCD) has been proposed as an alternative solution to an energy-integrating detector (EID) in medical imaging field due to its high resolution, high efficiency, and low noise. The PCD has expanded to variety of fields such as spectral CT, k-edge imaging, and material decomposition owing to its capability to count and measure the number and the energy of an incident photon, respectively. Nonetheless, pulse pile-up, which is a superimposition of pulses at the output of a charge sensitive amplifier (CSA) in each PC pixel, occurs frequently as the X-ray flux increases due to the finite pulse processing time (PPT) in CSAs. Pulse pile-up induces not only a count loss but also distortion in the measured X-ray spectrum from each PC pixel and thus it is a main constraint on the use of PCDs in high flux X-ray applications. To minimize these effects, an energy-correction PC (ECPC) pixel is proposed to resolve pulse pile-up without cutting off the PPT by adding an energy correction logic (ECL) via a cross detection method (CDM). The ECPC pixel with a size of 200×200µm2 was fabricated by using a 6-metal 1-poly 0.18µm CMOS process with a static power consumption of 7.2 μW/pixel. The maximum count rate of the ECPC pixel was extended by approximately three times higher than that of a conventional PC pixel with a PPT of 500 nsec. The X-ray spectrum of 90 kVp, filtered by 3mm Al filter, was measured as the X-ray current was increased using the CdTe and the ECPC pixel. As a result, the ECPC pixel dramatically reduced the energy spectrum distortion at 2 Mphotons/pixel/s when compared to that of the ERCP pixel with the same 500 nsec PPT.

Development of a highly sensitive radon-222 amplifier (HiSRA) for low-level atmospheric measurements

Radon (222Rn), a radioactive gas with a half-life of 3.82 days, is continuously emanated from soil, rocks, and water by the radioactive decay of 226Ra. Radon-222 is released from the ground into the atmosphere, where it is transported mainly by turbulent diffusion or convection. For precise measurement of radon-222 atoms in the atmosphere, the detectors typically used present a small volume or surface area and are therefore not very sensitive, especially for online measurements and short sample intervals (<1 h). This article deals with the development of a Highly Sensitive Radon Amplifier (HiSRA) consisting in an enrichment system placed prior to a classic radon-222 analyzer. This system uses permeation membranes that make it possible to treat large quantities of air online (30 m3 h−1). The radon-222 concentration is increased instantaneously by at least a factor of 30 across the HiSRA system. Therefore, in this study, when coupling to an ionization chamber (AlphaGUARDTM) at the outlet of the HiSRA system, the detection limit of the overall system is multiplied by factor of 30 and induces a new LD for a radon 222 gas analyzer lower than 1 Bq m−3 for an integrating time of 10 min and 0.1 Bq m−3 for 1 h. We constructed one radon amplifier prototype that provided the preliminary results for amplification efficiency and the initial measurements presented herein.

Low-Parametric-Crosstalk Phase-Sensitive Amplifier for Guard-Band-Less DWDM Signal Using PPLN Waveguides

We demonstrated guard-band-less dense wavelength division multiplex signal amplification with a phase sensitive amplifier (PSA). The PSA consists of periodically poled lithium niobate waveguide that employs two-stage nonlinear process, namely second-harmonic generation and optical parametric amplification, which makes it possible to mitigate the crosstalk induced by the optical parametric interaction between DWDM channels. The PSA amplified 16-channel signals simultaneously with a gain of 17 dB over 12-nm wavelength range. We demonstrated a 2.5-dB signal-to-noise-ratio improvement and a low noise figure of 2.1 dB below the 3-dB quantum limit. We achieved the amplification of a 10-Gbaud quadrature phase shift keying signal with phase and amplitude regeneration.