Sense Amplifier Based Flip Flop Research Articles

Review of innovations in low-power flip-flops based on the development of innovative logic gates

Integrated circuits have advanced quickly alongside the semiconductor industry's tremendous growth. The primary design considerations for each circuit in a VLSI data path are minimization of area and power consumption. As a very important logic unit in the integrated circuit, reducing the flip-flop's power consumption is of great significance for improving the performance of the whole circuit. There are many ways to reduce the power consumption of the flip-flop. This paper reviews several new low-power flip-flop designs using methods to improve the logic structure of flip-flops and their logic gates, including a reversible flip-flop design with reversible gates, a flip-flop design with memristors, and a sense amplifier-based flip-flop. The analysis shows that all three options for improving the logic gate can reduce the power consumption of the flip-flops and also have a positive effect on reducing the size of the device.

A glitch free variability resistant high speed and low power sense amplifier based flip flop for digital sequential circuits

In this work, a sense amplifier based flip flop (SAFF) is presented appropriate for high speed, high data activity and low power operations. The delay and power of the proposed flip flop have been considerably reduced as it uses a novel single-ended latch structure. The flip flop (FF) also achieves glitch free operation and can be operated and is functional at near-threshold voltage levels. SPICE simulations were carried out to do a comprehensive and quantifiable analysis between the presented architecture and formerly known architectures in 32 nm CMOS technology. The proposed design achieved a reduction of minimum 22.67% in power at nominal voltage. In terms of Power Delay Product (PDP), a reduction of 63.51% was observed. At 100 MHz clock frequency, the power dissipation was lowered by 30%. The proposed design at data activity of 100% consumes 28.24% less power whereas at activities of less than 12.5% it does not show significant improvements. However, the proposed design has an advantage in terms of speed and is 40% to 82% faster at nominal conditions and can also operate at wide supply voltage. It also has the second lowest transistor count and second lowest area. The power performance is verified by implementing the proposed design as a 4-bit shift register.

Design and Analysis of High Performance Frequency Divider in 32 nm CMOS Technology for Biomedical Applications

In this paper, a 3-bit frequency divider (FD) using a novel sense amplifier based flip-flop (SAFF) is presented and demonstrated. The delay in this design was meticulously improved resulting in better values of power delay product (PDP).The latching stage of the proposed design makes use of a novel single ended structure. Comparative analysis in 32 nm CMOS technology using T-SPICE revealed significant and quantitative differences between the proposed design and the existing designs. The PDP results were obtained for ±10% voltage variation, wide temperature range of -40 ℃ to 125 ℃ and at extreme corner cases. Results indicated that the PDP of the new design at nominal operating conditions decreased by minimum of 27.28% and maximum of 57.49%. The proposed design was also at par with available design in terms of area and power. The analysis on the FD proved the assertions that the proposed design is a feasible alternative for high performance applications.

Power and Area Efficient Sense Amplifier Based Flip Flop with Wide Voltage and Temperature Upholding for Portable IoT Applications

Power and Area Efficient Sense Amplifier Based Flip Flop with Wide Voltage and Temperature Upholding for Portable IoT Applications

A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS

In this paper, a sense-amplifier-based flip-flop (SAFF) suitable for low-power high-speed operation is proposed. With the employment of a new sense-amplifier stage as well as a new single-ended latch stage, the power and delay of the flip-flop is greatly reduced. A conditional cut-off strategy is applied to the latch to achieve glitch-free and contention-free operation. Furthermore, the proposed SAFF can provide low voltage operation by adopting MTCMOS optimization. Post-layout simulation results based on a SMIC 55 nm MTCMOS show that the proposed SAFF achieves a 41.3% reduction in the CK-to-Q delay and a 36.99% reduction in power (25% input data toggle rate) compared with the conventional SAFF. Additionally, the delay and the power are smaller than those of the master-slave flip-flop (MSFF). The power-delay-product of the proposed SAFF shows 2.7× and 3.55× improvements compared with the conventional SAFF and MSFF, respectively. The area of the proposed flip-flop is 8.12 μm2 (5.8 μm × 1.4 μm), similar to that of the conventional SAFF. With the employment of MTCMOS optimization, the proposed SAFF could provide robust operation even at supply voltages as low as 0.4 V.

Time Amplifier Based Bang-Bang Phase Frequency Detector in 0.18μm CMOS Technology

A CMOS Implementation of Time amplifier (TA) based Bang-Bang Phase Frequency Detector (BBPFD) using Sense amplifier based flip flop (SAFF) is presented in this paper using 0.18μm CMOS technology. A time amplifier based on feedback output generator concept is utilized in minimizing the metastability and increasing the gain of TA which in turn boosts the gain of Phase Frequency Detector (PFD). Also, a modified SAFF was built in CMOS 0.18μm technology at 1.8V which further reduces the hysteresis and metastability aspect related to PFD. The proposed PFD works at a maximum frequency of 4GHz consuming 0.46mW of power with no dead zone.

SINUSOIDAL CLOCKED SENSE-AMPLIFIER-BASED ENERGY RECOVERY FLIP-FLOPS

Energy recovery clocking is an ultimate solution to the ultra low power sequential digital circuit design. In this paper, we present a new slave latch for a sense-amplifier based flip-flop (SAFF). Energy recovery sinusoidal clock is applied to the low power SAFF. Extensive simulation based comparisons among reported and proposed SAFF are carried-out at 90 nm CMOS technology node. The proposed flip-flop operating with energy recovery single phase sinusoidal clock shows better performance. The proposed flip-flop also reduces the leakage current and glitch.

Design of CMOS constant switching current flip-flop

A novel flip-flop that has constant switching current profile is proposed. The proposed flip-flop contributes no pattern dependent current consumption compared to a conventional sense amplifier-based flip-flop. It can be useful for supplying noise-sensitive analogue circuits or adopted in smart cards or cryptographic processors, which can secure sensitive data from differential power analysis.

Improved sense-amplifier-based flip-flop: design and measurements

Design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is presented. It was found that the main speed bottleneck of existing SAFF's is the cross-coupled set-reset (SR) latch in the output stage. The new flip-flop uses a new output stage latch topology that significantly reduces delay and improves driving capability. The performance of this flip-flop is verified by measurements on a test chip implemented in 0.18 /spl mu/m effective channel length CMOS. Demonstrated speed places it among the fastest flip-flops used in the state-of-the-art processors. Measurement techniques employed in this work as well as the measurement set-up are discussed in this paper.

CMOS sense amplifier-based flip-flop with two N-C2MOS output latches

By replacing the NAND SR latch at the output stage of a conventional sense amplifier-based flip-flop (SAFF) by two N-C2MOS latches, the operating speed of the flip-flop is enhanced by 63% and the power-delay-product is reduced by 28%.