Semiconductor Wafer Fab Research Articles

Bayesian Optimization for the Vehicle Dwelling Policy in a Semiconductor Wafer Fab

Bayesian Optimization for the Vehicle Dwelling Policy in a Semiconductor Wafer Fab

Ranking routes in semiconductor wafer fabs

We develop a method to estimate the quality of processing routes in a wafer fabrication process. Ranking such routes can be useful for identifying the “best” and “worst” routes when making adjustments to recipes. Route categorization is also useful in developing efficient scheduling algorithms. In particular, we propose a method for ranking routes based on count-based metrics such as the number of defects on a wafer. We start with a statistical model to produce a “local” ranking of a tool and then build a “global” ranking via a heuristic procedure. Creating a fully statistical procedure for ranking routes in semiconductor fabrication plants is virtually impossible, given the number of possible routes and the limited data available. Nonetheless, our discussions with working engineers indicate that even approximate rankings are useful for making better operational decisions.

Data-driven aggregate modeling of a semiconductor wafer fab to predict WIP levels and cycle time distributions

In complex manufacturing systems, such as a semiconductor wafer fabrication facility (wafer fab), it is important to accurately predict cycle times and work-in-progress (WIP) levels. These key performance indicators are commonly predicted using detailed simulation models; however, the detailed simulation models are computationally expensive and have high development and maintenance costs. In this paper, we propose an aggregate modeling approach, where each work area, i.e., a group of functionally similar workstations, in the wafer fab is aggregated into a single-server queueing system. The parameters of the queueing system can be derived directly from arrival and departure data of that work area. To obtain fab-level predictions, our proposed methodology builds a network of aggregate models, where the network represents the entire fab consisting of different work areas. The viability of this method in practice is demonstrated by applying it to a real-world wafer fab. Experiments show that the proposed model can make accurate predictions, but also provide insights into the limitations of aggregate modeling.

Feature Selection for Waiting Time Predictions in Semiconductor Wafer Fabs

Based on real operational data from the Robert Bosch GmbH, we investigate influencing features for waiting time estimation of operations in high product-mix / low-volume semiconductor manufacturing fabs. We define waiting time as the elapsed time between completing the previous operation and starting the next one. In addition to well-established features, we introduce novel features to capture the complexity of the manufacturing environment. To the best of our knowledge, we are the first to attempt waiting time estimation in a high product-mix / low-volume semiconductor fab. We present a framework for feature selection which is composed of three steps: First, random forest models are trained for each operation. Second, a permutation feature importance (PFI) for the full set of features for each operation is computed and the performance is statistically evaluated. The optimal subset of features is then chosen by a sequential backward search based on the PFI values. Third, the performance in terms of the coefficient of determination of each optimized model is evaluated by means of the initial performance. We apply the framework to real operational data from the production areas Lithography and Diffusion and conclude that the feature set can be reduced significantly, while the prediction performance remains equal. The novel features are found to be frequently used when estimating waiting times in the investigated use case.

Optimization of Work-Center Cycle Time Target Setting in a Semiconductor Wafer Fab

In this paper the problem of assigning target cycle times at operation level in a semiconductor wafer fab, where target end-to-end-delays are given, is considered.In the original position allowed waiting times are assigned at processing stations proportional to the square root of processing times. We apply the fairness principle which claims that waiting times should be proportional to processing times at so-called machine resource pools. To match overall cycle time targets the normalization constants are adjusted using LP and QP methods.

Investigation of different inputs and a new release policy in the proposed simulation model for wafer fabrication system

This paper investigates the effect of different inputs on selected performance metrics such as cycle time, WIP level and throughput in the processes of semiconductor wafer fab by developing a simulation model of representative but fictitious semiconductor wafer fab. The different inputs include arrival rate, arrival distribution, processing time, maintenance schedule, operator schedule, batch size, dispatching rule and release policy. Simulation results show that the relationship between inputs and system performance metrics, considered in this study, are extremely complex particularly for the inputs maintenance schedule, operator schedule and batch size. An overall result shows that dispatching rule and closed loop release policy can significamtly improve the performance of wafer fabrication system. However; major improvement comes from closed loop release policy. Accordingly, this paper presents a new closed loop release policy called as constant batch machine workload (CONSTBWL) to improve the performance of wafer fab. The behaviour of CONSTBWL is analysed in combination with dispatching rules using the proposed simulation model for wafer fab. Simulation results show that CONSTBWL policy outperformed traditional release policies in terms of the average cycle time, the work in process (WIP) level and the standard deviation of WIP level under a prescribed throughput level. Furthermore, the analysis of the results indicated that a good shop floor performance can be achieved with a right combination of closed loop release policy and simple dispatching rules with respect to the choice of performance metrics.

Experimental investigation for performance assessment of scheduling policies in semiconductor wafer fabrication—a simulation approach

This paper is concerned with assessing the impact of 15 existing release policies in combination with three dispatching rules (together called as scheduling policy) on the performance of semiconductor fabrication facilities using a simulation model of a representative but fictitious semiconductor wafer fab. The performance criteria employed includes average cycle time, standard deviation of cycle time, work in process (WIP) level, and throughput. Arena simulation software is used to build the simulation model and conduct the experimental study. The experimental results indicate that workload regulating (WR), constant work in process (CONWIP), and constant load (CONLOAD) policies are superior among tested release policies and shortest remaining processing time (SRPT) is the best dispatching rule. This paper present a new release policy called as constant workload (CONSTWL), which is a modified version of CONWIP policy to overcome the limitations of traditional release policies. CONSTWL policy triggers the release of job into the system based on the overall workload of shop floor. Results on computational experiments indicate that CONSTWL outperforms traditional release policies in terms of the average cycle time, the standard deviation of cycle time and work in process under a prescribed throughput level. The positive impact of CONSTWL policy on system performance appears to be reliable with the increase of system congestion level. CONSTWL policy may prove useful in practical contexts of make to stock manufacturing environment whose orders are met usually from finished inventory.

Impact of capacity fluctuation on throughput performance for semiconductor wafer fabrication

• The impact of critical machines’ available time (AT) fluctuation, the level of AT%, and the loading of machine on semiconductor wafer fab's throughput performance have been studied. • A capacity impact analysis approach, based on an object-oriented wafer fab capacity planning and analysis simulation (CPAS) system, has been presented. • The simulation experiment shows that a fab's capacity performance is highly affected by the machines belonging to single machine-multiple layers (SM) machine group, and the level of AT% (i.e., not the AT fluctuation), the fab management staffs should put more attention on the “key” machines’ promised AT. • It is worthy to buy or rent one extra non-critical machine if it did have a serious continuous downtime periods (e.g., more that 7 days) occurred in one month under the situation of medium (e.g., 70%) to high scheduled loading situation. With the characteristics of high capital investment and complicated manufacturing processes, effectively planning and analyzing the available capacity is a crucial challenge in semiconductor industry. However, the fab management staffs usually believe that the ideal planned capacity , generated by static capacity planning approach, is too optimistic to achieve, in particular, many abnormal events (e.g., machine breakdown) occurring in fab are not reasonably considered. Therefore, this paper aims at proposing a capacity impact analysis (CIA) approach based on a reasonable capacity plan generated by an object-oriented capacity planning simulation system. As such it analyzes the impact of the identified critical available time (AT) fluctuation of machines, the level of AT%, and the loading of machine on overall capacity and output performance (e.g., wafer out, utilization, WIP) in a fab. The simulation experiment shows that a capacity performance is highly affected by the machines belonging to a single machine-multiple layers (SM) machine group, and the level of AT% (i.e., not the AT fluctuation). Therefore, fab management staff should put more attention on the promised AT or increasing the level of AT% of the “key” machines to maintain a high throughput.

All Wet Resist Strip for Improved Semiconductor Process and Product Improvement

Conventionally, plasma ash followed by a wet clean has been used to strip implanted photoresists on all semiconductor technology process flows and nodes. This paper describes the theory and implementation of an All Wet Strip (AWS) process at various post implant levels in the process flow, thus eliminating the need for a plasma treatment. Plasma treatment post implants have shown to add product yield limiting defects most likely eliminated by an All Wet Strip (AWS) process; successfully contributing to cycle time, capacity, cost and yield improvement for semiconductor chips. AWS involves the use of a sulfuric acid and hydrogen peroxide mixture for stripping implanted photo resists, the effectiveness of which has a dependency on the ion implant dose, energy and photo resist type. The paper describes the unique challenges that were overcome to bring the concept from an experimental stage to actual implementation, the process integration plus device sensitivities involved in ramping a process, in a volume 300mm semiconductor wafer fab for complex technologies.

Designing a Sustainable and Distributed Generation System for Semiconductor Wafer Fabs

Driven by wind and solar photovoltaics technology, the power industry is shifting towards a distributed generation (DG) paradigm. A key challenge in deploying a renewable DG system is the power volatility. This study proposes a visionary energy concept and further presents a mathematical model that could help the large industry consumers adopt this new energy technology. The study seeks to design a grid-connected DG system that is capable of providing the necessary electricity for wafer fabs. Simulation-based optimization algorithm was applied to determine the equipment type and capacity aiming to minimize the DG lifecycle cost. The proposed method was demonstrated on fab facilitates located in three different regions in the US.

Scheduling of multiple in-line steppers for semiconductor wafer fabs

A few prior studies noticed that an in-line stepper (a bottleneck machine in a semiconductor fab) may have a capacity loss while operated in a low-yield scenario. To alleviate such a capacity loss, some meta-heuristic algorithms for scheduling a single in-line stepper were proposed. Yet, in practice, there are multiple in-line steppers to be scheduled in a fab. This article aims to enhance prior algorithms so as to deal with the scheduling for multiple in-line steppers. Compared to prior studies, this research has to additionally consider how to appropriately allocate jobs to various machines. We enhance prior algorithms by developing a chromosome-decoding scheme which can yield a job-allocation decision for any given chromosome (or job sequence). Seven enhanced versions of meta-heuristic algorithms (genetic algorithm, Tabu, GA–Tabu, simulated annealing, M-MMAX, PACO and particle swarm optimisation) were then proposed and tested. Numerical experiments indicate that the GA–Tabu method outperforms the others. In addition, the lower the process yield, the better is the performance of the GA–Tabu algorithm.

A simulation-based two-stage scheduling methodology for controlling semiconductor wafer fabs

In this paper, we propose an efficient simulation-based two-stage scheduling methodology by integrating vector ordinal optimization (VOO) and response surface methodology (RSM) to make a good scheduling policy for fab operation. The suggested method combines local and global rules into a single rule, with the objective of simultaneously optimizing multiple performance indices. Our approach consists of 2 stages: rule combination selection, and parameter optimization. In the first stage, we apply the VOO techniques to effectively selecting good rule combination. Results show that 1 orders of computation time reduction over traditional simulations can be achieved. In the second stage, we adopt RSM and desirability function to tune the parameters associated to scheduling algorithm. The proposed approach is validated by means of a comparison with other scheduling policies. The results show that the proposed scheduling method is effective.

Optimising the location of crossovers in conveyor-based automated material handling systems in semiconductor wafer fabs

This research presents several heuristics to optimise the location of crossovers in a conveyor-based automated material handling system (AMHS) for a semiconductor wafer fabrication facility. The objective is to determine the location of crossovers that minimises the total cost of the expected work-in-process on the conveyor and the cost of installing and operating the AMHS with the crossovers. The proposed heuristics are integrated with a queuing-based analytical model incorporating practical hardware considerations of the AMHS, such as turntables and crossovers. To illustrate the proposed heuristics’ practical application they are applied to SEMATECH's virtual wafer fabrication facility. Experimental results demonstrate that under a wide variety of operating conditions and cost scenarios the local improvement heuristic is able to identify the optimal solution and outperform other commonly used heuristics for layout design such as genetic algorithms.

A case study on energy saving of the facility systems for 12-inch semiconductor wafer fabs in Taiwan

In recent years, the semiconductor wafer fabs have begun to produce 12-inch wafers instead of 8-inch wafers as the new generation process technology has evolved. The production area increases, and the energy consumption of production buildings is also increased. In a semiconductor fab, besides the processing equipments, the plant facility system consumes most of energy. The facility system contains chilled water systems, outside air supply systems, circulating air systems, exhaust-gas treatment systems, vacuum systems, process cooling water systems, ultra-pure water systems and compressed-air systems. Considering the gradual depletion of energy sources and the soaring energy cost, energy saving has become an important project to high energy consumption semiconductor fabs. Therefore, this paper presents a case study on the energy saving of a clean air conditioning system and facility of 12-inch semiconductor fabs. The energy saving schemes contain four cases: (1) Case 1: The gas consumption of the organic substance processing system of direct firing type is compared with that of regenerative heat recovery type; (2) Case 2: The energy consumption of the cooling tower adopting high and low speed operations is compared with that adopting a frequency converter; (3) Case 3: The low vacuum system of the clean room adopts the phone call system to switch on/off the pump, and (4) Case 4: The make up air unit of the clean room adopts the run around system to recover heat. As for the energy saving efficiency, Case 1 can save NT$9,881,616 of gas cost annually; Case 2 can save NT$2,398,913 annually; Case 3 can save NT$317,004 annually, and Case 4 can save NT$1,738,758 annually. Through the aforementioned four manipulations, 25.24% of the total energy consumption of the corresponding facilities can be saved. Key words: Semiconductor fab, energy consumption, energy saving.

Capacity planning through queueing analysis and simulation-based statistical methods: a case study for semiconductor wafer fabs

This paper presents a comprehensive framework for the strategic capacity expansion of production equipment in semiconductor manufacturing, and the proposed approach is applied to a model of an actual wafer fabrication facility. It is the intention of this work to show that, once intelligently integrated, an analytical queueing model and a numeric computer simulation model can be used synergistically and can lead to a better alternative method than methods restricted to only one of them. The outcome of our methods is a number of good system configurations, each of which is characterised by its cycle time (CT)–throughput (TH) profile. Such profiles fully describe the system's comprehensive performance over a wide range of demand scenarios (involving varying product mix), and hence can be used to thoroughly evaluate alternative configurations in capacity expansion decisions.

A Swarm Intelligence Based Rescheduling Method for Semiconductor Wafer Fabrication Facilities

An effective rescheduling method takes an important role on improving the operational performance of a semiconductor wafer fabrication facility (fabs). In this paper, we propose a rescheduling method based on swarm intelligence. Firstly, we build a swarm intelligence based rescheduling model (SIRM) including an ant queen agent, multiple job ant agents and machine ant agents. Secondly, we design a rescheduling algorithm (CMRA) composed of three sub-algorithms: sub-algorithm-1 is used by an ant queen agent to transfer an existing static optimized scheduling plan into additional pheromones of job ant agents; sub-algorithm-2 and sub-algorithm-3 are used to convert scheduling related real-time information to dynamic pheromones of job ant agents and machine ant agents, respectively. Finally, a simplified semiconductor wafer fab model is used to verify and validate CMRA. The simulation results demonstrate that CMRA is superior to the original scheduling method to generate a static optimized scheduling plan with better performance on move, step and on-time operational due date rate under uncertain production environments.

Optimisation approaches for batch scheduling in semiconductor manufacturing

In this research, several approaches for the optimisation of batch processes are investigated and compared. The motivation for this is the analysis of an oven work centre in a semiconductor wafer fab. Different objectives like keeping operational due dates as well as the minimisation of lot completion time will be optimised with regard to existing process constraints. First, the problem is modelled from two different viewpoints: as scheduling problem and with the help of a simulation system. For this, it used mixed integer programming (MIP) and a discrete event simulation system respectively. As a next step, a MIP time window decomposition approach combining simulation and mathematical programming is discussed. This reduces the complexity of the given problem by solving local sub-problems. Experiments on real manufacturing data determine the optimisation potential for the work centre using the different approaches. This allows, among others, a comparison to dispatching strategies as they are used in the manufacturing line.

A survey of dispatching rules for operational control in wafer fabrication

Production scheduling in semiconductor wafer fabs is a non-trivial task owing to the complexity of wafer fabrication. Dispatching rules are the most commonly used tools for shop floor control in this industry. Over the years, advanced dispatching rules, capable of impacting multiple performance measures and utilising both upstream and downstream information in assigning lot priorities, have been introduced. This article aims to provide an overview of these rules and explores the effectiveness of their performance as they pertain to different areas in a wafer fab. Based on this overview, several future directions on developing new dispatching rules are also proposed.

An Optimization Approach for Semiconductor Wafer Fabrication Scheduling Problem

Due to the increasing scale of scheduling problems, the study is to explore an effective optimize scheduling approach for the semiconductor wafer fab. Semiconductor manufacturing is widely regarded as one of the most complex manufacturing processes in the world. The particular complexity, characterized by reentrant flows, uncertainties, mixed processing styles, etc., leads to a great challenge in its scheduling. Without powerful scheduling techniques it becomes practically impossible to design a manufacturing system. So, by means of a new coding method, and the adaptive mechanism of crossover and mutation, an improved immune algorithm (IA) is presented to solve the scheduling problem. The algorithm is based on clonal selection and affinity maturation for finding optimal solutions. To demonstrate the efficiency of the IA, some numerical experiments are carried out. The results show that the IA will yield a more efficient solution than several other scheduler.

Stochastic programming based capacity planning for semiconductor wafer fab with uncertain demand and capacity

Capacity planning is a challenging problem in semiconductor manufacturing industry due to high uncertainties both in market and manufacturing systems, short product life cycle, and expensive capital invest. To tackle this problem, this paper proposes a scenario-based stochastic programming model which considers demand and capacity uncertainties via scenarios, where the overall equipment efficiency is employed to describe the uncertain capacity for the first time. Based on the decentralized structure of tool procurement, production, stockout, and inventory decision-making processes, recourse approximation strategies are presented with varying degree of information share. The computational experiments show that the resulting tool set is robust enough to cope with the changes in capacity with the expected profits being maximized for different scenarios, and the scheme can generate pretty good solutions in reasonable computational time.