Semiconductor Testing Industry Research Articles

Simultaneous resource portfolio planning under demand and technology uncertainty in the semiconductor testing industry

Abstract One of the most challenging issues for the semiconductor testing industry is how to deal with capacity planning and resource allocation simultaneously under demand and technology uncertainty. In addition, capacity planners require a tradeoff among the costs of resources with different processing technologies, while simultaneously considering resources to manufacture products. The need for exploring better solutions further increases the complexity of the problem. This study focuses on the decisions pertaining to (i) the simultaneous resource portfolio/investment and allocation plan accounting for the hedging tradeoff between the expected profit and risk, (ii) the most profitable orders from pending ones in each time bucket under demand and technology uncertainty, (iii) the algorithm to efficiently solve the stochastic and mixed integer programming problem. Due to the high computational complexity of the problem, this study develops a constraint-satisfaction based genetic algorithm, in conjunction with a chromosome-repair mechanism and sampling procedure, to resolve the above issues simultaneously. The experimental results indicate that the proposed mathematical model can accurately represent the resource portfolio planning problem of the semiconductor testing industry, and the solution algorithm can solve the problem efficiently.

An RFID-based manufacture process control and supply chain management in the semiconductor industry

This study proposed an RFID management information system that integrated three common areas in semiconductor testing industry including inventory flows management, location control in warehouse, and handcar localisation. The main core of this research focused on cassette management in semiconductor test industry. The entire management flow enters the warehouse management from a semiconductor manufacturing company to the semiconductor testing company. Based on RFID readers, tags and RFID middleware, label information where located on each cassette will be passed to the backend information system. Through RFID technology characteristic, this system immediately presents the RFID label information for the user to achieve tracing purpose. The research result unified the RFID and the semiconductor testing system to establish a set of immediate information management system. Through the RFID technology and flows integration, this system reduced the standard warehouse working-hour and increased more efficiency in production line. The enterprise saved the more manpower cost, and information transmission was more transparent between customers and suppliers.

Reliability deployment in distributed manufacturing chains via closed-loop Six Sigma methodology

This paper proposes a Six Sigma based framework to deploy high product reliability commitment in distributed subcontractor manufacturing processes. The study aims to expand the Six Sigma tools in applications, where products are designed and developed under the fast time-to-market requirement. The reliability deployment is driven by two incentives: the customer satisfaction and the reduction of the warranty cost. A closed-loop control mechanism is created between the upper and the lower manufacturing streams to identify and remove the early life failures occurred during the initial system installation. A cross-functional team is formed to implement Six Sigma tools for resolving critical failures arising in the upper manufacturing stream. The ultimate goal is to achieve high product reliability in the shortest time when the product time-to-market is essential for gaining the market share. Finally, the proposed control mechanism is demonstrated on the system designs drawn from the semiconductor testing industry.

CMOS-MEMS piezoresistive force sensor with scanning signal process circuit for vertical probe card

In response to the essential role probe cards play in the semiconductor testing industry, a CMOS-MEMS force sensing devices capable of simultaneously monitoring the probe reacting force and electrical test signals is designed for probe cards. The probe reacting force can assist operators immediately to identify a broken, deformed, or worn-out probe and recognize that the measured electrical signals are erroneous. The debug time and cost of the IC test can therefore be effectively reduced. Array-type CMOS-MEMS force sensors are capable of monitoring the status of vertical probe cards on-line in the case of both die-level and wafer-level applications. The force sensor essentially is a Wheatstone-bridge-based piezoresistive force sensor with a small surface area and can be easily fabricated. It consists of a membrane composed of metal, silicon oxide, and a piezoresistive layer made of polycrystalline silicon. Moreover, as the conventional back-etch process can barely handle the increasingly smaller probe pitch, we use front etching to etch out a cavity under the membrane on the silicon substrate in order to deform the membrane during the post-process. For measuring the output signals of the sensors, on-chip circuits to scan and amplify the output signals of the sensors are integrated in the design process. Furthermore, a finite element method is adopted to analyze the structure of the sensors and to find the optimal piezoresistive sensor design. The TSMC 0.35 μm 2P4M process is used to fabricate the force sensors and the circuits. According to the measurement results, the designed sensor reports a sensitivity of 3.114 mV/N/V while a load-bearing force is 0.0294 N.

A resource portfolio model for equipment investment and allocation of semiconductor testing industry

Profitable but risky semiconductor testing market has led companies in the industry to carefully seek to maximize their profits by developing a proper resource portfolio plan for simultaneously deploying resources and selecting the most profitable orders. Various important factors, such as resource investment alternatives, trade-offs between the price and speed of equipment and capital time value, further increase the complexity of the simultaneous resource portfolio problem. This study develops a simultaneous resource portfolio decision model as a non-linear integer programming, and proposes a genetic algorithm to solve it efficiently. The proposed method is employed in the context of semiconductor testing industry to support decisions regarding equipment investment alternatives (including new equipment procurement, rent and transfer by outsourcing, and phasing outing) for simultaneous resources (such as testers and handlers) and task allocation. Experiments have showed that our approach, in contrast to an optimal solution tool, obtains a near-optimal solution in a relatively short computing time.

A hybrid knowledge discovery model using decision tree and neural network for selecting dispatching rules of a semiconductor final testing factory

One of the most challenging production decisions in the semiconductor testing industry is to select the most appropriate dispatching rule which can be employed on the shop floor to achieve high manufacturing performance against a changing environment. Job dispatching in the semiconductor final testing industry is severely constrained by many resources conflicts and has to fulfil a changing performance required by customers and plant managers. In this study we have developed a hybrid knowledge discovery model, using a combination of a decision tree and a back-propagation neural network, to determine an appropriate dispatching rule using production data with noise information, and to predict its performance. We built an object-oriented simulation model to mimic shop floor activities of a semiconductor testing plant and collected system status and resultant performances of several typical dispatching rules, earliest-due-date (EDD) rule, first-come-first-served rule, and a practical dispatching heuristic taking set-up reduction into consideration. Performances such as work-in-process, set-up overhead, completion time, and tardiness are examined. Experiments have shown that the proposed decision tree found the most suitable dispatching rule given a specific performance measure and system status, and the back propagation neural network then predicted precisely the performance of the selected rule.

Modelling and resolving the joint problem of capacity expansion and allocation with multiple resources and a limited budget in the semiconductor testing industry

In the semiconductor testing process, many resources such as testers, handlers, loadboards and toolings are required to be ready simultaneously so that testing tasks can be conducted. A limited budget under depressed economy enhances the need for exploring better solutions of testing capacity expansion and allocation. However, to maximize profit as planning with multiple resources is very challenging. This study focused on the issues pertaining to the decisions of (1) the type and number of testers that should be invested to deal with forthcoming orders at a semiconductor testing facility under a constrained budget and (2) the allocation of tester capacity for the orders so as to maximize company profit with limited, multiple resources. Owing to the high computational complexity of the problem, the study developed a genetic algorithm to resolve the two issues simultaneously. A mathematical model was developed to formalize the problem and serve as a benchmark for comparison with the proposed algorithm that attacked the same problem more efficiently. Taguchi experimental design was employed to find the most appropriate parameters for the proposed genetic algorithm under a variety of budget set-up. Experimental results indicated that the proposed algorithm was robust enough to budget plans, and its performance approximated closely with that of the mathematical model.