Semiconductor Memory Systems Research Articles

Compact and power efficient SEC-DED codec for computer memory

Frequently, soft errors occur due to striking of radioactive particles in memory cells which reduce the reliability of memory systems. Generally, single error correction-double error detection (SEC-DED) codes are employed to detect and correct the soft errors in semiconductor memory systems. In this paper, a new optimization algorithm is proposed based on common sub-expression elimination method. By employing this proposed optimization algorithm, more simplified expressions for encoder and decoder are obtained from parity check matrix (H-matrix). Proposed optimization technique has been used to implement seven different SEC-DED codecs with message length of 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, 256 bits and 512 bits. Compact design requires at most 21.66% lesser number of two-input XOR gates compared to related SEC-DED codes. All codec architectures are simulated and synthesized using both FPGA and ASIC platforms. Area and power consumption of proposed designs are reduced compared to the existing design without affecting its speed. Proposed designs are beneficial in computer memory systems due to its compactness and lower power consumption.

An identity between the m-spotty weight enumerators of a linear code and its dual

The m-spotty byte error control codes provide a good source for detecting and correcting errors in semiconductor memory systems using high density RAM chips with wide I/O data (e.g. 8, 16, or 32 bits). m-spotty byte error control codes are very suitable for burst correction. Here, we introduce the m-spotty weights and m-spotty weight enumerator of linear codes over the ring F_2+uF_2 and prove a MacWilliams type identity.

MacWilliams Identity for M-Spotty Weight Enumerator

M-spotty byte error control codes are very effective for correcting/detecting errors in semiconductor memory systems that employ recent high-density RAM chips with wide I/O data (e.g., 8, 16, or 32 bits). In this case, the width of the I/O data is one byte. A spotty byte error is defined as random t-bit errors within a byte of length b bits, where 1 ≤ t < b. Then, an error is called an m-spotty byte error if at least one spotty byte error is present in a byte. M-spotty byte error control codes are characterized by the m-spotty distance, which includes the Hamming distance as a special case for t = 1 or t = b. The Mac Williams identity provides the relationship between the weight distribution of a code and that of its dual code. The present paper presents the Mac Williams identity for the m-spotty weight enumerator of m-spotty byte error control codes. In addition, the present paper clarifies that the indicated identity includes the Mac Williams identity for the Hamming weight enumerator as a special case.

MacWilliams identity for [formula omitted]-spotty Lee weight enumerators

It is a well established fact that m -spotty byte error control codes provide a good source for detecting and correcting errors in semiconductor memory systems using high-density RAM chips with wide I/O data (e.g. 8, 16 or 32 bits). Recently, a MacWilliams identity that establishes an important relation between an m -spotty weight enumerator of a binary code and its dual has been proven in Kazuyoshi Suzuki et al. (2007) [5]. In this paper, we introduce the m -spotty Lee weights and the m -spotty Lee weight enumerator of a quaternary code and prove a MacWilliams type identity.

Complex M-Spotty Byte Error Control Codes

Spotty byte error control codes are very effective for correcting / detecting errors in semiconductor memory systems using recent high-density RAM chips with wide I/O data, e.g., 8, 16, or 32 bits. A spotty byte error is defined as t-bit errors within a byte of length b-bit, where 1 ≤ t ≤ b, and denoted as t/b-error. This paper proposes a new error model of two spotty byte errors occurring simultaneously, i.e., t/b-error and t'/b-error, where t ≠ t', called complex spotty byte errors. This paper presents two complex m-spotty byte error control codes, i.e., St/bEC-(St/b+St'/b)ED codes which correct all single t/b-errors and detect both t/b-errors and t'/b-errors simultaneously, and (St/b+St'/b)EC codes which correct both single t/b-errors and single t'/b-errors simultaneously. This paper also presents practical examples of the codes with parameter t' = 1, that is, St/bEC-(St/b+S)ED codes and (St/b+S) EC codes which require smaller check-bit length than the existing Single t/b-error Correcting and Double t/b-error Detecting (St/bEC-Dt/bED) codes and the Double t/b-error Correcting (Dt/bEC) codes, respectively.

Parallel decoding for burst error control codes

AbstractIt is well known that sequential decoding methods for burst error control codes use Linear Feedback Shift Registers (LFSR). However, a parallel decoding method employing only combinational logic is preferable in certain applications, such as semiconductor memory systems and holographic memory systems, where a huge amount of data needs to be read or written at ultrahigh speed. This paper proposes a parallel decoding method for linear burst error control codes including the Fire code. In order to obtain the error pattern, this decoding method uses an inverse matrix of a nonsingular matrix which includes a sub‐matrix of the parity check matrix. Burst error correction is possible because correct burst error patterns are obtained only from frames that completely include the burst error pattern. Furthermore, this decoding method can also be applied to single byte error correcting codes with less hardware. The implementation of decoding circuits for burst and byte error control codes are illustrated in this paper. And their hardware complexity is also evaluated to show that the proposed method requires less hardware than the existing parallel decoding method. Finally, we will discuss about how the proposed decoding method can be extended to correct multiple burst or byte errors. © 2003 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 87(1): 38–48, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.10094

A class of error control codes for byte organized memory systems-SbEC-(Sb+S)ED codes

A new class of error control codes, single byte error correcting and single byte plus single bit error detecting codes, are presented. The codes are suitable for semiconductor memory systems organized in a b-bit-per-chip manner, b/spl ges/2, and more efficient than previously known codes with as strong error control capabilities.

Centralized system level redundancy scheme for large‐capacity memory systems

AbstractTo cope with the deterioration of the yield of the memory LSI due to the microstructured design, this paper considers the centralized system‐level redundancy scheme, where, by providing the spare memory chip and the rescue control circuit to the semiconductor memory system, the fault is rescued in a centralized way. In this scheme, the fault bits are memorized in the nonvolatile memory for each word/bit line, and the normal and the spare memories are switched at the I/O terminal of the system by the parallel access.As the method of access to the spare memory, this paper proposes the indirect address input method, where the external address is converted by the control circuit, and the direct address input method, where the external address is directly used. In the former, the external address is converted into the internal address and the ratio of the spare memory to the normal memory decreases with the increase of the system scale, which is favorable to low‐cost applications.The method is applied to the 20‐Mbit file memory using partially good 1 MSRAM, and it is verified that the defect word/bit lines of up to 35 line/chip can be rescued, thereby improving the yield by approximately three times.In the latter method, the addresses to the normal and the spare memories are input simultaneously in parallel, which is favorable for the high‐speed operation. This method is applied to the 4‐Mbit memory module using partially good 4 MDRAM and it is verified that the defect can be rescued while minimizing the deterioration of the access time.

A class of SEC‐DED‐SBED codes for semiconductor memory

AbstractThe SEC‐DED‐SbED code is capable of correcting a single‐bit eror, detecting a random double‐bit error and detecting a b‐bit block error. It is expected to be widely used for highly reliable semiconductor memory systems composed of memory devices with b‐bit output.In this paper a new theoretical construction method for SEC‐DED‐SbED codes is proposed. The proposed class of codes is so characterized that, with byte length b, it is constructed from conventional SEC‐DED‐SbED codes of byte length b/2 and the weight of the column vector of its parity check matrix H (the number of l's) is odd. The bit length n of the code is given as n _ b2(r‐b) . r/2Cb/2 bits, when the check bit length r and the byte length b are even. It has the longest bit length among the known code classes in a large range of byte lengths.

SbEC‐DbED codes derived from experiments on a computer for semiconductor memory systems

AbstractSingle byte (= b bits) error‐correcting and double byte error‐detecting (SbEC‐DbED) codes are useful for semiconductor memory systems with memory chips of b‐bit output per one address. In this paper, codes with information length k up to k = 128 bit for 2 b 8 are derived experimentally using a computer. As a result, codes with longer code lengths than before are obtained. In particular, as for the codes of b = 2 and k = 64, 12 check bits were required in the conventional codes, but the codes requiring only 10 check bits are derived by experiments and are an excellent result from a practical viewpoint too. In the derivation, each column in an H matrix of the code is regarded as an element in a Galois field GF (qr) where q = 2b (b is the number of bits in a byte) and r is the number of check bytes. to obtain codes with large code length, as many elements as possible are selected in GF(qr) satisfying the code condition. Here, a subset in a GF(qr) whose elements are linearly independent, is used to select the columns of the H matrix. Moreover, all the elements of GF(qr) arising as operation results in the derivation process can be in correspondence to the elements of the subset. Consequently, the objective sets are restricted and the derivation through computer experiments is facilitated.

Lifetime analyses of error-control coded semiconductor RAM systems

The paper is concerned with developing quantitative results on the lifetime of coded random-access semiconductor memory systems. Although individual RAM chips are highly reliable, when large numbers of chips are combined to form a large memory system, the reliability may not be sufficiently high for the given application. In this case, error-correction coding is used to improve the reliability and hence the lifetime of the system. Formulas are developed which will enable the system designer to calculate the improvement in lifetime (over an uncoded system) for any particular coding scheme and size of memory. This will enable the designer to see if a particular memory system gives the required reliability, in terms of hours of lifetime, for the particular application. In addition, the designer will be able to calculate the percentage of identical systems that will, on average, last a given length of time.

A military grade 1024-bit nonvolatile semiconductor RAM

The performance and use of a unique metal nitride oxide semiconductor (MNOS) nonvolatile random access memory (RAM) designed and fabricated by the Sperry Univac Semiconductor Facility in St. Paul, MN, are presented. Chip operation and characteristics are described which make this device, called the SU110, suitable for a broad range of applications over a range of write times, retention times, and temperature. An example is given of a 2K word by 8-bit nonvolatile semiconductor memory system building block using the SU110.

Biotelemetry of the glomerular filtration rate (GFR) in man by external detection of DTPA-(Sn)- 99mTc with CdTe detectors

With a small cadmium telluride detector fixed to the skin surface, the kidney function [glomerular filtration rate (GFR)] can be determined in man from the disappearance rate of i.v. injected DTPA-(Sn)- 99mTc monitored in a three hour period and just one blood sample. The small (2–3 mm 3) p-type CdTe-crystals (developed by C.R.N., Strasboug, Frnace) grown by the THM-method, without external chemical compensation have a resistivity of 10 4–10 6 ω· cm. The combination of CdTe detectors and portable recording media like tape-cassette recorders or semiconductor memory systems (CMOS), constitutes the biotelemetry equipment, which can be used in the clinical routine or in studies of the kidney function in ambulant patients during different physiological conditions. The method and some studies will be presented.

Synthesis and Analysis of a Cost Effective, Ultrareliable, High Speed, Semiconductor Memory System

This paper provides a detailed synthesis and analysis of a cost effective, ultrareliable, high speed, semiconductor memory system. The memory system has the capability of detecting and correcting over 99% of all single faults. The memory cycle time of 250 ns is not compromised unless a fault is encountered. The increase in circuitry for the fault-tolerent system, over the simplex system, is less than 20%. These results have been achieved through the use of special coding implementations, virtual codes, and selective redundance.

Synthesis and analysis of a cost-effective, ultrareliable, high speed, semiconductor memory system : E. W. Husband and S. A. Szygenda. IEEE Trans. Reliab.R-25 (3), 217 (August 1976)

Synthesis and analysis of a cost-effective, ultrareliable, high speed, semiconductor memory system : E. W. Husband and S. A. Szygenda. IEEE Trans. Reliab.R-25 (3), 217 (August 1976)

Microcomputer reliability improvement using triple-modular redundancy

Triple-modular redundancy (TMR) is a classical technique for improving the reliability of digital systems. However, applying TMR to microcomputer systems may not improve overall system reliability because voter circuits may contribute as much to system unreliability as the microprocessors themselves. We examine the issues that affect the effectiveness of TMR for transient recovery and the reliability of semiconductor memory systems. With careful application, TMR can improve the mission time of a small system by a factor of 3 or more.