Semiconductor Device Technology Research Articles

Semiconductor device fabrication technology GaN HEMT for RF power amplifier– current capabilities and future perspective

The demand of Gallium Nitride based semiconductor device technology as compared to others has been increased dramatically in past few years and number of devices has been manufactured for use in RF applications. This Paper encapsulates technology overview, unique features, current capabilities and future perspective of GaN HEMT device. GaN HEMT device technology performance is characterized by high efficiency, high power and wide bandwidth operation. The paper summarize with the quantitative comparison of device technologies in terms of performancemetrics of PA.

Back-Channel Defect Termination by Sulfur for p-Channel Cu2O Thin-Film Transistors.

The absence of a high-performance p-channel oxide thin-film transistor (TFT) is the major challenge faced in the current oxide semiconductor device technology. Simple solution-based back-channel subgap defect termination using sulfur was developed for p-channel cuprous oxide (Cu2O)-TFTs. We investigated the origin of poor device characteristics in conventional Cu2O-TFTs and clarified that it was mainly because of a back-channel donor-like defect of ∼2.8 ×1013 cm-2 eV-1, which originated from the interstitial Cu defect. Sulfur ion treatment using thiourea effectively reduced the back-channel defect down to <3 × 1012 cm-2 eV-1 and demonstrated the Cu2O-TFT with a saturation mobility of 1.38 ± 0.7 cm2 V-1 s-1, a s-value of 2.35 ± 1.22 V decade-1, and an on/off current ratio of ∼4.1 × 106. The improvement of device characteristics was attributed to the reduction of back-channel defect by the formation of a thin CuSO4 back-channel passivation layer by the chemical reaction of interstitial Cu with S and O ions. An oxide-based complementary inverter using a p-channel Cu2O-TFT and a n-channel a-In-Ga-Zn-O-TFT was demonstrated with a high voltage gain of ∼230 at VDD = 70 V.

THE FEATURES OF SCANNING LIQUID PHASE EPITAXY TECHNIQUE AS APPLIED TO THICK EPITAXIAL LAYERS GROWTH

Background. Growing of both thin and thick epitaxial layers is an essential part of semiconductor device technology. Liquid phase epitaxy is among well-known technological methods. There are pulse methods of liquid phase epitaxy specially developed for obtaining thin epitaxial layers. Their adaptation or modification for obtaining thick epitaxial layers is an actual issue.Objective. This work deals with the possibility of obtaining of thick epitaxial layers by extending the capabilities of scanning liquid phase epitaxy technique which also relates to pulse liquid phase growing methods.Methods. In this work we considered the influence of extra heating of the substrate on the growth of epitaxial layers when using scanning liquid phase epitaxy technique. For this purpose we carried out modelling of heat- and mass transport processes in the apparatus of scanning liquid phase epitaxy in conditions of extra heating of the substrate. To experimentally approve the validity of the model proposed we carried out the growing of Ge epitaxial layer on GaAs substrate in the above mentioned conditions.Results. The modelling showed that if the substrate was in contact with the solution-melt more than 1 second in conditions of substrate extra heating in scanning liquid phase epitaxy method, a segment of epitaxial layer dissolution appeared in plots of the grown epitaxial layer thickness against the growth time. The crystallization front temperature was lower than the initial solution-melt temperature in this case. We showed that it was connected with the magnitude of initial cooling/heating of the substrate heater. The modelling also showed that the epitaxial layer growth occurred in kind of a temperature gradient due to the extra substrate heating. Thus in a few seconds there took place the growth in the time-constant temperature gradient. Using the extra substrate heating we obtained epitaxial Ge layer on GaAs substrate from Ga-Ge solution-melt. The growth time was 60 sec. The layer thickness determined by spherical slice technique was 12.6 um.Conclusions. In this work we showed that using extra heating of the substrate’s back side there appeared the conditions for growing of thick epitaxial layers by scanning liquid phase epitaxy technique in case when the substrate temperature was lower than the solution-melt temperature. Here the growth of thick epitaxial layers took place in the condition of temperature gradient at crystallization front.

Nanoparticle meta-grid for enhanced light extraction from light-emitting devices

Based on a developed theory, we show that introducing a meta-grid of sub-wavelength-sized plasmonic nanoparticles (NPs) into existing semiconductor light-emitting-devices (LEDs) can lead to enhanced transmission of light across the LED-chip/encapsulant interface. This results from destructive interference between light reflected from the chip/encapsulant interface and light reflected by the NP meta-grid, which conspicuously increase the efficiency of light extraction from LEDs. The “meta-grid”, should be inserted on top of a conventional LED chip within its usual encapsulating packaging. As described by the theory, the nanoparticle composition, size, interparticle spacing, and distance from the LED-chip surface can be tailored to facilitate maximal transmission of light emitted from the chip into its encapsulating layer by reducing the Fresnel loss. The analysis shows that transmission across a typical LED-chip/encapsulant interface at the peak emission wavelength can be boosted up to ~99%, which is otherwise mere ~84% at normal incidence. The scheme could provide improved transmission within the photon escape cone over the entire emission spectrum of an LED. This would benefit energy saving, in addition to increasing the lifetime of LEDs by reducing heating. Potentially, the scheme will be easy to implement and adopt into existing semiconductor-device technologies, and it can be used separately or in conjunction with other methods for mitigating the critical angle loss in LEDs.

A Density Metric for Semiconductor Technology [Point of View

Since its inception, the semiconductor industry has used a physical dimension (the minimum gate length of a transistor) as a means to gauge continuous technology advancement. This metric is all but obsolete today. As a replacement, we propose a density metric, which aims to capture how advances in semiconductor device technologies enable system-level benefits. The proposed metric can be used to gauge advances in future generations of semi-conductor technologies in a holistic way, by accounting for the progress in logic, memory, and packaging/integration technologies simultaneously.

Features of the receiving of piezoelectric thin films by plasma spraying of powdery AlN

Оne of the promising materials in solid state electronics is the AlN compound. A wide range of semiconductor devices are produced from it, such as photodetectors, LEDs, piezoelectric converters, etc. But the widespread use of products based on AlN prevents low manufacturability designs based on it. In this regard, the development of new technologies for the production of devices based on AlN is relevant. The work is devoted to the study of thin AlN films obtained by plasma spraying from AlN powder. The review of existing technologies of production of thin films AlN is carried out. Their advantages and disadvantages are discussed. Information on the modernization of the VUP-5 installation, which allowed to spray the AlN film from the powdered state, is given. One of the significant advantages of the process developed in this work is that the substrate is heated to temperatures no higher than 300 oC, which in turn allows to combine this technology with the technology of silicon semiconductor devices. As a result, films with a thickness of 200 nm on various substrates were obtained and their surface structure was studied. It is shown that AlN films deposited on single crystal substrates such as diamond and silicon have the least roughness, while films on sitall have the worst roughness. The transmission spectra of the obtained AlN films were investigated by IR spectroscopy. With their help, it was shown that a polycrystalline AlN layer oriented in the crystallographic direction 002 is formed on the substrate. The piezoelectric properties of the obtained films were investigated by scanning probe microscopy. It is shown that their piezoelectric coefficient d 33 is 60% of the value for a single-domain single-crystal sample for a diamond substrate, which indicates a sufficiently high quality of the resulting film. It is concluded that, although the quality of the layers strongly depends on the substrate, nevertheless, they exhibit a significant piezoelectric effect, which allows the use of this method for the manufacture of piezoelectric sensors, ultrasonic emitters, etc.

Understanding and optimizing EBIC pn-junction characterization from modeling insights

In this paper, the physical mechanisms involved in electron-beam-induced current (EBIC) imaging of semiconductor pn-junctions are reviewed to propose a model and optimize the acquisition of experimental data. Insights are drawn on the dependence of the EBIC signal with electron accelerating voltage and surface conditions. It is concluded that improvements in the resolution of EBIC are possible when the surface conditions of the specimens are carefully considered and optimized. A lower accelerating voltage and an increase of the surface recombination velocities are quantitatively shown to maximize the EBIC lateral resolution in locating the pn-junction. The effect of surface band bending is included in the model, and it is seen to primarily affect the surface recombination. Introducing controlled surface damage is shown as a potential method for resolution enhancement via focused ion beam milling with Ga+ ions. These findings contribute to the understanding of this technique and can produce further improvements to its application in semiconductor device technology.

Development of a fast atom beam gun for surface-activated bonding

Surface-activated bonding (SAB), also called room-temperature bonding, is used in three-dimensional integration technology for semiconductor devices. An Ar fast atom beam (FAB) is used for SAB. However, conventional FAB guns must be replaced after hundreds of minutes of irradiation because carbon abrasion powders are generated by Ar ions sputtering in the gun. Therefore, this study develops a novel FAB gun with improved lifetime. The proposed FAB gun applies magnetic fields to guide Ar ions to reduce sputtering in the gun and improve irradiation efficiency. The proposed FAB gun indicates the possibility of improving gun lifetime.

Robustness and reliability review of Si and SiC FET devices for more-electric-aircraft applications

Increased electrification of traditionally hydraulic and pneumatic functions on aircrafts has put power electronics at the heart of modern aviation. Aircraft electrical power systems have traditionally operated at 115 V AC and 28 V DC with a constant speed generator and transformer rectifier units converting jet engine power into electrical power. However, due to the increasing trend towards the More Electric Aircraft (MEA), 270 V DC systems are likely in the future. This calls into question, the power semiconductor device technology that enables the on-board power converters needed for electro-mechanical actuation as well as solid-state circuit breakers for system protection. Silicon IGBTs have been the work-horse of power electronics, but as switching speeds increase due to the need for high frequency operation, the bipolar nature of IGBT tail currents become a limiting factor for improved energy conversion efficiency. A number of unipolar FET technologies, including SiC trench MOSFETs, SiC planar MOSFETs, silicon super-junction MOSFETs and SiC JFETs in cascode with a low voltage Si MOSFET, have become commercialized at around 650 V. However, reliability and robustness, especially against single event burn-out and/or single event gate rupture is critical. This paper experimentally investigates the performance of the listed FET devices under Unclamped Inductive Switching and Bias Temperature Instability/gate oxide stress tests.

Enhanced Open Innovation: CMP Innovation to Open New Paradigm

The history of miniaturization of semiconductors, which has been supported by Dennard's theory and developed in accordance with Moore's law, has entered the new era of Å, and the market is expected to grow explosively beyond the conventional market mechanisms. Semiconductor technology has always faced developing technical challenges, each of which has been overcome by a newly proposed innovation. Even now, a sense of stagnation about the future technology is pervasive. On the other hand, the market is expected to grow explosively due to a shift from single driver technology, including PCs and mobile phones, to multi-driver technology including ICAC5 (IoT, cloud, AI, cars, and 5G). This paper covers a method of development through Enhanced Open Innovation, which is an advanced form of Open Innovation, as a method for overcoming the sense of stagnation about the future technology and responding to the explosively growing market. In preparation for the paradigm revolution of semiconductors that is expected to occur in 2030, CMP needs to be advanced in terms of hardware as well as software. Manabu's principle “Semiconductor device technology is immortal as long as there are human desires” is about to be proved.

International Congress on Semiconductor Materials and Devices

Abstract 2nd International Congress on Semiconductor Materials and Devices (ICSMD-2018) was held in Ardahan, Turkey, at Ardahan University between the 28th and 30th of August 2018. The main aim of the congress was to bring together researchers from both academic and industrial community, working in the field of semiconductor science and technology, and to promote the exchange of their ideas and results, as well as to foster collaboration between them. The scientific topic of the congress spanned a broad range of research fields on 1) Semiconductor Materials and Devices, 2) Thin Films: Surface and Interface, 3) Nanofabrication, Nanotubes, and Nanowires, 4) Photonic Devices and Sensors, 5) Organic Semiconductors and Devices, 6) Magnetic Semiconductors, 7) Biological Applications of Semiconductors, 8) Computational Methods Applied to Semiconductor Materials. There were about 200 national and international participants comprised of university students, academicians, and experts from the industry. A total of 94 oral presentations, including 10 invited speakers, were given and about 39 posters were presented. The presentations mostly gave a critical assessment of existing work and future directions in semiconductor growth and device technology, including materials characterization and device fabrication processes, growth of semiconductors, photovoltaic materials, Schottky barrier diodes and hybrid organic/inorganic semiconductor devices. This special issue of Materials Today: Proceedings features 33 peer-reviewed articles which provide a general overview of topics in the field of semiconductor materials and devices discussed in ICSMD-2018. The guest editors are thankful to all the participants, and all the authors who contributed their time and effort submitting their excellent and extended works to the present special issue. The guest editors would also like to thank all the reviewers for their valuable comments and suggestions to the authors on improving the quality of the papers.

The Figure of Merit of a Semiconductor Power Electronics Switch

The figure of merit (FOM) of a semiconductor device represents an important quality as it pertains to its performance limits and is often used to drive the technology development in a specific direction. Comparing the performances of switching power MOSFETs using their FOMs has become ubiquitous practice in power semiconductor and power electronics industries. In this paper, a critical review of the proposed power MOSFET FOMs is presented, and key limitations are discussed. It is shown that the quality factor Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F2</sub> = (λE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> /R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> ) along with Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> and Tjmax may be used to guide the development of future generations of power semiconductor device technologies for power electronics switching applications, where λ and Ec are the thermal conductivity and critical electric field strength for the avalanche breakdown of the semiconductor material, respectively, RON,sp is the specific on-state electrical resistance, Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> is the gate charge, and T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">jmax</sub> is the maximum junction temperature of the semiconductor power device, respectively.

Prototype of KIOSK Data Downloading System at 300 GHz: Design, Technical Feasibility, and Results

Recent advances in semiconductor device technologies and the ever growing worldwide traffic explosion have focused great attention on THz frequencies, which had long been considered a forbidden region in the electromagnetic spectrum. The huge bandwidth, perhaps much larger than the total bandwidth used on Earth for all wireless systems, is now believed to be the only way to handle incredibly large amounts of data instantaneously by wireless means. In this article, we describe the development of a KIOSK data downloading system prototype designed for touch-and-go use. Implementation of the 300 GHz THz front-end components and the performance are briefly summarized. A preliminary investigation of the LoS channel responses and a simple comparison of the forward error correction algorithms in the given THz channel are presented as well. Finally, an experimental demonstration of instant data transfer with the prototype is described to confirm the feasibility of using the THz wave band for future wireless applications.

Exploration of the Infrared Sensitivity for a ZnSe Electrode of an IR Image Converter

Significant improvement has been carried out in the field of the II–VI group semiconductor device technology. Semiconductors based on the II–VI group are attractive due to their alternative uses for thermal imaging systems and photonic applications. This study focuses on experimental work on the optical, electrical and structural characterization of an infrared (IR) photodetector zinc selenide (ZnSe). In addition, the IR sensitivity of the ZnSe has primarily been investigated by exploiting the IR responses of the material for various gas pressures, p, and interelectrode distances, d, in the IR converter. The experimental findings include the results of plasma current and plasma discharge emission under various illumination conditions in the IR region. The electron density distributions inside the gas discharge gap have also been simulated in two-dimensional media. Experimentally, the current–voltage, current–time, and discharge light emission plots are produced for a wide experimental parameter range. Consequently, the structural and optical properties have been studied through atomic force microscopy and Fourier-transform infrared spectroscopy techniques to obtain a comprehensive knowledge of the material.

The Correlation Between the Preferred Orientation and Al Distribution of Al-Doped HfO2 Films by Plasma-Enhanced Atomic Layer Deposition

This research was mainly supported by the Global Frontier R&D Program (2013M3A6B1078874) on Center for Hybrid Interface Materials (HIM) funded by the Ministry of Science, ICT & Future Planning, Republic of Korea, and partially supported by the Future Semiconductor Device Technology Development Program (10067739) funded by Ministry of Trade, Industry & Energy (MOTIE) and Korea Semiconductor Research Consortium (KSRC), and this study has been conducted with the support of the Korea Institute of Industrial Technology development project (KITECH EO-18-0022). The first two authors (Da-Young Kim and Jaeho Jang) contributed equally to this paper.

A fluorometric skin-interfaced microfluidic device and smartphone imaging module for in situ quantitative analysis of sweat chemistry.

The rich composition of solutes and metabolites in sweat and its relative ease of collection upon excretion from skin pores make this class of biofluid an attractive candidate for point of care analysis. Wearable technologies that combine electrochemical sensors with conventional or emerging semiconductor device technologies offer valuable capabilities in sweat sensing, but they are limited to assays that support amperometric, potentiometric, and colorimetric analyses. Here, we present a complementary approach that exploits fluorometric sensing modalities integrated into a soft, skin-interfaced microfluidic system which, when paired with a simple smartphone-based imaging module, allows for in situ measurement of important biomarkers in sweat. A network array of microchannels and a collection of microreservoirs pre-filled with fluorescent probes that selectively react with target analytes in sweat (e.g. probes), enable quantitative, rapid analysis. Field studies on human subjects demonstrate the ability to measure the concentrations of chloride, sodium and zinc in sweat, with accuracy that matches that of conventional laboratory techniques. The results highlight the versatility of advanced fluorescent-based imaging modalities in body-worn sweat microfluidics platforms, and they suggest some practical potential for these ideas.

An Ultrathin Single Crystalline Relaxor Ferroelectric Integrated on a High Mobility Semiconductor.

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, the integration of gate materials that enable nonvolatile or hysteretic functionality in field-effect transistors could lead to device technologies that consume less power or allow for novel modalities in computing. Here we present electrical characterization of ultrathin single crystalline SrZrxTi1-xO3 (x = 0.7) films epitaxially grown on a high mobility semiconductor, Ge. Epitaxial films of SrZrxTi1-xO3 exhibit relaxor behavior, characterized by a hysteretic polarization that can modulate the surface potential of Ge. We find that gate layers as thin as 5 nm corresponding to an equivalent-oxide thickness of just 1.0 nm exhibit a ∼2 V hysteretic window in the capacitance-voltage characteristics. The development of hysteretic metal-oxide-semiconductor capacitors with nanoscale gate thicknesses opens new vistas for nanoelectronic devices.

Three fundamental devices in one: a reconfigurable multifunctional device in two-dimensional WSe2

The three pillars of semiconductor device technologies are (1) the p–n diode, (2) the metal-oxide-semiconductor field-effect transistor and (3) the bipolar junction transistor. They have enabled the unprecedented growth in the field of information technology that we see today. Until recently, the technological revolution for better, faster and more efficient devices has been governed by scaling down the device dimensions following Moore’s Law. With the slowing of Moore’s law, there is a need for alternative materials and computing technologies that can continue the advancement in functionality. Here, we describe a single, dynamically reconfigurable device that implements these three fundamental device functions. The device uses buried gates to achieve n- and p-channels and fits into a larger effort to develop devices with enhanced functionalities, including logic functions, over device scaling. As they are all surface conducting devices, we use one material parameter, the interface trap density of states, to describe the key figure-of-merit of each device.

Si太陽電池製作とエネルギー変換効率シミュレーションを利用した半導体教育の実践

In higher education institutions such as universities and colleges of technology, practical and theoretical education of semiconductor devices is required. Therefore, we introduce a silicon (Si) solar cell fabrication into student experiment to make them understand the pn junction as a basis of semiconductor devices. Furthermore, spectral response characteristic measurement using light emitting diodes (LED) and energy conversion efficiency simulation of the solar cell are introduced into the student experiment to make them understand the relation between light energy and energy band gap, and the function of minority carriers. We verify the effectiveness of introducing these experiments by conducting examination and questionnaire before and after the experiment.

Removal of Bull’s Eye Signature by Optimizing Wet Cleans Recipe

As the semiconductor device technology is moving toward increasingly smaller nodes, it is becoming more challenging to keep the wafers free from contamination of even smaller particles. Wet cleaning process takes a major role in keeping the wafers clean, especially in post-RIE cleans. However, as every other process, wet cleaning also contributes some defects as adders which can potentially cause significant yield killer defects. A cluster of defects, classified as incomplete etch, was observed at the center of the wafer with a wet clean recipe (CIP1) since the adders from this recipe were not allowing the etch process and rendering incomplete etch defects. In this work, we optimized this CIP1 recipe to eliminate defects with the bull’s eye signature at the wafer center and widened the process window of this type of wet cleaning process. The new recipe (CIP2) showed 100% success rate while CIP1 recipe had an occurrence of 35% failure for the bull’s eye signature on the similar quality and quantity of wafers.