Semiconductor Chip Manufacturing Research Articles

Bonding structure and dry etching characteristics in amorphous B–C–N films for hardmask applications

The etch selectivity of the hardmask layer in lithography process for semiconductor chip manufacturing is being continually improved through the utilization of single-element introduction in amorphous carbon (a-C) matrix. Because the exploration of ternary hardmask systems is lacking, we analyzed the bonding structure and dry etching characteristics of a hardmask composed of a ternary system by combining Boron (B) and Nitrogen (N), which are widely used in single-element addition in a-C films. Amorphous B–C–N (a-BCN) hardmasks were obtained by adjusting the N content in an amorphous boron-carbon film using the DC sputter process. The differences in N content within the a-BCN hardmask before and after dry etching were characterized through X-ray reflectometry (XRR) and X-ray photoelectron spectroscopy (XPS) analyses. Consequently, an increase in the ratio of B–N and C–N bonds and a decrease in film density were observed in the pre-etched film. Furthermore, we identified that etch selectivity is related to changes in B–C bonds and C–C sp2 bonds in the post-etched residual film. Additionally, density functional theory (DFT) calculations confirmed an increase in the binding energy between C atoms within the film and etchant, F, influenced by N within the film. This revealed that N in ternary systems not only deteriorates physical density, as known from previous binary hardmask research, but also chemically promotes etch reactions. In our paper, we elucidate the aspects regarding the relationship between the etchant F and C that should be considered when designing ternary hardmask systems.

DSCU-Net: MEMS Defect Detection Using Dense Skip-Connection U-Net

With the rapid development of intelligent manufacturing and electronic information technology, integrated circuits play a vital role in high-end chips. The semiconductor chip manufacturing process requires precise operation and strict control to ensure chip quality. The traditional manual visual inspection method has a high workforce cost and intense subjectivity and is accompanied by a high level of misdetection and leakage. Computer vision-based wafer defect detection technology is gaining popularity in the industry. However, previous methods still find it challenging to meet the production requirements regarding accuracy. To solve the problem, we propose a defect detection network based on a coding and decoding structure, Dense Skip-Connection U-Net (DSCU-Net), which optimizes the skip connection between the encoder and decoder and enhances the profound fusion of high-level semantics and low-level semantics to improve accuracy. To verify the effectiveness of DSCU-Net, we validate it in actual microelectromechanical systems (MEMS) data, and the results show that DSCU-Net reaches an optimal level. Therefore, the DSCU-Net proposed in this paper effectively solves the defect detection problem in semiconductor chip manufacturing. This method reduces workforce cost and subjectivity interference and improves inspection efficiency and accuracy. It will help to promote further development in the field of intelligent manufacturing and electronic information technology.

The Chalkboard: An Introduction to Electrochemical Separations

Chemical separations are a cornerstone of industrial manufacturing processes that generate products and services that have improved the standard of living for humans across the globe. To give some context as to how ubiquitous separations are in the modern world, they are involved in the production of fuels, medicines, clean water, fertilizers, materials used in semiconductor chip manufacturing, and other goods. A 2019 report by the National Academies of Sciences, Engineering, and Medicine highlights that chemical separations account for about 10 to 15% of energy use in the United States. Of the four broad sectors (residential, transportation, industry, and commerce) that use energy in the United States, industry has the largest use at 32% and about half of the energy use in industry hails from separations. It is likely that the transportation and residential sectors will experience significant decarbonization in the next 25 years with the proliferation of wind and solar energy sources coupled with electrochemical energy storage and electrification of vehicles. Industrial decarbonization, on the other hand, is far more complex and challenging and it is imperative that future engineers and scientists work hard to devise alternative processes that can be powered on renewable electrons while generating little waste to produce the goods and services that make up our modern lives.

Evolution of Maskless Digital Lithography: Game changer for Advanced Semiconductor Packaging

Lithography is a fundamental process in semiconductor chip manufacturing, patterning the chip design onto the photoresist coated wafer substrate before it is further processed for creating the device architectures. At one end, cutting EUV lithography is shaping the 3-5nm devices with masks and advanced OPC (optical proximity correction algorithms), and at the other end, newer maskless lithography technologies are shaping patterning at 2micron (predicted to touch 500nm) for other emerging applications in micro-electronics with new commercial propositions and actualization TAT. This paper gives a comparative overview of these patterning technologies and their potent applications in the semiconductor industry.

An improved method for measuring epi-wafer thickness based on the infrared interference principle: Addressing interference quality and multiple interferences in double-layer structures

The precise measurement of the thickness of substrate and epitaxial layers in epi-wafers is essential in the semiconductor chip fabrication process. This study presents a new method for measuring the thickness of epi-wafers using Fourier Transform Infrared (FTIR) technology, which allows for precise, simultaneous, and fast measurement of both substrate and epitaxial layers. To address the low accuracy of traditional FTIR techniques, a novel VMD-LSP algorithm is introduced, capable of precisely extracting frequency components from the original spectral signal to calculate the precise thickness of the substrate and epitaxial layers. This study also introduces an adaptive spectral excision algorithm and a high-precision thickness extraction algorithm to handle variations in the infrared light absorption of different epi-wafer materials, leading to weakened interference signals, and the challenges that stem from the unique double-layer structure of the wafer. These algorithms efficiently reduce the impact of poor spectral quality and multiple interferences on measurement results, resulting in improved measurement accuracy and stability. During the experimental phase, we compared our results obtained by ellipsometry as truth to evaluate the accuracy and stability of our proposed method. The results show an 85% reduction in measurement error and a 65% improvement in stability compared to traditional methods. As a result, our method meets the need for fast and efficient epi-wafer thickness measurement in semiconductor chip manufacturing, providing a feasible and effective solution to the challenge of epi-wafer thickness measurement.

ESD Prevention Technology for Two-Fluid Pure Water Spray Cleaning with Controlled Electrostatic Charge

In the manufacture of semiconductor chips, the cleaning process is an important process. A two-fluid spray is used in single-wafer cleaning. However, two-fluid spray cleaning has the problem of electrostatic discharge (ESD) on devices on the wafer. In this study, we measured the current generated by two-fluid spraying of pure water using a prototype Faraday cage. We also measured the velocity and size of flying droplets using a shadow doppler particle analyzer (SDPA) to clarify the relationship between the generated current and flying droplet characteristics. As a result, it was confirmed that the current generated during two-fluid spraying shows positive polarity and that the amount of droplet charge increases as the flying droplet velocity increases. To reduce ESD generated during two-fluid spray cleaning, we have confirmed that the amount of electrification of pure water droplets can be controlled by installing an induction charging device immediately after the injection of pure water.

Imaging microwave field of chip surfaces based on scanning microwave microscopy

With the rapid development of semiconductor chip circuit integration and miniaturization, especially the high integration of microwave chips, it has become critical to realize the surface microwave field imaging for such chips. In this paper, a new method of microwave field imaging for chip surface is proposed based on scanning probe microscopy. We analyse the echo signal and extract the peak-to-peak values to characterize the microwave field intensity on the chip surface by building a theoretical model of the microwave signal coupling. Using a high-precision scanning stage based on a piezoelectric ceramic tube, we realize the imaging of microwave field. The experimental results show that the imaging method can complete the chip surface microwave field imaging, which is important to support the optimization of semiconductor chip manufacturing process, fault analysis and new material research, and promote the development and progress of the semiconductor industry.

Prediction of the Test Yield of Future Integrated Circuits Through the Deductive Estimation Method

In the past 20 years, semiconductor manufacturing technology has advanced rapidly, but the advancement of integrated circuit (IC) testers has been slow. Using obsolete testers to inspect advanced wafers has become a significant challenge for test manufacturers. In this research, we used DITM (digital IC testing model) to discuss the impact of the test guardband (TGB) on quality and yield. Considering the interaction between semiconductor fabrication capability parameters and test capability parameters, we proposed an estimation method [deductive estimation method (DEM)] to analyze the electrical distribution changes of products after chip production and deduce the yield of future products. The deductive estimation method can correctly depict the future test yield [Formula: see text] curve using the chip frequency data published by IRDS (International Roadmap for Devices and Systems) in 2017. Furthermore, test manufacturers can measure whether the current test capabilities can cope with future semiconductor chip manufacturing capabilities by predicting the trends. Next, test manufacturers can maintain high-quality and high-yield chip output by pre-adjusting the hardware testing capabilities of ATE (automated test equipment) or proposing more effective chip testing methods.

Block Chain Scada Quality Control for in Industrial Automation

Abstract: Scada systems are highly distributed systems used to control geographically dispersed assets, often scattered over thousands of square kilometers, where centralized data acquisition and control are critical to system operation. They are used in distribution systems such as water distribution and waste water collection systems, oil and gas pipelines, electrical power grids, and railway transportation systems. A scada control center performs centralized monitoring and control for field sites over longdistance communications networks, including monitoring alarms and processing status data. Based on information received from remote stations, automated or opera tor-driven supervisory commands can be pushed to remote station control devices, which are often referred to as field devices . Field devices control local operations such as opening and closing valves and breakers, collecting data from sensor systems, and monitoring the local environment for alarm conditions. In general, the error rate of 1-1.5 percent found in manual working can be brought down to 0.00001 percent with automation. as stakeholders have begun to increasingly demand certain quality standards, automation has also become a key part of today’s manufacturing setup.” automation is the key in all types of manufacturing, especially in the face of an emerging global economy. From being used to increase productivity and reduce cost, automation has now become vital to increasing product quality. Further, in certain fields like semiconductor chip manufacturing where miniaturization is the key, machines are capable of achieving greater precision and speed than humans-after all.

Modeling and experimental investigation of monocrystalline silicon wafer cut by diamond wire saw

Diamond wire sawing is one of the key technologies in solar cell manufacturing process and semiconductor chip manufacturing process. The thinned of silicon wafer has become a development trend of semiconductor industry, and the reduction of silicon wafer thickness can improve the material utilization and reduce the manufacturing cost. Therefore, the minimum thickness analytical model of diamond wire saw cutting monocrystalline silicon wafer is proposed in this paper to study the processing mechanism of minimum thickness of monocrystalline silicon wafer. Firstly, based on the Kirchhoff’s thin plate theory, the theoretical equation of the maximum internal stress of single silicon wafer and the sawing thickness of the silicon wafer is derived from the sawing force model. Combined with the Mohr’s strength theory, the analytical model of minimum sawing thickness of monocrystalline silicon wafer is established. Then, the analytical model is verified by the finite element simulation. The average error between the simulation results and the calculation results of the analytical model about the minimum sawing thickness of silicon wafer is 9%. Finally, the monocrystalline silicon sawing verification experiments are conducted under some groups of processing conditions. The experimental results show that the minimum sawing thickness of the silicon wafer decreases with the increasing axial speed of the wire saw, increases with the increase of the feed rate of the wire saw, and decreases first and then increases with workpiece speed becoming large. The average error of the experimental results and the calculation results of the analytical model of the wafer minimum sawing thickness is 7.4%, which verifies corrections of the analytical model.

Logic Locking of Integrated Circuits Enabled by Nanoscale MoS2-Based Memtransistors

With an ever-increasing globalization of the semiconductor chip manufacturing supply chain coupled with soaring complexity of modern-day integrated circuits (ICs), intellectual property (IP) piracy, reverse engineering, counterfeiting, and hardware trojan insertion have emerged as severe threats that have compromised the security of critical hardware components. Logic locking (LL) is an IP protection technique that can mitigate these threats by locking a given IC with a secret key. Earlier LL demonstrations based on traditional silicon complementary metal-oxide-semiconductor (CMOS) technology and emerging memristors require significant hardware investment in the form of additional input gates and extensive CMOS peripherals, rendering them area- and energy-inefficient. In this article, we demonstrate multiple two-dimensional (2D) nanoscale memtransistor-based programmable logic gates such as AND, NAND, OR, XOR, and NOT gates, each of which can be locked/unlocked without requiring peripherals and at minuscule energy expenditure (<1 pJ). We also show that SAT-solver is unsuccessful in breaking into any of the ISCAS’85 benchmark circuits that utilize our LL scheme. The massive resilience to SAT-attack is attributed to the prowess of programmable 2D memtransistors which enable device-level LL of all the gates in each of the benchmark circuits. Given that 2D transistors are drawing increasing attention of chip manufacturing corporations like Intel, TSMC, etc., to replace and/or augment silicon at aggressively scaled technology nodes, our demonstration of area- and energy-efficient LL can be considered as a step toward the realization of secure ICs enabled by 2D nanoscale memtransistors.

Imaging-based optical barcoding for relative humidity sensing based on meta-tip

Abstract In a wide range of applications such as healthcare treatment, environmental monitoring, food processing and storage, and semiconductor chip manufacturing, relative humidity (RH) sensing is required. However, traditional fiber-optic humidity sensors face the challenges of miniaturization and indirectly obtaining humidity values. Here, we propose and demonstrate an optical barcode technique by cooperating with RH meta-tip, which can predict the humidity values directly. Such RH meta-tip is composed of fiber-optic sensor based on surface plasmon resonance (SPR) effect and graphene oxide film as humidity sensitizer. While SPR sensor is composed of multimode fiber (MMF) integrated with metallic metasurface. Dynamic time warping (DTW) algorithm is used to obtain the warp path distance (WPD) sequence between the measured reflection spectrum and the spectra of the precalibrated database. The distance sequence is transformed into a pseudo-color barcode, and the humidity value is corresponded to the lowest distance, which can be read by human eyes. The RH measurement depends on the collective changes of the reflection spectrum rather than tracking a single specific resonance peak/dip. This work can open up new doors to the development of a humidity sensor with direct RH recognition by human eyes.

Study on the subsurface damage depth of monocrystalline silicon in ultrasonic vibration assisted diamond wire sawing

Diamond wire sawing is one of the key technologies in solar cell manufacturing process and semiconductor chip manufacturing process. The subsurface damage depth (SSD) affects the quality of machined surface in diamond wire sawing, which must be evaluated. In this paper, a mathematical model of the SSD in monocrystalline silicon wafers induced by ultrasonic vibration assisted diamond wire sawing (UAWS) was proposed. In this model, the input is the depth and deflection angle of the median crack, the depth and length of the lateral crack, and ultrasonic vibration, and the output is the residual SSD on the chip. According to the model, the variation of SSD with position angle of diamond abrasives under ultrasonic vibration was analyzed on the cross section of wire saw, and the influence of shielding effect about median crack on SSD under ultrasonic vibration was analyzed later. Then, a finite element model (FEM) of diamond wire sawing monocrystalline silicon was established by ABAQUS,and the SSD under different slicing parameters was simulated. Finally, the interface bonding method was used to measure the SSD of monocrystalline silicon wafer. The experimental results showed that the SSD increases with the increase of the wire saw feed rate, and decreases with the increase of the wire saw speed and the workpiece rotation speed. The SSD in wafer sliced by UAWS is 18.95% on average lower than that in wafer sliced by conventional wire sawing (CWS). The maximum error between theoretical of mathematical model and experimental values is 15.9%, which verifies the validity of the mathematical model.

Green Nanofabrication Opportunities in the Semiconductor Industry: A Life Cycle Perspective.

The turn of the 21st century heralded in the semiconductor age alongside the Anthropocene epoch, characterised by the ever-increasing human impact on the environment. The ecological consequences of semiconductor chip manufacturing are the most predominant within the electronics industry. This is due to current reliance upon large amounts of solvents, acids and gases that have numerous toxicological impacts. Management and assessment of hazardous chemicals is complicated by trade secrets and continual rapid change in the electronic manufacturing process. Of the many subprocesses involved in chip manufacturing, lithographic processes are of particular concern. Current developments in bottom-up lithography, such as directed self-assembly (DSA) of block copolymers (BCPs), are being considered as a next-generation technology for semiconductor chip production. These nanofabrication techniques present a novel opportunity for improving the sustainability of lithography by reducing the number of processing steps, energy and chemical waste products involved. At present, to the extent of our knowledge, there is no published life cycle assessment (LCA) evaluating the environmental impact of new bottom-up lithography versus conventional lithographic techniques. Quantification of this impact is central to verifying whether these new nanofabrication routes can replace conventional deposition techniques in industry as a more environmentally friendly option.

Термоміграція довільно орієнтованих рідких лінійних зон Al–Si крізь пластини кремнію (110)

The paper analyzes the reasons and factors that allow avoiding faceting of non-oriented linear zones. It is shown that in the manufacture of semiconductor chips with a large perimeter and a reverse voltage of 2000 V, the conditions sine qua non to create isolating walls on silicon wafers with an orientation different from (111) are to form an ensemble of linear zones by the method of high-temperature selective forced wetting (HSV) and to fulfill a number of requirements to the “thermomigration” photomask and zones immersion stage during TM at high temperatures. It is shown that these factors provide a stable migration of an ensemble of linear zones through wafers (110) even in a stationary temperature gradient field. For the first time in the world, the authors practically demonstrate the possibility of stable migration of an ensemble of non-oriented linear zones through silicon (110) in a stationary temperature gradient conditions, outlining the conditions and factors necessary for this process. It is assumed that when the conditions for the formation of linear zones and their immersion are met, the crystallographic orientation of the silicon wafers does not matter at all.

Automated Linescan Analysis for CMP Modeling

Many of the process steps used in semiconductor chip manufacturing require planar (smooth) surfaces on the wafer to ensure correct pattern printing and generation of multilevel interconnections in the chips during manufacturing. Chemical-mechanical polishing/planarization (CMP) is the primary process used to achieve these surface planarity requirements. Modeling of CMP processes allows users to detect and fix large surface planarity variations (hotspots) in the layout prior to manufacturing. Fixing hotspots before tape-out may significantly reduce turnaround time and the cost of manufacturing. Creating an accurate CMP model that takes into account complicated chemical and mechanical polishing mechanisms is challenging. Measured data analysis and extraction of erosion and dishing data from profile linescans from test chips are important steps in CMP model building. Measured linescans are often tilted and noisy, which makes the extraction of erosion and dishing data more difficult. The development and implementation of algorithms used to perform automated linescan analysis may significantly reduce CMP model building time and improve the accuracy of the models. In this work, an automated linescan analysis (ALSA) tool is presented that performs automated linescan delineation, test pattern separation, and automatic extraction of erosion and dishing values from linescan data.

The origins of the tools suppliers in the semiconductor industry

Technological progress in semiconductor chips plays a central role in enabling the Information Technology revolution. Continual technological progress in semiconductor chips, which has become popular under the name of Moore’s Law, reduces the cost of storing and processing information. While the role of the semiconductor chip manufacturing companies in driving Moore’s Law is well known, less attention has been given to the equally important role played by upstream suppliers who produce the tools that are necessary to make the chips. In the early stages of the industry, the chip manufacturers made their own tools in-house. Using data at the initial stages of the industry and a wealth of publicly available information from interviews with industry pioneers conducted as part of oral history projects, this article examines how (i) market size (ii) heterogeneity in firm capabilities (iii) geographic proximity to manufacturing clusters, influenced the emergence of these semiconductor tools suppliers.

Acute and chronic toxicity to Daphnia magna of colloidal silica nanoparticles in a chemical mechanical planarization slurry after polishing a gallium arsenide wafer

Semiconductor chip manufacturers use slurries of metal oxide nanoparticles (NPs) as abrasives in chemical mechanical planarization (CMP) processes on wafers containing films of III/V semiconducting materials. Assessing the toxicity of these specialized NPs is challenging not only because commercial slurries may contain undefined toxic constituents, but because CMP processes can change the physical and chemical properties of the NPs. Herein, the fresh water flea Daphnia magna (D. magna) was used to assess the effects of Ultra-Sol® 200S CMP slurry containing ~30-nm colloidal silica (c-SiO2) NPs before (pristine) and after (spent) a GaAs wafer was polished with an extreme arm-pressure of 5 psi. In the acute 96-hour toxicity assessments, both the pristine and spent slurries at 4.0 mg/mL c-SiO2 NPs had little effect on D. magna morbidity and body sizes. In the chronic 21-day toxicity assessments, neither slurry at 0.10 mg/mL c-SiO2 NPs was toxic, but both slurries lead to a modest (9–10%) increase in D. magna body sizes and a significant (~2-fold) increase in reproductive output, indicative of a positive hormetic response. Identical increases in D. magna body sizes and reproductive output were observed with a supernatant of the pristine slurry, in the absence of the c-SiO2 NPs, indicating that soluble material in the pristine supernatant contributed to the hormetic response, which suggests that the soluble material may also contribute to the hormetic response of the spent material.

The Emergence of Tools Suppliers in the Semiconductor Industry

While the R&D intensive semiconductor tools industry has become pivotal to the advancement of technology and the growth of the downstream semiconductor chip manufacturing industry, this was not always the case. In the early stages of the industry, the chip manufacturers made their own tools in-house. Using data at the initial stages of the industry and a wealth of publicly available information from interviews with industry pioneers conducted as part of oral history projects, I examine how (i) market size (ii) intellectual property protection (iii) geographic proximity to downstream firms, influenced the process of emergence of the tools suppliers.

Toward CO&lt;sub&gt;2&lt;/sub&gt; Beam Cleaning of 20-nm Particles in Atmospheric Pressure

We propose an optimal strategy for cleaning 20-nm contaminants in atmospheric pressure by using CO2 solid particles injected from a supersonic nozzle. We found that an excessively small exit diameter of the nozzle results in the shock wave, which decreases the particle removal efficiency (PRE). Based on the incompressible flow theory, we developed a supersonic nozzle that can issue CO2 solid particles without shock wave. The shape of CO2 beam and PRE of the developed nozzle are compared with the results of a pre-existing nozzle for vacuum condition by analyzing scanning electron microscopy (SEM) image of substrates. The results show that when we use the newly developed nozzle in atmospheric pressure, PRE is above 95 % without pattern damage. This work can pave the way for cleaning nanoscale contaminants that occur during manufacture of semiconductor chips at little cost.