Back-end Semiconductor Manufacturing Research Articles

A real-time production scheduling method for RFID-enabled semiconductor back-end shopfloor environment in industry 4.0

PurposeA real-time production scheduling method for semiconductor back-end manufacturing process becomes increasingly important in industry 4.0. Semiconductor back-end manufacturing process is always accompanied by order splitting and merging; besides, in each stage of the process, there are always multiple machine groups that have different production capabilities and capacities. This paper studies a multi-agent based scheduling architecture for the radio frequency identification (RFID)-enabled semiconductor back-end shopfloor, which integrates not only manufacturing resources but also human factors.Design/methodology/approachThe architecture includes a task management (TM) agent, a staff instruction (SI) agent, a task scheduling (TS) agent, an information management center (IMC), machine group (MG) agent and a production monitoring (PM) agent. Then, based on the architecture, the authors developed a scheduling method consisting of capability & capacity planning and machine configuration modules in the TS agent.FindingsThe authors used greedy policy to assign each order to the appropriate machine groups based on the real-time utilization ration of each MG in the capability & capacity (C&C) planning module, and used a partial swarm optimization (PSO) algorithm to schedule each splitting job to the identified machine based on the C&C planning results. At last, we conducted a case study to demonstrate the proposed multi-agent based real-time production scheduling models and methods.Originality/valueThis paper proposes a multi-agent based real-time scheduling framework for semiconductor back-end industry. A C&C planning and a machine configuration algorithm are developed, respectively. The paper provides a feasible solution for semiconductor back-end manufacturing process to realize real-time scheduling.

Enhanced Die Attach Process Defect Recognition on QFN Leadframe Packages

Advanced packaging at the back-end semiconductor manufacturing characterizes various equipment capabilities per device requirement. High resolution imaging for inspection system during die attach process has gained its interest to feature automated selections during in-line processing. Increasing yet stringent requisites of today’s applications give us leading indicators of market’s demand at more functionality in a smaller and complex package. In light with the technology trend, vision inspection system is a well-known challenge. Instead of using a high magnification microscope off-line after assembly processing, leadframe inspection feature uses optical image-based system to recognize real-time feedback on lead-related defects. Such leadframe inspection activation provides good accuracy, monitoring process integrity in real-time for quad-flat no-leads (QFN) leadframe packages. This paper presents how leadframe inspection at die attach machine takes advantage of simultaneous detection of early die attach defect manifestations.

Optimizing class-constrained wafer-to-order allocation in semiconductor back-end production

This paper studies the problem of allocating semiconductor wafers to customer orders with the objective of minimizing the overallocation prior to assembly. It is an important problem for back-end semiconductor manufacturing as overallocation may have severe impact on operational performance due to excess inventory and unnecessarily occupied manufacturing equipment. In practice, a wafer can contain dies from several different die classes, making the wafer-allocation problem more challenging. As a novel contribution of this work, we explicitly consider the existence of multiple die classes on a wafer in the wafer-allocation problem. An integer linear programming formulation of the class-constrained wafer allocation problem is provided. The formulation is further extended to be more flexible by allowing the dies from different classes on the same wafer to be allocated to distinct customer orders. A real-world case study from the back-end assembly and test facility of a semiconductor manufacturer is presented. Experiments with real-world data show that the proposed method significantly reduces the overallocation performance in current practice and allows planners to quantify the value of flexibility in wafer allocation.

Simulation optimization approach for hybrid flow shop scheduling problem in semiconductor back-end manufacturing

This study presents a simulation optimization approach for a hybrid flow shop scheduling problem in a real-world semiconductor back-end assembly facility. The complexity of the problem is determined based on demand and supply characteristics. Demand varies with orders characterized by different quantities, product types, and release times. Supply varies with the number of flexible manufacturing routes but is constrained in a multi-line/multi-stage production system that contains certain types and numbers of identical and unrelated parallel machines. An order is typically split into separate jobs for parallel processing and subsequently merged for completion to reduce flow time. Split jobs that apply the same qualified machine type per order are compiled for quality and traceability. The objective is to achieve the feasible minimal flow time by determining the optimal assignment of the production line and machine type at each stage for each order. A simulation optimization approach is adopted due to the complex and stochastic nature of the problem. The approach includes a simulation model for performance evaluation, an optimization strategy with application of a genetic algorithm, and an acceleration technique via an optimal computing budget allocation. Furthermore, scenario analyses of the different levels of demand, product mix, and lot sizing are performed to reveal the advantage of simulation. This study demonstrates the value of the simulation optimization approach for practical applications and provides directions for future research on the stochastic hybrid flow shop scheduling problem.

A Constraint programming-based genetic algorithm for capacity output optimization

Purpose: The manuscript presents an investigation into a constraint programming-based genetic algorithm for capacity output optimization in a back-end semiconductor manufacturing company. Design/methodology/approach: In the first stage, constraint programming defining the relationships between variables was formulated into the objective function. A genetic algorithm model was created in the second stage to optimize capacity output. Three demand scenarios were applied to test the robustness of the proposed algorithm. Findings: CPGA improved both the machine utilization and capacity output once the minimum requirements of a demand scenario were fulfilled. Capacity outputs of the three scenarios were improved by 157%, 7%, and 69%, respectively. Research limitations/implications : The work relates to aggregate planning of machine capacity in a single case study. The constraints and constructed scenarios were therefore industry-specific. Practical implications: Capacity planning in a semiconductor manufacturing facility need to consider multiple mutually influenced constraints in resource availability, process flow and product demand. The findings prove that CPGA is a practical and an efficient alternative to optimize the capacity output and to allow the company to review its capacity with quick feedback. Originality/value: The work integrates two contemporary computational methods for a real industry application conventionally reliant on human judgement.

Scheduling Semiconductor Multihead Testers Using Metaheuristic Techniques Embedded with Lot-Specific and Configuration-Specific Information

In the semiconductor back-end manufacturing, the device test central processing unit (CPU) is most costly and is typically the bottleneck machine at the test plant. A multihead tester contains a CPU and several test heads, each of which can be connected to a handler that processes one lot of the same device. The residence time of a lot is closely related to the product mix on test heads, which increases the complexity of this problem. It is critical for the test scheduling problem to reduce CPU's idle time and to increase tester utilization. In this paper, a multihead tester scheduling problem is formulated as an identical parallel machine scheduling problem with the objective of minimizing makespan. A heuristic grouping method is developed to obtain a good initial solution in a short time. Three metaheuristic techniques, using lot-specific and configuration-specific information, are proposed to receive a near-optimum and are compared to traditional approaches. Computational experiments show that a tabu search with lot-specific information outperforms all other competing approaches.

Coordinated Multistage Scheduling of Parallel Batch-Processing Machines Under Multiresource Constraints

Motivated by scheduling challenges of burn-in ovens in back-end semiconductor manufacturing, we propose a linear-programming-based algorithm, an integer-programming-based algorithm, and a heuristic-based algorithm to schedule nonhomogenous parallel batch machines with nonidentical job sizes and incompatible job families. We consider the common scheduling of consecutive steps that are linked together through secondary scarce resources. Our approach addresses the availability and compatibility of several resources required to make each process possible. The algorithms strive to meet short-term production targets expressed by product and step. The algorithms are shown to be effective and computationally efficient for this purpose. Taken together with previously developed methodology for the practical translation of target output schedules into short-term local production targets, this article suggests how a complex supply chain manufacturing system can be efficiently and effectively managed by decentralized local scheduling algorithms striving to meet short-term production targets that in turn ensure maintenance of an appropriate dynamic profile across production steps for work-in-process.

Coordinating decentralized local schedulers in complex supply chain manufacturing

Motivated by scheduling challenges in back-end semiconductor manufacturing, we propose a framework to oversee and integrate local decentralized scheduling algorithms utilized in complex supply chain manufacturing networks. We fill the gap between higher-level production planning and lower-level scheduling by establishing short-term production targets and priority scores for each product at each step in the system. Given a target output schedule, target cycle times for each step, the process and product structure, and initial WIP status, short-term production targets for each product/step are set. These targets can be used to evaluate the system performance and guide decentralized schedulers to control the system so as to achieve desirable outputs in dynamic environments.

Practical lot release methodology for semiconductor back-end manufacturing

This paper presents a new method and system that has been developed to solve production lot release problems in a discrete semiconductor back-end manufacturing environment, wherein there is always a huge product mix and a multitude of capacity constraints. The methodology is a multi-constraint based finite capacity production control mechanism to plan lot release of the desired mix of products for the semiconductor assembly and test operations. Practical lot prioritization considerations, order release policies, finite capacity constraints and a novel technique of multi-level loading pattern for minimizing machine conversion are discussed in detail. The system and methodology presented in this paper has been successfully implemented in a semiconductor back-end factory in Asia.

An approach to regulating machine sharing in reconfigurable back-end semiconductor manufacturing

By complying with the operational philosophy of virtual production lines, a back-end semiconductor manufacturing system can be controlled and managed with better reconfigurability. However, due to the absence of a fully-integrated information system and the gaining popularity of distributed computing, machine reconfiguration decisions are made by machine controllers on the shop floor where heterarchical control architecture is typically used. This research investigates how non-cooperative game theory could be applied for facilitating the decision process reconfiguration decision-making at the machine controller level as machines are competed by multiple jobs streams. This paper presents how material flow traffic can be better regulated in a reconfigurable manufacturing environment. A study using an industrial pilot system is discussed to demonstrate the applicability of the proposed approach, in which heuristics are used to determine the game specification.

Integrated design approach for virtual production line-based reconfigurable manufacturing systems

Reconfigurable manufacturing systems (RMSs) have been recognized as a new manufacturing paradigm. In light of their enhanced flexibility and responsiveness, RMSs are considered to be mostly applicable to the very dynamic and unpredictable marketplaces of the near future. However, systematic approaches to the design and ramp-up of an RMS have not been well addressed. This paper presents a virtual production line-based (VPL) approach to the design and operation of a reconfigurable manufacturing system. Shop floor attributed finite-capacity automaton and VPL attributed finite-capacity automaton are proposed for modelling the control of an RMS, which leads to ease of control software development. Algorithms for balancing VPLs to maximize the productivity of an RMS are discussed. The results of simulation runs of the proposed methodology and algorithms applied to simplified back-end semiconductor manufacturing are provided.

Novel Noncontact Thickness Metrology for Partially Transparent and Nontransparent Wafers for Backend Semiconductor Manufacturing

ABSTRACTSingle probe infrared low coherence optical interferometry has been proven to be an effective tool for characterization of thin and ultra-thin semiconductor Si and compound materials wafers. Its application was however limited to wafers transparent at probing wavelength, and having relatively smooth surfaces. Purpose of this paper is to present an extension of low coherence interferometry to characterization of non-transparent wafers, and wafers with rough surfaces.

Virtual production lines design for back-end semiconductor manufacturing systems

This paper introduces the virtual production line (VPL) concept, which initiates a new method to model the shop floor from both control and management point of view. Heuristic algorithms are presented to dynamically configure a large system into many VPLs, which ensure the line balance and efficiency, and accurately predicate the completion time for each work-order. The proposed methodology and algorithms are demonstrated through a simplified back-end semiconductor manufacturing system.

A simulation based analysis of cycle time distribution, and throughput in semiconductor backend manufacturing

This paper presents a preliminary analysis of the relationship between selected input and output variables in semiconductor backend manufacturing system, using a data driven discrete event simulation model. This study is of interest and importance for a better understanding of the controllable input variables in an effort to reduce factory cycle time and distribution. Our analysis quantifies the effect of varying the input variables of lot release controls, heuristic machine dispatching rules, elimination of selected processes, material handling time, set-up time, and machine up time on selected output variables of throughput, cycle time and cycle time spread. Simulation model of a semiconductor site based in Singapore is used as the base case and the effects are quantified against the base model.