Scheduling Semiconductor Multihead Testers Using Metaheuristic Techniques Embedded with Lot-Specific and Configuration-Specific Information

Yi-Feng Hung,Chi-Chung Wang,Gen-Han Wu

doi:10.1155/2013/436701

Abstract

In the semiconductor back-end manufacturing, the device test central processing unit (CPU) is most costly and is typically the bottleneck machine at the test plant. A multihead tester contains a CPU and several test heads, each of which can be connected to a handler that processes one lot of the same device. The residence time of a lot is closely related to the product mix on test heads, which increases the complexity of this problem. It is critical for the test scheduling problem to reduce CPU's idle time and to increase tester utilization. In this paper, a multihead tester scheduling problem is formulated as an identical parallel machine scheduling problem with the objective of minimizing makespan. A heuristic grouping method is developed to obtain a good initial solution in a short time. Three metaheuristic techniques, using lot-specific and configuration-specific information, are proposed to receive a near-optimum and are compared to traditional approaches. Computational experiments show that a tabu search with lot-specific information outperforms all other competing approaches.

Highlights

Semiconductor manufacturing consists of front-end and back-end manufacturing
A pattern of circuitry is imprinted onto the surfaces of a wafer, on which hundreds of dice are fabricated, and dice are individually tested in the process of wafer probe
In [12,13,14,15], back-end operations such as assembly and final test are considered as serial production stages or workstations and heuristic techniques such as ant colony optimization [12], multistep reinforcement learning algorithm [13], reactive greedy randomized adaptive search procedure (GRASP) [14] and dynamic machine/lot prioritization [15] are introduced

Summary

Introduction

The front-end manufacturing contains the processes of wafer fabrication and wafer probe. In [9, 10] and the wafer probe process was scheduled as a mathematical model to minimize the makespan. Lot and process information are used to develop scheduling algorithm. The back-end manufacturing comprises the processes of assembly and final testing. An assignment algorithm is developed to obtain the machine configuration of each job and allot specific resources. In [12,13,14,15], back-end operations such as assembly and final test are considered as serial production stages or workstations and heuristic techniques such as ant colony optimization [12], multistep reinforcement learning algorithm [13], reactive greedy randomized adaptive search procedure (GRASP) [14] and dynamic machine/lot prioritization [15] are introduced. We focus on the scheduling problem of multihead testers in order to solve the bottleneck of the final testing process

Methods

Results

Conclusion