Semi-floating Gate Research Articles

Non-volatile 2D MoS2/black phosphorus heterojunction photodiodes in the near- to mid-infrared region

Cutting-edge mid-wavelength infrared (MWIR) sensing technologies leverage infrared photodetectors, memory units, and computing units to enhance machine vision. Real-time processing and decision-making challenges emerge with the increasing number of intelligent pixels. However, current operations are limited to in-sensor computing capabilities for near-infrared technology, and high-performance MWIR detectors for multi-state switching functions are lacking. Here, we demonstrate a non-volatile MoS2/black phosphorus (BP) heterojunction MWIR photovoltaic detector featuring a semi-floating gate structure design, integrating near- to mid-infrared photodetection, memory and computing (PMC) functionalities. The PMC device exhibits the property of being able to store a stable responsivity, which varies linearly with the stored conductance state. Significantly, device weights (stable responsivity) can be programmed with power consumption as low as 1.8 fJ, and the blackbody peak responsivity can reach 1.68 A/W for the MWIR band. In the simulation of Faster Region with convolution neural network (CNN) based on the FLIR dataset, the PMC hardware responsivity weights can reach 89% mean Average Precision index of the feature extraction network software weights. This MWIR photovoltaic detector, with its versatile functionalities, holds significant promise for applications in advanced infrared object detection and recognition systems.

Photoelectric performance of InSe vdW semi-floating gate p–n junction transistor

Semi-floating gate transistors based on vdW materials are often used in memory and programmable logic applications. In this paper, we propose a semi-floating gate photoelectric p–n junction transistor structure which is stacked by InSe/h-BN/Gr. By modulating gate voltage, InSe can be presented as N-type and P-type respectively on different substrates, and then combined into p–n junction. Moreover, InSe/h-BN/Gr device can be switched freely between N-type resistance and p–n junction. The resistance value of InSe resistor and the photoelectric properties of the p–n junction are also sensitively modulated by laser. Under dark conditions, the rectification ratio of p–n junction can be as high as 107. After laser modulation, the device has a response up to 1.154 × 104 A W−1, a detection rate up to 5.238 × 1012 Jones, an external quantum efficiency of 5.435 × 106%, and a noise equivalent power as low as 1.262 × 10−16 W/Hz1/2. It lays a foundation for the development of high sensitivity and fast response rate tunable photoelectric p–n junction transistor.

Flash memory based on MoTe2/boron nitride/graphene semi-floating gate heterostructure with non-volatile and dynamically tunable polarity

Flash memory based on MoTe2/boron nitride/graphene semi-floating gate heterostructure with non-volatile and dynamically tunable polarity

A semi-floating gate AlGaN/GaN HEMT for normally-off operation

AlGaN/GaN-Si based HEMTs are considered as the promising candidates for application in the 5G communication system due to their excellent characteristics and low cost. Enhancement mode (E-mode) AlGaN/GaN HEMTs should be fabricated for power application. In this paper, we report a novel semi-floating gate (SFG) AlGaN/GaN HEMT with 20 nm Al2O3 which acts as control gate capacitance for normally-off operation. This methods avoids gate recess process which may damage the 2DEG channel. Also, the Vth can be programmed to different values by adjusting the VCGP. In our results, by adjusting control gate voltage VCGP = 15 V, the Vth of AlGaN/GaN HEMT on PCB (containing capacitances with different capacitance values which acts as control gate capacitance) is extracted to exceed over 8.5 V at VDS = 15 V. In addition, for the fabricated SFG AlGaN/GaN HEMT with the Al2O3 thickness of 20 nm, the Vth of the fabricated SFG AlGaN/GaN HEMT is extracted to be 0.42 V when VCGP increases up to 5 V. The SFG AlGaN/GaN HEMT technique presented in our results offer a prospective method to fabricate E-mode AlGaN/GaN HEMTs.

Enhancement of refresh time in quasi-nonvolatile memory by the density of states engineering

The recently reported quasi-nonvolatile memory based on semi-floating gate architecture has attracted extensive attention thanks to its potential to bridge the large gap between volatile and nonvolatile memory. However, the further extension of the refresh time in quasi-nonvolatile memory is limited by the charge leakage through the p–n junction. Here, based on the density of states engineered van der Waals heterostructures, the leakage of electrons from the floating gate to the channel is greatly suppressed. As a result, the refresh time is effectively extended to more than 100 s, which is the longest among all previously reported quasi-nonvolatile memories. This work provides a new idea to enhance the refresh time of quasi-nonvolatile memory by the density of states engineering and demonstrates great application potential for high-speed and low-power memory technology.

1T semi-floating gate image sensor with enhanced quantum efficiency and high response speed

The active pixel image sensor based on a semi-floating gate transistor (SFGT-APS) has been proposed and investigated; however, the quantum efficiency (QE) and the sensitivity are too poor to meet low illumination intensity and high-speed application due to the shallow junction of photodiodes. In this work, we demonstrate a new structure, called buried photodiode semi-floating gate transistor active pixel image sensor (BSFGT-APS), which possesses enhanced QE, high sensitivity, and fast response speed. Moreover, BSFGT-APS has the same fill factor with SFGT-APS, which is 55% with a 1 μm2 photodiode in 0.13 μm process. The basic device characteristics were investigated by Sentaurus TCAD simulation, including potential of photodiode, transient response, dark current, conversion gain, and full well capacity.

A Semi-Floating Gate Memory Based on SOI Substrate by TCAD Simulation

Over the past decade, the dimensional scaling of semiconductor electronic devices has been facing fundamental and physical challenges, and there is currently an urgent need to increase the ability of dynamic random-access memory (DRAM). A semi-floating gate (SFG) transistor has been proposed as a capacitor-less memory with faster speed and higher density as compared with the conventional one-transistor one-capacitor (1T1C) DRAM technology. The integration of SFG-based memory on the silicon-on-insulator (SOI) substrate has been demonstrated in this work by using the Sentaurus Technology Computer-Aided Design (TCAD) simulation. An enhancement in retention characteristics, anti-disturbance ability, and fast writing capability, have been illustrated. The device exhibits a low operation voltage, a large threshold voltage window of ~3 V, and an ultra-fast writing of 4 ns. In addition, the SOI-based memory has shown a much-improved anti-irradiation capability compared to the devices based on bulk silicon, which makes it much more attractive in broader applications.

Investigation of device physics and modeling of semi-floating gate image sensor cell

In this paper, an image sensor cell based on the semi-floating gate (SFG) concept is fabricated and measured. The physics and modeling of the proposed device are studied, and the overall electrical properties such as transfer characteristics and operating sequence are investigated. The relationships between the floating gate potential, photocurrent and exposure time are also discussed. Moreover, the photosensitivity to the light of different wavelengths and the effects of different voltage settings are further investigated.

A Semi-Floating Gate Memory with Tensile Stress for Enhanced Performance

With the continuous scaling down of devices, traditional one-transistor one-capacitor dynamic random access memory (1T-1C DRAM) has encountered great challenges originated from the large-volume capacitor and high leakage current. A semi-floating gate transistor has been proposed as a capacitor-less memory with ultrafast speed and silicon-compatible technology. In this work, a U-shaped semi-floating gate memory with strain technology has been demonstrated through TCAD simulation. Ultra-high operation speed on a timescale of 5 ns at low operation voltages (≤ 2.0 V) has been obtained. And the tensile stress induced in its channel region by using contact etch stop layer (Si3N4 capper layer) was found to significantly improve the drain current by 12.07%. Furthermore, this device demonstrated a favorable retention performance with a retention time over 1 s, and its immunity to disturbance from bit-line has also been investigated that could maintain data under the continuous worst writing disturbance operation over 10 ms.

Design and Characterization of Semi-Floating-Gate Synaptic Transistor.

In this work, a study on a semi-floating-gate synaptic transistor (SFGST) is performed to verify its feasibility in the more energy-efficient hardware-driven neuromorphic system. To realize short- and long-term potentiation (STP/LTP) in the SFGST, a poly-Si semi-floating gate (SFG) and a SiN charge-trap layer are utilized, respectively. When an adequate number of holes are accumulated in the SFG, they are injected into the nitride charge-trap layer by the Fowler–Nordheim tunneling mechanism. Moreover, since the SFG is charged by an embedded tunneling field-effect transistor existing between the channel and the drain junction when the post-synaptic spike occurs after the pre-synaptic spike, and vice versa, the SFG is discharged by the diode when the post-synaptic spike takes place before the pre-synaptic spike. This indicates that the SFGST can attain STP/LTP and spike-timing-dependent plasticity behaviors. These characteristics of the SFGST in the highly miniaturized transistor structure can contribute to the neuromorphic chip such that the total system may operate as fast as the human brain with low power consumption and high integration density.

A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications.

As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 106 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.

A Semi-Floating Gate Transistor with Enhanced Embedded Tunneling Field Effect Transistor

With the continuous semiconductor device scaling and the boosting of transistor density, it has become more and more important to design and realize novel paradigms of miniaturized electronic devices. A planar semi-floating gate transistor employs an embedded tunneling field-effect transistor for gate charging and discharging. U-shape semi-floating gate transistor uses a recessed trench to increase the channel length of the device. In this letter, we report the application of high- $k$ /metal gate in the transistor replacing the polysilicon control gate and SiO2 dielectric. The process and device characteristics have been theoretically studied and the simulation work has been carried out using Sentaurus TCAD tools. This transistor can be operated at lower voltages and higher writing, and erasing operation speed has been achieved. The device power consumption has been successfully reduced.

Analysis and modeling of the semi-floating transistor based 1T pixel in CMOS image sensors

A semi-floating gate transistor (SFGT) based 1T pixel can achieve the same functions as the traditional 3T active pixel sensor (APS). The SFGT APS improves the fill factor and the pixel density of CMOS image sensors to meet the requirement for high sensitivity application. This paper proposes an equivalent circuit model for the SFGT APS. The model shows that the intrinsic capacitances and the applied voltages affect the SFG voltage range, the maximum non-saturated light power, the conversion gain and the full well capacity (FWC). The simulation results are obtained by technology computer aided design (TCAD), which shows a good agreement with theoretical calculation. A higher drain voltage improves the output swing, the maximum non-saturated light power, the conversion gain and the FWC. A lower capacitance CPIP increases the output level and the conversion gain at the expense of the light range and the FWC. The model also proposes optimization for better pixel design.

Two-dimensional non-volatile programmable p-n junctions.

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe2/hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 104 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

Investigation of Dynamic Threshold Voltage Behavior in Semi-Floating Gate Transistor for Normally-Off AlGaN/GaN HEMT

In this paper, an inverter composed of semi-floating gate (SFG) transistor and a load resistor was analyzed. Varying threshold voltage $(V_{\mathrm {th}})$ during switching was observed. This dynamic $V_{\mathrm {th}}$ behavior of SFG device is because of the special device structure of SFG transistors. Based on the $V_{\mathrm {th}}$ -programmable behavior of the SFG transistor, a SFG-based GaN high electron mobility transistor was proposed and enhancement-mode was realized with writing-0 into the transistor during every switching operation by simulation.

NP-Domino, Ultra-Low-Voltage, High-Speed, Dual-Rail, CMOS NOR Gates

In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations are the main advantages of the proposed gates in comparison to the previously reported domino dual-rail NOR gates. The simulation results in a typical TSMC 90 nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.

Feasibility Study of Semifloating Gate Transistor Gamma-Ray Dosimeter

The feasibility study of semifloating gate (SFG) transistor dosimeter consisting a large area p-i-n diode between floating gate and drain region is described. No bias is applied during irradiation. The SFG is charged via the diode when exposed to gamma rays, and reset with the diode positively biased. A comprehensive device simulation that includes the mechanism of charge collection, the operation of device's threshold voltage (Vth) reading, and the effect of diode dark current have been carried out with sentaurus TCAD. As a result, high linear dependence of the Vth on the absorbed dose of ionizing radiation is observed with a sensitivity of 65.8 mV/Gy, which suggests that this device could be used as a sensitive gamma-ray dosimeter.

A Semi-Floating Gate Transistor for Low-Voltage Ultrafast Memory and Sensing Operation

As the semiconductor devices of integrated circuits approach the physical limitations of scaling, alternative transistor and memory designs are needed to achieve improvements in speed, density, and power consumption. We report on a transistor that uses an embedded tunneling field-effect transistor for charging and discharging the semi-floating gate. This transistor operates at low voltages (≤2.0 volts), with a large threshold voltage window of 3.1 volts, and can achieve ultra-high-speed writing operations (on time scales of ~1 nanosecond). A linear dependence of drain current on light intensity was observed when the transistor was exposed to light, so possible applications include image sensing with high density and performance.