Self-test Technique Research Articles

All real projective measurements can be self-tested

Entangled quantum systems feature non-local correlations that are stronger than could be realized classically. This property makes it possible to perform self-testing, the strongest form of quantum functionality verification, which allows a classical user to deduce the quantum state and measurements used to produce a given set of measurement statistics. While self-testing of quantum states is well understood, self-testing of measurements, especially in high dimensions, remains relatively unexplored. Here we prove that every real projective measurement can be self-tested. Our approach employs the idea that existing self-tests can be extended to verify additional untrusted measurements, known as post-hoc self-testing. We formalize the method of post-hoc self-testing and establish the condition under which it can be applied. Using this condition, we construct self-tests for all real projective measurements. We build on this result to develop an iterative self-testing technique that provides a clear methodology for constructing new self-tests from pre-existing ones.

BMC-Based Temperature-Aware SBST for Worst-Case Delay Fault Testing Under High Temperature

This article presents a bounded model checking (BMC)-based temperature-aware software-based self-testing (SBST) technique to test worst case delay faults within the highest temperature range. The BMC-based SBST method first defines the sequential constraint. It develops a sequentially constrained automatic test pattern generation (ATPG) to ensure that the generated delay test patterns can emerge in functional mode. It then uses the processor’s multiple-level information to reduce the model complexity, avoid aborts due to time-outs during the BMC process, and generate test programs automatically. A temperature-aware SBST method has then been developed to ensure that the test temperature is within the specified range and test the worst case delays under high temperature. Experimental results demonstrate that the proposed technique achieves an extremely high coverage for delay faults and effectively avoids yield loss caused by the overtesting problem. Its test quality also outperforms that of the existing methods. The generated SBST programs are successful and efficient in testing worst case delay faults under high temperature.

Digital Fault-based Built-in Self-test and Evaluation of Low Dropout Voltage Regulators

With increasing pressure to obtain near-zero defect rates, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, power converters, and data converters. This article presents an extremely low-cost built-in self-test technique for LDOs, specifically designed for fault detection. The methodology relies on exciting the LDO loop at the voltage reference input via a pseudo-random signal with white noise characteristics and observing the response from the output of LDO via all-digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with an LDO as a device under test is designed in 65nm technology. Fault simulations performed at the transistor level show that all resistive open/short defects in circuit components can be detected even if they do not cause a catastrophic failure in the LDO response. The proposed technique is validated with hardware using off-the-shelf components.

Power analyzer of linear feedback shift register techniques using built in self test

Wasteful patterns that don't lead to fault dropping squander a tone of energy in the linear-feedback shift register and circuit under examination in a random research region. Random switching actions in the CUT and scan pathways between applications with two consecutive vectors are another significant cause of energy loss. This study proposes a unique built-in self-test (BIST) technique for scan-based circuits that might help save energy. Only the available vectors are produced in a fixed series thanks to a mapping logic that alters the LFSR's state transitions. As a consequence, and without reducing fault coverage, the time it takes to execute trials has decreased. Experiments on circuits demonstrated that during random testing, the linear feedback shift register saves a significant amount of power.

Self-testing technique for sexually transmitted infections

<h3>ЦЕЛЬ ИССЛЕДОВАНИЯ</h3> Оценить приемлемость метода самотестирования на инфекции, передающиеся половым путем (ИППП). <h3>МАТЕРИАЛ И МЕТОДЫ</h3> На базе консультативно-диагностического отделения ФГБОУ ВО «СПб ГПМУ» Минздрава России, СПб НИИ СП им. И.И. Джанелидзе и женской консультации №12 СПб ГБУЗ «Городская поликлиника №49» с января по октябрь 2020 г. проведено исследование 80 пациентов (40 (50%) мужчин и 40 (50%) женщин) с ИППП (хламидиоз, гонорея), подтвержденными лабораторным методом полимеразной цепной реакции (ПЦР). Материал собирали традиционным методом (вагинальный/уретральный мазок) с повторным сбором материала самими пациентами. Женщины собирали материал по следующей схеме: 1) тампон помещали во влагалище на 4 ч, далее, после извлечения тампона, срезали часть волокон тампона и помещали в пробирку для ПЦР; 2) пластмассовым шпателем собирали материал из влагалища. Мужчины собирали утреннюю первую порцию мочи в контейнер (2—3 мл) и затем доставляли материал в лабораторию для проведения анализа методом ПЦР. <h3>РЕЗУЛЬТАТЫ</h3> По результатам исследования 90,0% (36 из 40) мужчин и 95,0% (38 из 40) женщин, которые использовали самотестирование хламидиоза и гонореи, получили положительный результат на хламидиоз и/или гонорею. При проверке данных путем тестирования в процессе посещения врача выяснилось, что положительный результат на хламидиоз и/или гонорею получен у 87,5% (35 из 40) мужчин и у 90,0% (36 из 40) женщин. При обследовании пациентов положительный результат получен с большей вероятностью при выборе теста с помощью самопроверки по сравнению с клиническим тестом (χ²<i></i> (1, <i>n</i>=80) = 8,76, <i>p</i>&lt;0,05). <h3>ЗАКЛЮЧЕНИЕ</h3> Самотестирование может быть эффективным и действенным способом проведения ранней диагностики инфекций, передающихся половым путем, особенно при бессимптомном течении заболевания. Применение самотестирования позволяет увеличить выявление пациентов из групп риска и ускорить оказание медицинской помощи. Эта легковоспроизводимая программа может быть реализована для улучшения выявления новых случаев заболеваний на более раннем этапе.

Fault-based Built-in Self-test and Evaluation of Phase Locked Loops

With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This article presents a very low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65 nm technology. Fault simulations performed at the transistor and system-level show that the majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.

Software-Based Self-Test Techniques for Dual-Issue Embedded Processors

Nowadays, Self-Test strategies for testing embedded processors are increasingly diffused, especially for safety critical systems. Test programs can be effectively used for this purpose. This paper describes a set of systematic self-test techniques for in-order dual-issue embedded processors. The paper shows how to produce test programs suitable for the detection of faults in five classes of sub-modules: duplicated computational modules; multi-port register file; duplicated pipeline registers and feed-forward paths; pipeline interlocking logic; and pre-fetch buffer. While some techniques extend single-issue test programs, new techniques are also shown; results are illustrated for a couple of 32-bit in-order dual-issue processors included in automotive Systems-on-Chip manufactured by STMicroelectronics.

Built-in Harmonic Prediction Scheme for Embedded Segmented-Data-Converters

Increase in manufacturing test cost is of paramount issue to chip suppliers, which has been primarily due to costly external testers and long test-time. This paper proposes a loopback-based self-test technique to cost-effectively predict the dynamic nonlinearities of on-chip segmented digital-to-analog-converter (DAC) and analog-to-digital-converter (ADC), by externally looping a DAC back to an ADC, through an external load board employing two parallel paths: a programmable-gain-amplifier (PGA) path and a bypass path for test purpose. A segmented DAC (or ADC) consists of coarse and fine DACs (or ADCs). Two loopback tests are sequentially performed. For the first loopback test, a clean and single-tone sinusoidal signal is applied to a coarse DAC, and it bypasses a fine DAC for test purpose. The obtained DAC output is then fed to a coarse ADC through a bypass path on the load board. Simultaneously, the DAC output is applied to a fine ADC through a PGA path, so that the DAC output signal can fit into the input full-scale range of the fine ADC. For the second loopback test, a sinusoid is fed to a fine DAC, and it bypasses a coarse DAC in this time. Similarly, the DAC output is then applied to a fine and a coarse ADCs through two paths on the load board, at the same time. For postprocessing in on-chip processor, the correlation equations between the dynamic nonlinearities of sub-DACs/ADCs and the aforementioned loopback responses are simultaneously solved to predict the dynamic nonlinearity for each of a DAC and an ADC. Simulation and hardware measurements verified that the proposed technique can be practically used for production testing, by showing less than 0.28-dB and 0.55-dB of the prediction errors, respectively.

An ADC BIST using on-chip ramp generation and digital ORA

This paper presents an on-chip built-in self-test technique for testing an ADC. The conventional test of a mixed signal element has performed through DSP based tester with the help of an arbitrary waveform and a signal digitizer but it is consuming more time and cost. Hence, the testing strategy has started an on-chip BIST based testing scheme to control the testing issues. An on-chip ramp generator based BIST technique has proposed for testing static characteristics of ADC. The evaluation procedure of this BIST consists of test pattern generation and output response analysis. A novel cascode current mirror based analog linear ramp generator has used to generate the test pattern through fast switching TIQ comparator based ADC. Output response analyzer evaluates switching positions of binary code for computing the static parameters. The proposed ADC BIST has implemented in 0.18 μm technology with the supply voltage of 1.8 V.

Built-In Test of Phased Arrays Using Code-Modulated Interferometry

This paper presents a built-in self-test technique for phased arrays that applies code modulation to each element within the array to allow parallel in situ measurements and a built-in distribution network to allow injection or extraction of test signals. The aggregated test response is downconverted from radio-frequency or millimeter-wave frequencies using a direct (power) detector, resulting in a baseband interference signal composed of code-modulated complex cross correlations between all elemental signals. Using orthogonal code products, each cross correlation can be extracted from the interference signal, and then the full set of cross correlations can be used to obtain amplitude and phase data of each element. A four-element 60-GHz phased-array receiver front end that includes this code-modulated embedded test (CoMET) infrastructure has been fabricated in SiGe BiCMOS technology. The BIST overhead is less than 2% of the total die area. Comparisons between our built-in test technique and measurements using a vector network analyzer show that CoMET can be used to extract amplitude with 1 dB accuracy and phase with four degree accuracy. Furthermore, measurements confirm that CoMET can be used to extract the phase-step response of each element in parallel across all settings as well as phase offset introduced by the built-in test network.

Online Built-In Self-Test of High Switching Frequency DC–DC Converters Using Model Reference Based System Identification Techniques

A built-in self-test (BIST) technique that enables tracking of loop parameters of integrated DC–DC converters without affecting the normal mode of operation is presented. A digital pseudo-noise based stimulus and a mixed signal cross-correlation based analysis technique is used to derive on-chip impulse response, with minimum computational requirements in comparison to a digital correlator approach. Using measured impulse response, open-loop phase margin and closed-loop unity-gain frequency are estimated within 5.2% and 4.1% error, respectively, for the load current range of 30 mA to 200 mA. Converter parameters, such as natural frequency, $Q$ -factor, and center frequency are estimated within 3.6%, 4.7%, and 3.8% error, respectively, over load inductance of 4.7 $\mu \text{H}$ to 10.3 $\mu \text{H}$ , and filter capacitance of 200 nF to 400 nF. A 5 MHz switching frequency, 5 V to 8.125 V input voltage range, voltage-mode controlled DC-DC buck converter is designed for the proposed model reference based parametric and non-parametric BIST analysis. The converter output voltage range is 3.3 V to 5 V and supported maximum load current is 450 mA with a peak efficiency of 87.93%. The proposed converter is fabricated on a 0.6 $\mu \text{m}$ 6 layer-metal SOI technology with a die area of 9 mm2. The system identification circuitry occupies 3.8% of the converter area with 530 $\mu \text{A}$ quiescent current during operation.

Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding

A new low-power (LP) scan-based built-in self-test (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministic BIST. During the pseudorandom testing phase, an LP weighted random test pattern generation scheme is proposed by disabling a part of scan chains. During the deterministic BIST phase, the design-for-testability architecture is modified slightly while the linear-feedback shift register is kept short. In both the cases, only a small number of scan chains are activated in a single cycle. Sufficient experimental results are presented to demonstrate the performance of the proposed LP BIST approach.

A Flexible Framework for the Automatic Generation of SBST Programs

Software-based self-test (SBST) techniques are used to test processors and processor cores against permanent faults introduced by the manufacturing process or to perform in-field test in safety-critical applications. However, the generation of an SBST program is usually associated with high costs as it requires significant manual effort of a skilled engineer with in-depth knowledge about the processor under test. In this paper, we propose an approach for the automatic generation of SBST programs. First, we detail an automatic test pattern generation (ATPG) framework for the generation of functional test sequences. Second, we describe the extension of this framework with the concept of a validity checker module (VCM), which allows the specification of constraints with regard to the generated sequences. Third, we use the VCM to express typical constraints that exist when SBST is adopted for in-field test. In our experimental results, we evaluate the proposed approach with a microprocessor without interlocked pipeline stages (MIPS)-like microprocessor. The results show that the proposed method is the first approach able to automatically generate SBST programs for both end-of-manufacturing and in-field test whose fault efficiency is superior to those produced by state-of-the-art manual approaches.

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs

This work presents an efficient on-chip ramp generator targeting to facilitate the deployment of Built-In Self-Test (BIST) techniques for ADC static linearity characterization. The proposed ramp generator is based on a fully-differential switched-capacitor integrator that is conveniently modified to produce a very small integration gain, such that the ramp step size is a small fraction of the LSB of the target ADC. The proposed ramp generator is employed in a servo-loop configuration to implement a BIST version of the reduced-code linearity test technique for pipeline ADCs, which drastically reduces the volume of test data and, thereby, the test time, as compared to the standard test based on a histogram. The demonstration of the pipeline ADC BIST is carried out based on a mixture of transistor-level and behavioral-level simulations that employ actual production test data.

Prebond Testing of Weak Defects in TSVs

Through-silicon vias (TSVs) are critical elements in 3-D integrated circuits susceptible to defects during fabrication and lifetime. It is desirable to detect defective TSVs in the early steps of the fabrication process to prevent stacking yield loss. Thus, the development of effective prebond testing techniques becomes of great importance. In this direction, recent research effort has been devoted to the development of two main prebond techniques: 1) prebond probing and 2) built-in self-test (BIST) techniques. The prebond probing poses economic and technological challenges, whereas current BIST proposals have disadvantages for certain solutions. Hence, there is still a need for an effective methodology in terms of fault coverage, area overhead, and test time. This paper proposes a BIST technique based on a simple unbalanced circuit comparing the behavior of two TSVs. Electrical simulation results show the viability of the proposal to detect weak defects, i.e., resistive opens and resistive bridges, adding reasonable area overhead in a short-test application time. Furthermore, an experimental design is built on a 65-nm technology, where resistive open defects are intentionally injected. Automated test equipment measurements confirm the simulation results.

An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference

The direct radio frequency power injection (DPI) method was extended using on-chip voltage waveform monitoring and built-in self-test techniques. Static random access memory (SRAM) has been chosen as a demonstrator of the extended DPI method and exhibits a higher susceptibility against the lower interference frequency. This response is explained when we consider the time length of the threshold against how long the supply voltage stays lower than the specific voltage determined for a SRAM core. This voltage is also found to be comparable but slightly smaller than the static voltage margin of SRAM cells. In-place measurements using the extended DPI provide an in-depth understanding of the susceptibility and help us to enhance the immunity of VLSI circuits.

Low-Phase Noise Clock Distribution Network Using Rotary Traveling-Wave Oscillators and Built-In Self-Test Phase Tuning Technique

This brief describes a built-in self-test (BIST) technique used to verify and tune the timing integrity of a clock distribution system implemented with injection-locked rotary traveling-wave oscillators (RTWOs). The die is fabricated in a 130-nm CMOS process and occupies 4.4 mm $\times$ 2.25 mm and is limited by the outer diameter of the RTWOs, leaving internal space for other circuits. The BIST circuits take a chip area of only 0.025 $\hbox{mm}^{2}$ . The measured frequency tuning range of the RTWOs is from 1.7 to 2.0 GHz. The measured RTWO phase tuning range is 58.56 $^{\circ}$ with a worst case 0.34 $^{\circ}$ phase tuning resolution. The injection-locked clock multiplication and distribution network achieves a single-sideband integrated RMS jitter of 66.8 fs from 10-kHz to 40-MHz offset frequencies at 2.04-GHz output. The BIST circuit allows testing of the integrity of the clock distribution system at speed by determining if the system clock skew can be tolerated or needs adjustment. To the authors' knowledge, the implementation of this BIST technique to determine clock integrity of an injection-locked clock distribution network has not been explored previously.

Introductory notes for the Acta IMEKO Special Issue on "Technical Diagnostics : New Perspectives in Measurements, Tools and Techniques for Industrial Applications"

The concept of Quality has undergone important transformations over time. In a first assumption, sometimes passed in many industrial contexts, the term “product quality” was essentially associated with “compliance”. Nowadays, the term “conformity to specifications” is widely used but this has to be considered only as an aspect in the measurement of the quality level. In fact, referring to the ISO Standard 9001 Quality management systems, the term Quality corresponds with the degree to which a set of characteristics of an object fulfils requirements. Concerning characteristics, such Standard proposes a classification in physical (e.g. mechanical, electrical, etc.), temporal (e.g. reliability, availability, etc.), and so on. It is interesting to observe that also the concept of product changed over time. Now, it is usual to assume the product as the result of a manufacturing process in which a series of activities transforms raw materials, technologies and resources into the output – that is the product. So, it is mandatory to implement different activities concerning monitoring, as well as to collect and analyse appropriate data with the aim to demonstrate the suitability and the achievement of a desired quality levels. The analysis of data provides information about conformity to product requirements but also related to characteristics and trends of processes and products, including opportunities for preventive actions. This last aspect – the preventive action – depends also on the ability to monitor both the functionality of the product and the capability of the process to fulfil requirements. In this scenario IMEKO TC 10 aims to represent a reference point for scientists and researchers. It can be regarded as a forum for exchanging knowledge and sharing ideas concerning methods, principles, instruments and tools, standards and industrial applications on Technical Diagnostics as well as their diffusion across the scientific community. In this issue two main aspects are considered as a result of different research activities presented in the Workshop. First, the impact of technical diagnostics on the product performances is considered. For this topic different points of view and proposals in the field of fault diagnosis are presented by the authors. B. Aubert et al. deal in [1] with an Extended Kalman Filter based fault detection in Permanent Magnet Synchronous Generators. Being such equipment used often in high technology contexts, it is fundamental to guarantee high performances in terms of reliability and safety. Authors propose a method for inter-turn shortcircuit detection based on the identification of the shortcircuited turns ratio in a faulty PMSG model expressed in Park frame. Several tests are also implemented in order to demonstrate robustness and sensitivity of the approach. In the field of testing for electronic devices an interesting contribution is proposed by D. Zaleski and R. Zielonko in [2]. The paper concerns the testing of analog circuits and blocks in mixed-signal Electronic Embedded Systems (EESs) by means of the Built-in Self-Test (BIST) technique. In particular, two testing functions are performed:

Two-functional µBIST for Testing and Self-Diagnosis of Analog Circuits in Electronic Embedded Systems

The paper concerns the testing of analog circuits and blocks in mixed-signal Electronic Embedded Systems (EESs), using the Built-in Self-Test (BIST) technique. An integrated, two-functional, embedded microtester (µBIST) based on reuse of signal blocks already present in an EES, such as microprocessors, memories, ADCs, DACs, is presented. The novelty of the µBIST solution is its extended functionality. It can perform 2 testing functions: functional testing and fault diagnosis on the level of localization of a faulty element. For functional testing the Complementary Signals (CSs), and for fault diagnosis the Simulation Before Test (SBT) vocabulary techniques have been used. In the fault vocabulary the graphical signatures in the form of identification curves in multidimensional spaces have been applied.

A Review on Structural Software-Based Self- Testing of Embedded Processors

Proposed software-based self-test (SBST) techniques for embedded processor testing recently emerged as an effective substitute to the hardware built-in self-test (BIST) and classical external tester-based testing. These SBST approaches provide the high quality at-speed testing with additional features and reduce the high cost of hardware. This paper presents a survey on the structural software-based self-testing (SBST) of embedded processors for manufacturing test. This paper goes over the main points of structural-based self-testing techniques for manufacturing and functional testing of an embedded processor (e.g. Hierarchical-based and Register-Transfer Level–based (RTL-based)). Finally, an overview of the remarkable accomplishments of SBST and the major challenges faced in making these techniques reliable for industrial processors is presented