Self-test Structure Research Articles

Design of a Cost-Efficient Monostatic Radar Sensor With Antenna on Chip and Lens in Package

This work presents a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${D}$ </tex-math></inline-formula> -band monostatic radar system operating from 144.6 to 161 GHz, which is placed inside a 3-D-printed low-cost case with a built-in lens to boost the antenna (ANT) directivity. The monolithic microwave integrated circuit (MMIC) is manufactured in a 130-nm BiCMOS process and includes a compact transceiver architecture consisting of an oscillator, a diode-based mixer, and an on-chip antenna. The implemented topology allows to significantly improve the signal-to-noise ratio and features a built-in self-test (BIST) structure with the possibility to provide on-chip antenna characterization using power sensors in combination with a directional coupler. Housed inside the robust printed package, the MMIC has only dc and baseband frequency connections, which offers ease of handling and poses the low-cost potential for a variety of applications. The complete transceiver chip consumes only 84.7 mA from a 3.3-V supply and its size is 1964 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times1448\,\,\mu \text{m}$ </tex-math></inline-formula> . Together with the package the sensor measures a size of 42.2 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times42.2$ </tex-math></inline-formula> mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times45.7$ </tex-math></inline-formula> mm.

Embedded Radiation sensor with OBIST structure for applications in mixed signal systems

Oscillation based testing (OBT) has proven to be a simple and effective test strategy for numerous kind of circuits. In this work, OBT is applied to a radiation sensor to be used as a VLSI cell in embedded applications, implementing an oscillation built-in self-test (OBIST) structure. The oscillation condition is achieved by means of a minimally intrusive switched feedback loop and the response evaluation circuit can be included in a very simple way, minimizing the hardware overhead. The fault simulation indicates a fault coverage of 100% for the circuit under test.Keywords: fault simulation, mixed signal testing, OBIST, oscillation-based test, VLSI testing.

A Built-In Self-Test structure for measuring gain and 1-dB compression point of Power Amplifier

This paper proposes a Built-In Self-Test (BIST) structure for measuring the gain and the 1-dB compression point of the Power Amplifier (PA) in transceiver ICs. In this structure, it is not necessary to use the external devices for mapping and DC measuring because of linearity of blocks, comparative performance in the linear region and the digital representation of the 1-dB compression point and gain value. The BIST Circuit is designed and simulated in 180 nm RF-CMOS process with Spectre-RF for a 900 MHz PA while it can achieve an acceptable accuracy which the input referred 1-dB compression point and gain value can be obtained with an error of about 0.2 dBm and 0.18 dB, respectively and the testing time is about 25 µs depends on resolution. Finally, in order to verify the proposed approach, we implemented practically a similar discrete circuit as proof-of-concept prototype that it obtained input referred 1-dB compression point value with an error of about 0.15 dBm.

Conducting functional control of field-programmable gate arrays

Approaches to accomplishing functional control of field-programmable gate arrays (FPGA) are described. The first part of the article describes the existing equipment that allows conducting functional tests of FPGAs. A table comparing the main parameters of the equipment available in the market is given. The table contains the main parameters of the equipment that make it possible to simplify the process of conducting functional tests of FPGAs. The main advantages and disadvantages of using this equipment are shown on the basis of the analysis. In the second part of the article the author describes the main methods of conducting functional tests of FPGAs. When developing algorithms, the author divides all the internal structure of a FPGA into two functionally independent parts. The first part is the internal programmable logic, and the second part contains functional blocks built into a FPGA. The article gives examples of algorithms developed on the basis of the methods described and configuration firm-ware produced with the help of these algorithms. The developed algorithms carry out functional control of the internal logic, as well as of function blocks built into a FPGA. To develop algorithms for functional control of internal logic the author uses the method of iterative logic arrays. A method of creating built- in self-test structures is used for the control of function blocks built into a FPGA. In the final part the author draws conclusions and describes the directions of his further research.

Built‐in self‐test structure for fault detection of charge‐pump phase‐locked loop

A defect-oriented built-in self-test (BIST) structure of charge-pump phase-locked loop (CP-PLL) for high fault coverage and low area overhead test solution is proposed. It employs a new structure of phase/frequency detector, a D flip-flop and some existing blocks in the PLL as the input stimulus generator and fault feature extracted devices for testing evaluation. Thus, no extra test stimulus or high-performance measured instruments are required for test. The structure is easily implemented and has a little influence on the performance of CP-PLL. Fault simulation results indicate that the proposed BIST structure has high fault coverage (98.75%) and low area overhead (0.78%).

Study of self-calibrating MEMS accelerometers

Micro-electromechanical System(MEMS) accelerometers are widely used in a number of inertial navigation systems and vibration detection system thanks to their small size, low cost and low power consumption. In order to improve their performance, the accelerometers have been designed to compensate the zero-bias caused by process variations. A new method of self-calibration sensitivity applies a self-test structure to simulate standard acceleration; depending on the standard and real-time values of the accelerometer’s output and by adjustment of the time division feedback, the scale factor of capacitive accelerometers can be flexibly adjusted to achieve sensitivity in self-calibrating MEMS accelerometers. Moreover, this research also uses the following: a PID feedback structure to improve the stability of the closed-loop system; a correlated double sampling (CDS) circuit to attenuate noise, which can eliminate zero drift caused by offset voltage of the pre-amplifier; a time division multiplexing electrostatic force feedback circuit to achieve the operation of a closed-loop micro-accelerometer. The structure can completely avoid electrostatic feedback coupling with a capacitance change detection circuit, which can also improve the bandwidth and stability of the accelerometer. By means of capacitance compensation array the zero-bias performance of accelerometers can be improved. The bias stability of the accelerometer can be reduced from 173mg to 31mg by testing.

A Built-In Self-Test Structure (BIST) for Resistive RAMs characterization: Application to bipolar OxRRAM

Resistive Random Access Memory (RRAM) is a form of nonvolatile storage that operates by changing the resistance of a specially formulated solid dielectric material [1]. Among RRAMs, oxide-based Resistive RAMs (so-called OxRRAMs) are promising candidates due their compatibility with CMOS processes and high ON/OFF resistance ratio. Common problems with OxRRAM are related to high variability in operating conditions and low yield. OxRRAM variability mainly impact ON/OFF resistance ratio. This ratio is a key parameter to determine the overall performance of an OxRRAM memory. In this context, the presented built-in structure allows collecting statistical data related to the OxRRAM memory array (ON/OFF resistance distributions) for reliability assessment of the technology.

An Efficient 5-Input Exclusive-OR Circuit Based on Carbon Nanotube FETs

An Efficient 5-Input Exclusive-OR Circuit Based on Carbon Nanotube FETs Ronak Zarhoun, Mohammad Hossein Moaiyeri, Samira Shirinabadi Farahani, and Keivan Navi The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube field- effect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design. Keywords: Nanotechnology, carbon nanotube field- effect transistor, CNTFET, high-performance circuits, CNTFET-based inverter, exclusive-OR gate, XOR gate. Manuscript received Jan. 13, 2013; revised Apr. 2, 2013; accepted Apr. 5, 2013. Ronak Zarhoun (phone: +98 2129904195, r.zarhoon@mail.sbu.ac.ir), Mohammad H. Moaiyeri (h_moaiyeri@sbu.ac.ir), and Samira S. Farahani (sa.shirinabadi@mail.sbu.ac.ir) are with the Nanotechnology and Quantum Computing Laboratory, Shahid Beheshti University, G.C., Tehran, Iran. Keivan Navi (corresponding author, navi@sbu.ac.ir, knavi@uci.edu) is with the Quantum Computing Laboratory, Shahid Beheshti University, G.C., Tehran, Iran, and is also with the Department of Electrical Engineering and Computer Science, University of California, Irvine, Irvine, CA, USA. ETRI Journal, Volume 36, Number 1, February 2014 http://dx.doi.org/10.4218/etrij.14.0113.0051 I. Introduction No one can imagine today’s world without the influence and power of computer technology, which dominates many aspects of people’s lives, from such simple details as cell phones to such important and critical projects as those in aeronautics. All computer-based technological improvements are possible through computational functions, which are made up of precise logic gates. Such logic gates as NOT, NAND, NOR, and XOR are the main building blocks of logical functions [1], [2]. Considering these gates, the XOR gate plays a significant role in computational processors with low-power purposes and arithmetic circuits [3], [4], such as full adder cells [5], [6]-[8], parity bit generators and parity checkers [9], multipliers such as the polynomial basis multiplier [10], and comparator circuits [8], [11], [12]. High-speed XOR gates are needed for summation of partial products in multiplier circuits, and they are also used in MUX modules in arithmetic circuits [12]. The most famous application of the XOR gate is in coding processes and data encryption or decryption, especially in AES (Advanced Encryption Standard) [1], which is sufficiently used in data communication. In design testing, it is used in built-in self-test structures [10] and is essential in cryptography [9], FPGAs, and high-performance structures. The XOR gate is even used in compressors, phase detectors, error detection, and error correction circuits [13]. Digital signal processor circuits with a logarithmic number system composed of several multipliers and adders benefits from XOR gates [14]. Moreover, the important role of this gate has even appeared in optical telecommunication networks for bit pattern recognition, operations related to address comparison, and so on [15], [16]. Design and development of XOR gates with conventional CMOS architecture is limited by the number of its inputs. As a Ronak Zarhoun et al.

An Efficient 5-Input Exclusive-OR Circuit Based on Carbon Nanotube FETs

An Efficient 5-Input Exclusive-OR Circuit Based on Carbon Nanotube FETs Ronak Zarhoun, Mohammad Hossein Moaiyeri, Samira Shirinabadi Farahani, and Keivan Navi The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube field- effect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design. Keywords: Nanotechnology, carbon nanotube field- effect transistor, CNTFET, high-performance circuits, CNTFET-based inverter, exclusive-OR gate, XOR gate. Manuscript received Jan. 13, 2013; revised Apr. 2, 2013; accepted Apr. 5, 2013. Ronak Zarhoun (phone: +98 2129904195, r.zarhoon@mail.sbu.ac.ir), Mohammad H. Moaiyeri (h_moaiyeri@sbu.ac.ir), and Samira S. Farahani (sa.shirinabadi@mail.sbu.ac.ir) are with the Nanotechnology and Quantum Computing Laboratory, Shahid Beheshti University, G.C., Tehran, Iran. Keivan Navi (corresponding author, navi@sbu.ac.ir, knavi@uci.edu) is with the Quantum Computing Laboratory, Shahid Beheshti University, G.C., Tehran, Iran, and is also with the Department of Electrical Engineering and Computer Science, University of California, Irvine, Irvine, CA, USA. ETRI Journal, Volume 36, Number 1, February 2014 http://dx.doi.org/10.4218/etrij.14.0113.0051 I. Introduction No one can imagine today’s world without the influence and power of computer technology, which dominates many aspects of people’s lives, from such simple details as cell phones to such important and critical projects as those in aeronautics. All computer-based technological improvements are possible through computational functions, which are made up of precise logic gates. Such logic gates as NOT, NAND, NOR, and XOR are the main building blocks of logical functions [1], [2]. Considering these gates, the XOR gate plays a significant role in computational processors with low-power purposes and arithmetic circuits [3], [4], such as full adder cells [5], [6]-[8], parity bit generators and parity checkers [9], multipliers such as the polynomial basis multiplier [10], and comparator circuits [8], [11], [12]. High-speed XOR gates are needed for summation of partial products in multiplier circuits, and they are also used in MUX modules in arithmetic circuits [12]. The most famous application of the XOR gate is in coding processes and data encryption or decryption, especially in AES (Advanced Encryption Standard) [1], which is sufficiently used in data communication. In design testing, it is used in built-in self-test structures [10] and is essential in cryptography [9], FPGAs, and high-performance structures. The XOR gate is even used in compressors, phase detectors, error detection, and error correction circuits [13]. Digital signal processor circuits with a logarithmic number system composed of several multipliers and adders benefits from XOR gates [14]. Moreover, the important role of this gate has even appeared in optical telecommunication networks for bit pattern recognition, operations related to address comparison, and so on [15], [16]. Design and development of XOR gates with conventional CMOS architecture is limited by the number of its inputs. As a Ronak Zarhoun et al.

Charge-Controlled Readout and BIST Circuit for MEMS Sensors

In this paper, we present a new readout circuit with an integrated built-in self-test (BIST) structure for capacitive microelectromechanical system (MEMS). In the proposed solution, instead of commonly used voltage control signals to test the device, charge-controlled stimuli are employed to cover a wider range of structural defects. The proposed test solution eliminates the risk of structural collapse in the test phase for gap-varying parallel-plate MEMS devices. Measurement results using a prototype fabricated in TSMC 65-nm CMOS technology indicate that the proposed BIST scheme can successfully detect minor structural defects altering MEMS nominal capacitance.

Genetic algorithm for test pattern generator design

The paper describes an approach for the generation of a deterministic test pattern generator logic, which is composed of D-type and T-type flip-flops. This approach employs a genetic algorithm that searches for an acceptable practical solution in a large space of possible implementations. In contrast to conventional approaches the proposed one reduces the gate count of a built-in self-test structure by concurrent optimization of multiple parameters that influence the final solution. The optimization includes the search for: the optimal combination of register cells type; the presence of inverters at inputs and outputs; the test patterns order in the generated test sequence; and the bit order of test patterns. Results of benchmark experiments and comparison with similar studies demonstrate the efficiency of the proposed evolutionary approach.

A System-layer Infrastructure for SoC Diagnosis

During IC manufacturing phase, discriminating between good and faulty chips is not enough. In fact, especially in the first phase of the production of a new device, a complete understanding of the possible failures is quickly required to ramp up production yield. For test engineers, dealing with the manufacturing test of Systems-on-chip (SoCs) means to tackle the extraction of diagnostic data from faulty chips. Another equally important aim of diagnosis, in a later step of a product lifecycle, is to find the real root cause of silicon misbehaviors for field returns. At the core test layer, the adoption of diagnosis-oriented Design-for-Testability structures is almost mandatory and many solutions have been worked out for several types of cores; diagnosis data retrieval often consists in the execution of a set of self-test procedures whose application order and/or customization may depend on the obtained results themselves. This paper details the characteristics of a system-layer test architecture able to manage efficiently SoC self-diagnostic procedures. This architecture is composed of a diagnosis-oriented Test Access Mechanism (TAM) and an Infrastructure-IP owning enough intelligence to automatically manage core diagnostic procedures. Both of them have been designed in compliance with the IEEE 1500 Standard for Embedded Core Test and exploit the characteristics of Self-Test structures inserted for the diagnosis of memory, processor and logic cores. This approach to SoC diagnosis minimizes ATE memory requirements for pattern storage and drastically speeds up the complete execution of diagnostic procedures. Experimental results highlight the convenience of the approach with respect to alternative ATE driven diagnosis procedures, while resorting to negligible area overhead.

Estimating Error Rate in Defective Logic Using Signature Analysis

As feature size approaches molecular dimensions and the number of devices per chip reaches astronomical values, VLSI manufacturing yield significantly decreases. This motivates interests in new computing models. One such model is called error tolerance. Classically, during the postmanufacturing test process, chips are classified as being bad (defective) or good. The main premise in error-tolerant computing is that some bad chips that fail classical go/no-go tests and do indeed occasionally produce erroneous results actually provide acceptable performance in some applications. Thus, new test techniques are needed to classify bad chips according to categories based upon their degree, of acceptability with respect to predetermined applications. One classification criterion is error rate. In this paper, we first describe a simple test structure that is a minor extension to current scan-test and built-in self-test structures and that can be used to estimate the error rate of a circuit. We then address three theoretical issues. First, we develop an elegant mathematical model that describes the key parameters associated with this test process and incorporates bounds on the error in estimating error rate and the level of confidence in this estimate. Next, we present an efficient testing procedure for estimating the error rate of a circuit under test. Finally, we address the problem of assigning bad chips to bins based on their error rate. We show that this can be done in an efficient, hence cost-effective, way and discuss the quality of our results in terms of such concepts as increase effective yield, yield loss, and test escape

Self-calibration of input-match in RF front-end circuitry

The input match of RF front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input pad. The proposed technique ascertains the input match frequency of the circuit by using a built-in self-test (BiST) structure, determines the frequency interval by which it needs to be shifted to restore it to the desired value, and then feeds back a digital word to the low-noise amplifier (LNA), which adaptively corrects its input-match in real-time. The circuitry presented in the paper offers the advantages of low power overheads (the circuits can be powered off when not in use), robustness, no requirements of digital signal processing cores or processors, and fast calibration times (less than 30 /spl mu/s). This proof of concept is demonstrated by designing a cascode LNA and the complete self-calibration circuit in IBM 0.25-/spl mu/m CMOS RF process.

Built-In Self-Test for Phase-Locked Loops

An effective built-in self-test (BIST) structure of a phase-locked loop (PLL) in digital applications is presented in this paper. The proposed BIST structure can identify possible faults in any block such as the phase detector, charge pump, loop filter, voltage-controlled oscillator and divide-by-N of the PLL. The key advantage of this approach is that it uses all existing blocks in PLL for measuring and testing, reducing the chip area overhead. Restated, the proposed approach does not alter any existing analog circuits. Rather, the proposed approach only adds some small circuits to the PLL and requires a slight modification of the digital part. The final test outputs are digital values which can increase the reliability of the proposed BIST structure. Physical chip design and fault simulation results indicate the characteristics of the proposed BIST structure, namely, high fault coverage (97.2%) and low area overhead (2.78%).

LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects

For system-on-chips (SoC) using deep submicron (DSM) technologies, interconnects are becoming critical determinants for performance, reliability and power. Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods propose inserting dedicated interconnect self-test structures in the SoC to generate vectors which have high crosstalk defect coverage. However, these methods may have a prohibitively high area overhead. To reduce this overhead, existing logic BIST structures like LFSRs could be reused to deliver interconnect tests. But, as shown by our experiments, use of LFSR tests achieve poor crosstalk defect coverage. Additionally, it has been shown that the power consumed during testing can potentially become a significant concern. In this paper, we present Logic-Interconnect BIST (LI-BIST), a comprehensive self-test solution for both the logic of the cores and the SoC interconnects. LI-BIST reuses existing logic BIST structures but generates high-quality tests for interconnect crosstalk defects, while minimizing the area overhead and interconnect power consumption. The application of the LI-BIST methodology on example SoCs indicates that LI-BIST is a viable, low-cost, yet comprehensive solution for testing SoCs.

A current-mode BIST structure of DACs

An effective and accurate current-mode built-in self-test (BIST) structure for DACs is presented. Differential V/ I converters are used to convert the differences between the analog output voltages of the DACs and the voltage of references into currents. The offset error, gain error, integral nonlinearity ( INL) and differential nonlinearity ( DNL) are tested to examine whether they are within their acceptable ranges by a window current comparator. With a high performance integrator to generate a ramp signal as the reference for INL tests, the number of reference voltages can be greatly reduced such that the chip area overhead can be saved. High precision is also an advantage of this test structure due to the feature of the higher acceptable dynamic range in the current-mode design.

Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs

In this paper, we present a novel fault detection and fault diagnosis technique for Field Programmable Gate Arrays (FPGAs). The cell is configured to implement a bijective function to simplify the testing of the whole cell array. The whole chip is partitioned into disjoint one‐dimensional arrays of cells. For the lookup table (LUT), a fault may occur at the memory matrix, decoder, input or output lines. The input patterns can be easily generated with a k‐bit binary counter, where k denotes the number of input lines of a configurable logic block (CLB). Theoretical proofs show that the resulting fault coverage is 100%. According to the characteristics of the bijective cell function, a novel built‐in self‐test structure is also proposed. Our BIST approaches have the advantages of requiring less hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, two diagnosis sessions are required. However, the maximum number of configurations is k + 4 for diagnosing a faulty CLB. The diagnosis complexity of our approach is also analyzed. Our results show that the time complexity is independent of the array size of the FPGA. In other words, we can make the FPGA array C‐diagnosable.

Digital Signature Proposal for Mixed-Signal Circuits

A new Built-In Self-Test structure, based on the information provided by the XY-operation (Lissajous curves) is introduced in this paper. A Digital Signature is obtained which is used to discriminate catastrophic as well as parametric defects. High Fault Coverage is achieved when applying the proposed BIST on an ITC'97 benchmark circuit where 92% of the catastrophic defects and 87.5% of the parametric defects analyzed produced digital signatures clearly distinguishable from the golden signature.

Testing Configurable LUT-Based FPGAs

A novel approach to testing lookup table (LUT) based field programmable gate arrays (FPGAs) is proposed in this paper. A general structure for the basic configurable logic array blocks (CLBs) is assumed. We group k CLBs in the column into a cell, where k denotes the number of inputs of an LUT. The whole chip is configured as a group of one-dimensional iterative logic arrays of cells. We assume that in each linear cell array, there is at most one faulty cell, and that multiple faulty CLBs in the same cell can be detected. For the LUT, a fault may occur at the memory matrix, decoder, input or output lines. The switch stuck-on and stuck-off fault models are adopted for multiplexers. New conditions for C-testability of programmable reconfigurable arrays are also derived. Our idea is to configure the cells so as to make each cell function bijective. This property is helpful for applying pseudoexhaustive test patterns to each cell and propagating errors to the observable outputs. In order to detect all the faults defined, k+2 configurations are required, and the resulting number of test patterns is 2(superscript k). A novel built-in self-test structure is also proposed in this paper. The input patterns can be easily generated with a k-bit counter. The number of configurations for our BIST structures is 2k+4. Our BIST approaches also have the advantage of requiring fewer hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, three test sessions are required. However, the maximum number of configurations for diagnosing a faulty CLB is k+4.