Self-controllable Voltage Level Technique Research Articles

Analysis of 7T SRAM Cell Based on MTCMOS, SVL and I-SVL Technique

Objective: To design and propose an optimized Volatile 7T based SRAM cell in terms of leakage currents and dynamic power. Methods: The methodology involved is Multi threshold Voltage CMOS (MTCMOS), Self Controllable Voltage Level (SVL) and Improved Self Controllable Voltage Level (I-SVL). Findings: The proposed work demonstrates that 7T based SRAM cell using I-SVL method is efficient in terms of leakage currents and dynamic power. Also, Comparative Leakage current and dynamic power analyses are done between MTCMOS, SVL, and I-SVL methods The Proposed work based on I-SVL is significant than the MTCMOS and SVL Technique. All the circuits are developed using the Cadence virtuoso tool and spectre simulator is used to carry out the simulation. Novelty: The paper proposes Low power Volatile Memory cell based on 7T with improvements in leakage and dynamic power values in comparison with the earlier literatures. The proposed I-SVL based cell is 89% and 85% efficient in terms of dynamic power in comparison with the earlier references. Keywords: Improved – Self Controllable Voltage Level (I-SVL); Improved Lower SVL (I-LSVL); Improved Upper SVL (I-USVL); Multi threshold Voltage CMOS(MTCMOS); Self Controllable Voltage Level (SVL); SRAM

Leakage Reduction in 18 nm FinFET based 7T SRAM Cell using Self Controllable Voltage Level Technique

As the technology is scaled the power consumption increases significantly, because of which the battery life of portable devices is reduced. Due to high power density, the increased power consumption becomes an obstacle for scaling of devices. Power optimization is the most significantly visible in future portable IC’s. As per increasing need for a low power circuit, the reduction in leakage current becomes very important aspect while designing any IC. The leakage can be reduced by altering the threshold voltage. Further as the technology is scaled FinFET is the alternate for CMOS with increased control of gate over the channel. In this paper a FinFET based 7T SRAM cell is proposed which is faster in its operation and consumes less power. In order to further reduce the leakage power, FinFET based 7T SRAM cell is designed using self-controllable voltage level (SVL) techniques. In this paper, an 18 nm FinFET based SRAM cell is designed using SVL circuit to reduce the leakage current and power. The proposed design has the least leakage current of 16.56 nA and leakage power of 11.59 nW by using the combined technique of LSVL and USVL. All the circuit design and simulation have been done in Cadence Virtuoso using 18 nM FinFET technology.

Dual-mode power reduction technique for real-time image and video processing board

In real-time image and video processing boards, power, speed, and area are the most often used measures for determining the performance of motion imagery applications. Due to technological advancement, power consumption has gained major attention in real-time image processing ability compared to speed. The increase in on-chip temperature due to larger power consumption has resulted in reduced operating life of chip and battery-driven devices. In this work, a new logic family has been introduced i.e., dual-mode logic (DML), which provides flexibility between the optimization of energy and delay (E-D optimization). This gate can be switched between two modes of operation that is a static mode (CMOS-like mode), which provides low power consumption and dynamic mode, which provides high speed. Recently, power leakage has become a dominant problem due to continuous data transfer among a large number of connected devices. Thus, to reduce power leakage, a self-controllable voltage level (SVL) power reduction technique is used along with DML logic. In the SVL technique, a maximum dc voltage is provided to the active load circuit on-demand or decrease the dc supplied to the load circuit in the standby mode. Integrating DML with the SVL technique reduces power consumption as well as leakage power. A 4-bit RCA, 8-bit RCA, and 16-bit RCA are used for verifying the proposed method and comparison of performance parameters is done with a conventional circuit. Complete circuit implementation and simulation are carried out in TANNER EDA version 13 tools with operating voltage of 1 V. The proposed system is further applied to real-time image, and we obtain the finest resolution level with minimum power consumption.

Low power, high speed Schmitt trigger using SVL technique in nanoscale CMOS technology

Schmitt trigger device is mostly used in analogue and digital circuit as a wave-shaping device to resolve the noise problem, widely used to drive the load with fast switching low-power loss and low-power supply. Conventional Schmitt trigger provides more leakage power, so 4T Schmitt trigger overcomes this problem by using the Self-Controllable Voltage Level (SVL) techniques. The main purpose of this paper is to present the performance factor of Schmitt trigger by applying U-SVL and L-SVL and both technique. The simulation results perform in cadence tool and reported that static power (3.98 fW), dynamic power (38.04 pW), propagation delay (6.13 psec), hysteresis width (0.877 V), voltage gain (30.03 dB), periodic jitter (80 ns), frequency jitter (24.26 kHz), efficiency (63.06%), spectral power (5.388 aW), transconductance (7.17 × 10−14 S) and the total leakage power of individual transistors (1.17 pW) improve using both U-SVL and L-SVL techniques simultaneously with nanoscale measurement with supply voltage Vdd=0.7 V.

Minimizing Power Consumption in CMOS Full Subtractor using SVL Technique

Full Subtractor using Self Controllable Voltage Level (SVL) Technique is designed in this paper. The circuit can supply an increased dc voltage to an active-load circuit required or can decrease the dc voltage supplied to a load circuit under standby mode is developed. Full Subtractor is a consumed low power and low Leakage as compare to conventional design with SVL technique. We may reduce the value of total power dissipation by applying the U-SVL (upper Self Controllable voltage level) technology in which the supply potential is increased and L-SVL (Lower Self Controllable voltage level) technology in which the ground potential is raised. The analysis paper represents how to control power using SVL techniques. The SVL technique based Full Subtractor compared to conventional design that based on power consumption, propagation delay speed and layout area is more preferred. Low-power techniques projected to reduce power in nanoscale CMOS-Very Large Scale Integration (VLSI) systems, Using SVL technique. The result shows that there is significant reduction in Power assimilation of Full Subtractor in reference mode. This design is much useful in designing the system that low power consumed. The circuit is designed using Cadence Tools in 45nm Technology.