Self-checking Circuits Research Articles

Application of byte error detecting codes to the design of self-checking circuits

In this paper, we discuss the application of byte error detecting codes to the design of self-checking circuits for the single stuck-at fault model. We discuss strongly fault-secure realization of a given Boolean function using byte error detecting codes. Even though parity is the most efficient separable code for the detection of single errors, we show that the use of a byte error detecting code can lead to lower cost of self-checking realization of a given function as compared to its self-checking realization using the parity code. We also present a method for the design of totally self-checking checkers for byte error detecting codes. Experimental results obtained for various test circuits are also discussed.

Concurrent checking of clock signal correctness

Traditional concurrent-checking techniques may not detect the occurrence of the transient faults and resulting errors likely to affect clock signals in VLSI systems. The authors present a new method and self-checking circuit implementation for concurrently checking the correctness of clock distribution network signals in synchronous systems.

On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits

This paper investigates the detection of parametric bridging and delay faults affecting the functional block of CMOS self-checking circuits (SCCs). As far as these faults are concerned, classical definitions are shown to become ambiguous because they are entirely based on logic considerations. Thus, new definitions are proposed here to consider the analog and dynamic effects of such faults, and to ensure that they do not produce any problem at the system level. Moreover, electrical level design rules aimed at satisfying these conditions are proposed for self-checking circuits with combinational functional blocks. The problem of their practicability and effectiveness is analyzed in detail, and is shown by means of significant examples.

Logic synthesis of multilevel circuits with concurrent error detection

This paper presents a procedure for synthesizing multilevel circuits with concurrent error detection. All errors caused by single stuck-at faults are detected using a parity-check code. The synthesis procedure (implemented in Stanford CRCs TOPS synthesis system) fully automates the design process, and reduces the cost of concurrent error detection compared with previous methods. An algorithm for selecting a good parity-check code for encoding the circuit outputs is described. Once the code has been selected, a new procedure called structure-constrained logic optimization is used to minimize the area of the circuit as much as possible while still using a circuit structure that ensures that single stuck-at faults cannot produce undetected errors. It is proven that the resulting implementation is path fault secure, and when augmented by a checker, forms a self-checking circuit. The actual layout areas required for self-checking implementations of benchmark circuits generated with the techniques described in this paper are compared with implementations using Berger codes, single-bit parity, and duplicate-and-compare. Results indicate that the self-checking multilevel circuits generated with the procedure described here are significantly more economical.

An optimal single error locating TSC-TMRsystem

A triple modular redundancy (TMR) system incorporates majority voting to achieve fault tolerance, although not all single faults can be tolerated due to the possibility of voter failure. A totally self-checking (TSC) circuit is introduced to monitor the TMR system; it receives the outputs of each module and that of the voter to generate three system statuses, and three module status outputs. The TSC–TMR system has the capability to detect all single fault occurrences inclusive of the checking circuitry, thus achieving optimum availability and maintainability regarding single fault occurrences. Morphic Boolean algebra forms the basis of the TSC fault detecting circuit design. Morphic building blocks constitute the newly designed checking circuit.

Probability to achieve TSC goal

We propose a probabilistic measure for self-checking (SC) circuits that is analogous to reliability of fault-tolerant systems. This measure is defined as the probability to achieve totally self-checking (TSC) goal at the lth cycle: TSCG(t). TSCG provides insight to the worst case dynamic behavior of SC circuits with respect to the application environment and component failure rates. TSCG surpasses the TSC definitions in determining the applicability of a circuit in a given application environment. An SC circuit achieves TSC goal when no erroneous information or data is propagated beyond the boundary of this circuit. TSCG is therefore the probability that this fault confinement mechanism is intact. The SC properties are obtained through adding hardware redundancy to the original digital design, which means that an SC circuit has a higher failure rate than the original circuit. Further, there are tradeoffs between the level of hardware redundancy, the reliability, and the TSCG. We give several examples to clearly demonstrate these tradeoffs for different design environments. We emphasize that the TSCG is intended to provide a mean of dynamic error handling performance evaluation of SC designs. The TSC definitions and alike are still intact, since a cost-effective SC circuit must begin with a TSC circuit. The TSCG gives confidence in the use of cost-efficient error control codes and/or reduction in error handling capability. Analogous to reliability, the TSCG can be used in product specifications. This is a crucial step toward the practical applications of TSC or CED circuits.

A hyper optimal encoding scheme for self-checking circuits

A typical self-checking circuit has an unordered code encoded output. The optimal scheme needs [log(r+1)] check bits, where r is the number of unique weights in all output patterns. A hyper optimal scheme for self-checking output encoding is proposed in this paper where the number of check bits will be further reduced in some cases. Two algorithms are presented to search for the hidden m-out-of-n code words. The hidden m-out-of-n code words are found when all unique output patterns, specified by the circuit specification, in the n selected output bits have exactly m 1s. The output bits that belong to the hidden m-out-of-n code words are then excluded from further encoding. Typically, the number of added check bits of the proposed technique ranges from 0 to [log(p+1)], where p/spl les/r. When hidden m-out-of-n code words exist, applying the proposed scheme usually results in significant hardware cost and delay time reduction. In the five MCNC FSM benchmark circuits that have been identified with hidden m-out-of-n code words, 10% to 41% hardware reductions are exhibited compared to the theoretically optimal separable code encoding scheme. In addition, 7% to 45% reductions in checking delays are demonstrated for the same circuits compared to the separable code encoding scheme.

Self-checking design in Eastern Europe

This survey introduces the design concepts of self-checking circuits and discusses research activities in on-line hardware-checking techniques developed in Eastern Europe, including the former Soviet Union. Many of the research results appeared in journals and conference proceedings previously unavailable to Western researchers.

Accurate self-checking digital teraohmmeter

We describe a digital teraohmmeter achieving state-of-the-art linearity, stability, and accuracy. Proper shielding, guarding, and measurement reproducibility having been addressed by hardware design, the instrument employs automatic self-checking circuits and routines to help maintain a linearity of 50 ppm when working over 10/sup 6/-10/sup 12/ /spl Omega/ in resistance, 1-1000 V in test voltage, and 1 pA-1 /spl mu/A in test current. It can measure high-resistance standards up to 10/sup 15/ /spl Omega/ with a standard uncertainty not exceeding 100 ppm after a traceable calibration of its internal reference at the 1-M/spl Omega/ level. In a laboratory, an annual calibration should suffice. >

Evaluating the safety of self-checking circuits

In this paper, we consider the evaluation of the safety of a self-checking circuit with combinational logic. Since the circuit is tested under normal operation, it may stay in different states such as a perfect state in which any erroneous output can be detected, unstable states in which an erroneous output may be detected or may not, a safe-state when the erroneous output has been caught, and a fail-state because the erroneous output is undetected, as time goes on. Consequently, we propose a fail-safe evaluation, using a Markov model to describe the state transitions and predicate the probability of the circuit not being in the fail-state.

Self-timed is self-checking

Self-checking circuits detect (at least some of) their own faults. We describe self-timed circuits, including combinational logic and sequential machines, which either halt or generate illegal output if they include any single stuck-at faults. The self-timed circuits employ dual rail data encoding to implement ternary logic of 0, 1, andundefined states; the fourth state is used to signal illegal output and is shown to result only from certain circuit faults. The self-timed circuits also employ four-phase signaling according to a well-defined protocol of communications between the circuit and its environment; failures due to certain faults prevent the circuit from communicating properly, thus causing the circuit to halt. We show that any single stuck-at fault falls in either the first or the second category, thus providing complete fault coverage through self checking. No hardware needs to be added to our circuits to achieve the complete self-checking property; further, the circuit is guaranteed to never generate a legal but erroneous output if it contains a fault. Minimal hardware is needed to detect that a circuit has either halted or has generated an illegal output.

Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults

This work presents a design technique for CMOS static and dynamic checkers (to be used in self-checking circuits), that allows the detection of all internal single transistor stuck-on and bridging faults causing unacceptable degradations of the circuit dynamic performance (but not logical errors). Such a technique exploits simple voltage detector circuits to make sure that the intermediate faulty voltages inevitably produced by the faults of interest are always propagated at the checker output as logic errors. With the use of our technique, the main disadvantages of static checkers, so far preventing their use in practical applications, are overcome. The method has been applied to the particular case of two-rail (static as well as dynamic) checkers and its validity has been verified by means of electrical level simulations.

A strongly code disjoint built-in current sensor for strongly fault-secure static CMOS realizations

We present a strongly code disjoint (SCD) built-in current sensor (BICS) based on self-exercising concept. The integration of this SCD BICS with a self-checking circuit achieves the totally self-checking goal in static CMOS realizations, even in the presence of stuck-on and bridging faults, and results in a strongly fault-secure realization. Low-cost and high fault coverage is attractive for many high reliability and critical applications. >

Design of CMOS self-checking sequential circuits with improved detectability of bridging faults

Problems due to the presence of resistive bridging faults within sequential functional blocks of self-checking circuits are studied, and design criteria aimed at reducing their effects are proposed. >

Design and DCVS implementation of a self-checking bus-monitor unit for highly reliable fault-tolerant system configurations

We present the design and implementation of a bus-monitor unit targeted for the design of highly reliable fault-tolerant systems. The bus-monitor is designed using differential cascode voltage switch (DCVS) logic, whose inherent characteristics result in self-checking circuits. It is implemented in an application specific integrated circuit that can be used to implement a variety of fault-tolerant architectures including triple modular redundant and hybrid configurations. The unit is capable of detecting and correcting failures in the redundant modules by monitoring their respective buses, and it delivers fault-free data to the destination modules. The unit is also capable of detecting faults occurring in the unit itself by utilizing the fault secure properties of DCVS logic. In this paper, we present the operation of the bus-monitor unit and we describe its DCVS design and implementation, as well as the performance characteristics of the prototype chips. Finally, we illustrate how the bus-monitor unit(s) can be used to implement highly reliable fault-tolerant architectures, and we demonstrate that architectures designed using the developed unit(s) exhibit higher reliability compared to the ones implemented with CMOS logic, using the same number of computational resources. >

Enhanced reliability evaluation for self-checking circuits

A first attempt at evaluating the reliability of the checkers used in self-checking circuits is presented. Simple theory is proposed to compare different checker implementations that, although totally self-checking in the conventional sense, may perform differently under more realistic fault conditions. As a significant example of application, the case of the 1-out-of-3 checker is explicitly treated.

Self-checking combinational circuit design for single and unidirectional multibit error

This article presents novel input and output encoding techniques such that the resulting circuit is bidirectional error-free. The circuit can be fully optimized and any types of gates can be used. These schemes are used to design the functional part of a self-checking circuit. The input encoding algorithm can be applied to any circuit without significantly increasing the input lines. The output encoding technique involves graph-embedding which is done with heuristic method of polynomial complexity. The heuristic technique produces nearly optimal output encoding. Previously published work restrict the types of gates used in the circuit to non-inversion gates (AND/OR), and use inverters only at the inputs. The proposed techniques have a clear advantage over the currently available techniques because they allow the use of any types of gates. These techniques do not necessarily increase the overhead when applied to different MCNC benchmark circuits as the experimental results indicate. The only restriction is that either the inputs or the outputs have to be symbolic, and the two-level description of a circuit has to be given.

Design and synthesis of self-checking VLSI circuits

Self-checking circuits can detect the presence of both transient and permanent faults. A self-checking circuit consists of a functional circuit that produces encoded output vectors and a checker that checks the output vectors. The checker has the ability to expose its own faults as well. The functional circuit can be either combinational or sequential. A self-checking system consists of an interconnection of self-checking circuits. The advantage of such a system is that errors can be caught as soon as they occur; thus, data contamination is prevented. Methods for the cost-effective design of combinational and sequential self-checking functional circuits and checkers are examined. The area overhead for all proposed design alternatives is studied in detail. >

Design of self-checking circuits using DCVS logic: a case study

A technique for designing self-checking circuits using differential cascode voltage switch (DCVS) logic is presented. This technique is used in a design case study and the results obtained through actual implementation and testing of a self-checking circuit are discussed. It is demonstrated that the self-checking capability of the circuit can be used to implement fault tolerance at low hardware-overhead costs. >

Self-checking CMOS circuits using pass-transistor logic

This article presents a new approach to implementing self-checking circuits in CMOS technology. Implementations are made self-checking with respect to a single line stuck-at 0/1 fault. It is assumed that stuck faults at a common gate of neighboring PMOS and NMOS are not independent and the contact between a PMOS (NMOS) source and a power (ground) line is fault free. Self-checking error checkers for parity, two-rail code, and m-out-of-n code are designed using pass-transistor logic and then verified by fault simulation.