Self-calibration Circuit Research Articles

Accurate Low Current Measurement Electronics With Self-Calibration Function for Ionization Chamber of Slow Extraction in HIAF

The new wide-range readout electronics with a self-calibration function are designed for ionization chambers (ICs) in the slow extraction of high-intensity heavy-ion accelerator facility (HIAF), booster ring (BRing). These electronics consist of a programmable trans-impedance amplifier (TIA), a self-calibration circuit, an 18-bit analog-to-digital converter (ADC), and a ZYNQ-7015 field-programmable gate array (FPGA). It is capable of monitoring weak current signals of 40 pA–4 mA with a sampling rate of 5 MHz. The ZYNQ-7015 FPGA manages the operation mode of the analog front-end (AFE) and the gain of the TIA. It also performs digital signal processing algorithms and data communication with the host computer. The self-calibration circuit uses a combination of a Schmitt trigger and voltage-to-current (V–I) converters to generate two square wave current signals with different peaks ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2 \mu \text{A}$ </tex-math></inline-formula> and 2 mA). During offline tests, the effective number of bits (ENOB) is 12.98 bits, and the nonlinearity is less than 0.075% for a full scale. Finally, the readout electronics are deployed for ICs’ slow extraction measurements at the extraction line of the cooling storage ring of the heavy-ion research facility in Lanzhou (HIRFL). With the help of a commercial dc-transformer in the cooling storage ring project of heavy ion research facility in Lanzhou (HIRFL-CSR), these electronics not only execute an accurate current measurement, but also can monitor the extraction efficiency reliably. In a word, these electronics play an important role in the fields of extremely weak and high dynamic current signal measurements.

Design and implementation of high-precision voltage measurement system based on Kalman filter and automatic calibration technology

With the rapid development of science and technology, precision measurement is of increasing importance. In this paper, we discuss noise reduction and automatic calibration issues for a high-precision voltage measurement system that covers voltages from 0.1 µV to 300 V and a frequency range from 10 Hz to 300 kHz (including DC). First, a modified Kalman filter is proposed to reduce measurement noise. Then, a self-calibration circuit is constructed to eliminate the systematic errors in DC voltage (DCV) measurements. Finally, a wideband AC calibration model is developed to overcome the defects in AC voltage (ACV) measurements caused by AC characteristics. The measurement application demonstrates the effectiveness of the proposed methods----the designed voltage measurement system has a DCV measurement accuracy of better than 9 µV/V and a high ACV accuracy of 0.25 mV/V in the frequency range of 30 Hz to 30 kHz at an ambient temperature of 25 °C. In addition, the minimum DC measurement uncertainty obtained on the DCV 10 V range is 0.4 μV/V (type A) and the minimum AC measurement uncertainty obtained on the ACV 10 V range is 2 μV/V (type A).

Self-Aligning and Self-Calibrating Capacitive Sensor System for Displacement Measurement in Inaccessible Industrial Environments

High-precision positioning often requires high speed and high resolution displacement measurements in order to compensate for the small vibrations of critical components. The displacement sensor must be precise and stable over a long period of time to avoid expensive recalibration. This requires tight mounting tolerances, which are especially difficult to meet in inaccessible environments. The proposed sensor system is based on a capacitive sensor and consists of three subsystems: 1) a mechanical “zoom-in” system that performs self-alignment of the capacitive sensor electrode in order to reduce the mounting tolerances of the sensor; 2) a real-time capacitance-to-digital converter that employs an internal reference and electrical zoom-in technique to effectively reduce the dynamic range of the measured capacitance, thus improving the power efficiency; and 3) a self-calibration circuit that periodically calibrates the internal references to eliminate their drift. In previous publications, the three subsystems have been introduced. This paper shows how the different subsystems can be integrated to achieve optimal performance and presents new repeatability and stability measurement results. The overall system demonstrates a displacement measurement resolution of 65 pm (in terms of capacitance 65 aF) for a measurement time of 20 $\mu \text{s}$ . Furthermore, the thermal drift of the sensor is within 6 ppm/K, owing to the self-calibration circuit. In measurement mode, the system consumes less than 16 mW.

Measurement Algorithm of Clock Jitter Based on Sequential Equivalent Sampling

For the problem that general characteristic impedance measurement instrument is difficult to measure the size of clock jitter, this paper proposes a measurement algorithm to achieve clock jitter based on sequential equivalent sampling. First, according to the relationship between the equivalent sampling signal and the average signal, we count up the probability density distribution of the clock jitter and use the Tailfit jitter separation techniques to decompose total jitter (TJ) into deterministic jitter (DJ) and random jitter (RJ), then count up the peak-to-peak values of periodic jitter (PJ), cycle-to-cycle jitter (CCJ) and time interval error (TIE) to achieve a precise measurement of clock jitter. Finally we use the test results of jitter analysis software of Tektronix’s TDSJIT3 as a reference to verify the effectiveness of the algorithm. This algorithm provides quantitative analysis means for the stability of characteristic impedance measurement instrument, and provides the reference basis for self-calibration circuit design of subsequent hardware.

Nitrogen Dioxide Wireless Sensor Based on Carbon Nanotubes and UWB RFID Technology

This letter presents a semi-passive wireless nitrogen dioxide gas sensor based on a time-coded ultra-wideband tag. The gas is sensed by means of oxygen-plasma-treated multiwall carbon nanotubes. The reader consists of a commercial ultra-wideband radar. The signal backscattered at the tag is modulated by a single-pole double-throw switch and contains information on the gas concentration. The tag is normally in sleep mode and includes a wake-up circuit. A self-calibration circuit is also included, enabling two additional measurements used for background subtraction and calibration to be obtained. The sensor is able to detect nitrogen dioxide concentrations from 10 ppm to 100 ppm, with a mean relative error of 0.34%.

A column-parallel clock skew self-calibration circuit for time-resolved CMOS image sensors

A column-parallel clock skew self-calibration circuit for time-resolved CMOS image sensors

A delay-locked loop with self-calibration circuit for reducing phase error

A delay-locked loop with self-calibration circuit for reducing phase error is presented. In this DLL, the current mismatch adjusting circuit is proposed in order to reduce the static phase error. To reduce the static phase error the circuit eliminates the mismatch of up/down currents in the charge pump (CP). The current mismatch adjusting circuit is implemented with phase expanded circuit to amplifier the static phase error. To solve the false locking problem, a new phase detector is proposed. The proposed circuit has been fabricated in a 0.18μm CMOS process. The measured static phase errors are without and with calibration circuit are 29ps and 3.89ps at 1.2GHz, respectively.

A 10-b 500 MS/s CMOS Folding A/D Converter with a Hybrid Calibration and a Novel Digital Error Correction Logic

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 ㎚ 1P6M CMOS has a DNL of ±0.8 LSB and an INL of ±1.0 LSB. The measured SNDR is 52.34-㏈ and SFDR is 62.04-㏈c when the input frequency is 78.15 ㎒ at 500 MS/s conversion rate. The SNDR of the ADC is 7-㏈ higher than the same circuit without the proposed calibration. The effective chip area is 1.55 ㎟, and the power dissipates 300 ㎽ including peripheral circuits, at a 1.2/1.5 V power supply.

Built-in Self-Calibration Circuit for Monotonic Digitally Controlled Oscillator Design in 65-nm CMOS Technology

This brief presents a built-in self-calibration (BISC) circuit to correct nonmonotonic responses in a digitally controlled oscillator (DCO) with a cascading structure. Generally speaking, a cascading DCO structure has the advantages of low power consumption and a small chip area. Nevertheless, when a subfrequency band is changed, an overlap region between subfrequency bands causes a large phase error and cycle-to-cycle jitter in an output clock. The proposed BISC circuit can reduce this problem; thus, it is very suitable for a low-power all-digital phase-locked loop design in system-on-a-chip applications. The proposed DCO, implemented with a standard performance 65-nm complementary metal-oxide-semiconductor process, can output frequency ranges from 47.8 to 538.7 MHz. The total power consumption of the DCO with a calibration circuit is 0.142 mW at 58.7 MHz and 0.205 mW at 481.6 MHz.

An Ultra Low Power and Variation Tolerant GEN2 RFID Tag Front-End with Novel Clock-Free Decoder

In this paper, an ultra low power analog front-end for EPCglobal Class 1 Generation 2 RFID tag is presented. The proposed RFID tag removes the need for high frequency clock and counters used in conventional tags, which are the most power hungry blocks. The proposed clock-free decoder employs an analog integrator with an adaptive current source that provides a uniform decoding margin regardless of the data rate and a link frequency extractor based on a relaxation oscillator that generates frequency used for backscattering. A dual supply voltage scheme is also employed to increase the power efficiency of the tag. In order to improve the tolerance of the proposed circuit to environmental variations, a self-calibration circuit is proposed. The proposed RFID analog front-end circuit is designed and simulated in 0.25µm CMOS, which shows that the power consumption is reduced by an order magnitude compared to the conventional RFID tags, without losing immunity to environmental variations.

A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application

A 2.5GHz 8-phase phase-locked loop (PLL) is proposed for 10-Gbps system on chip (SoC) transmission links application. The proposed PLL has several features which use new design techniques. The first one is a new variable delay cell (VDC) for the voltage control oscillator (VCO). Its advantages over the conventional delay cell are: wide-range output frequency and low noise sensitivity with low KVCO. The second feature is that, the PLL consists of a self-calibration circuit (SCC) which protects the PLL from variations in the process, voltage and temperature (PVT). The third feature is that, the proposed PLL has an 8-phase output frequency and also for avoiding the power/ground (P/G) effect and the substrate noise effect on the PLL, it also has a low jitter output frequency. The PLL is implemented in 0.13-µm CMOS technology. The PLL output jitter is 2.83ps (rms) less than 0.7% of the output period. The total power dissipation is 21mW at 2.5GHz output frequency, and the core area is 0.08mm2.

A Self-Calibrated On-Chip Phase-Noise Measurement Circuit With $-$75 dBc Single-Tone Sensitivity at 100 kHz Offset

An on-chip clock phase-noise measurement circuit is presented. Unlike previously reported monolithic measurement techniques that measure jitter in the time domain, the proposed module measures the phase-noise spectrum. The proposed circuit is fully integrated and does not require a spectrally clean reference clock or any external calibration. The module can be integrated as part of a built-in self-test (BIST) scheme for PLL clock synthesizers. The proposed circuit uses a low-noise voltage-controlled delay-line (VCDL) and mixer-based frequency discriminator to extract the phase-noise fluctuations at baseband. A self-calibration circuit is used to operate the measurement circuit at its highest sensitivity point. The proposed circuit is fabricated using a 0.25 mum digital CMOS process and operates up to a 2 GHz carrier frequency. It achieves a single-tone measurement sensitivity of -75 dBc and an equivalent phase-noise sensitivity of -124 dBc/Hz at 100 kHz offset frequency.

Self-calibration of input-match in RF front-end circuitry

The input match of RF front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input pad. The proposed technique ascertains the input match frequency of the circuit by using a built-in self-test (BiST) structure, determines the frequency interval by which it needs to be shifted to restore it to the desired value, and then feeds back a digital word to the low-noise amplifier (LNA), which adaptively corrects its input-match in real-time. The circuitry presented in the paper offers the advantages of low power overheads (the circuits can be powered off when not in use), robustness, no requirements of digital signal processing cores or processors, and fast calibration times (less than 30 /spl mu/s). This proof of concept is demonstrated by designing a cascode LNA and the complete self-calibration circuit in IBM 0.25-/spl mu/m CMOS RF process.

A digital self-calibration circuit for absolute optical rotary encoder microsystems

The parameters of the analog waveforms produced by the front-end electronics of absolute optical rotary encoders are affected by substantial differences and drifts. The threshold level required to convert the generated analog signal into a digital square wave in each read-out channel has to, therefore, be calibrated so as to keep the output duty-cycle close to its ideal value of 50%. This paper presents a digital self-calibration circuit specifically designed for this purpose. The circuit performs dynamic calculation of the threshold level, continuously compensating for encoder nonidealities while the system is normally operating. This avoids the need for manual calibration, provides thermal stabilization, and prevents performance degradation. The proposed digital calibration system was integrated in conventional CMOS technology and was then successfully evaluated.

A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching

This paper describes a 1.8-GHz self-calibrated phase-locked loop (PLL) implemented in 0.35-/spl mu/m CMOS technology. The PLL operates as an edge-combining type fractional-N frequency synthesizer using multiphase clock signals from a ring-type voltage-controlled oscillator (VCO). A self-calibration circuit in the PLL continuously adjusts delay mismatches among delay cells in the ring oscillator, eliminating the fractional spur commonly found in an edge-combing fractional divider due to the delay mismatches. With the calibration loop, the fractional spurs caused by the delay mismatches are reduced to -55 dBc, and the corresponding maximum phase offsets between the multiphase signals is less than 0.20. The frequency synthesizer PLL operates from 1.7 to 1.9 GHz and the closed-loop phase noise is -105 dBc/Hz at 100-kHz offset from the carrier. The overall circuit consumes 20 mA from a 3.0-V power supply.

The Design and Performance of Multirange Current Transformer Standards for Audio Frequencies

The design, construction, and performance of two nearly identical, multirange current transformers for operation 400 Hz to 10 kHz and with errors of only a few ppm are discussed. A general discussion of the parameters that influence the performance of single-stage transformers and their consideration in effecting minimum errors throughout a wide frequency band is included. Construction of the two standards having consecutive ratios 1 to 1 to 6 to 1 and operating at a rated secondary current of 5 amperes is described. Circuit diagrams are used to describe 1) the self-calibration circuit for measuring the errors of the 1-to-1 ratios and 2) the (N+1) circuit together with an auxiliary circuit for measuring the errors of ratios> 1. Balance equations are derived in the Appendix. Measured values are presented; included are the results up to 16 kHz obtained at the National Research Council, Canada, during an international comparison and described in a companion paper [6]. The effects of polarization at low frequencies are emphasized by utilizing the 400 Hz data together with information obtained in supplementary experiments; also the role of winding and interwinding capacitances and the necessity for a more explicit definition of current ratio at the higher frequencies is highlighted.