Self-aligned Transistors Research Articles

Self-Aligned Fabrication of Graphene RF Transistors with T-Shaped Gate

Exceptional electronic properties of graphene make it a promising candidate as a material for next generation electronics; however, self-aligned fabrication of graphene transistors has not been fully explored. In this paper, we present a scalable method for fabrication of self-aligned graphene transistors by defining a T-shaped gate on top of graphene, followed by self-aligned source and drain formation by depositing Pd with the T-gate as a shadow mask. This transistor design provides significant advantages such as elimination of misalignment, reduction of access resistance by minimizing ungated graphene, and reduced gate charging resistance. To achieve high-yield scalable fabrication, we have combined the use of large-area graphene synthesis by chemical vapor deposition, wafer-scale transfer, and e-beam lithography to deposit T-shaped top gates. The fabricated transistors with channel lengths in the range of 110-170 nm exhibited excellent performance with peak current density of 1.3 mA/μm and peak transconductance of 0.5 mS/μm, which is one of the highest transconductance values reported. In addition, the T-gate design enabled us to achieve graphene transistors with extrinsic current-gain cutoff frequency of 23 GHz and maximum oscillation frequency of 10 GHz. These results represent important steps toward self-aligned design of graphene transistors for various applications.

Self-aligned lateral dual-gate suspended-body single-walled carbon nanotube field-effect transistors

Self-aligned lateral dual-gate suspended-body single-walled carbon nanotube (CNT) field-effect transistors (CNFETs) have been demonstrated. A nano-precision assembly method using resist-assisted ac-dielectrophoresis is applied. Superior I-V characteristics controlled by two independent lateral gates spaced sub-100 nm away from the CNT body are experimentally observed and studied. The dual-gate operation mode effectively boosts the device performance: 34% smaller subthreshold slope, three times larger on-current, and four times higher transconductance. The proposed dual-gate suspended-body CNFETs hold promise for bottom-up fabrication of advanced complementary metal-oxide-semiconductor circuits and nano-electro-mechanical systems devices, such as tunable/switchable resonators for sensing and radio-frequency applications.

Micro-imprinted prism substrate for self-aligned short channel organic transistors on a flexible substrate

Using a simple micro-imprinting process on flexible substrates, we demonstrate fabrication of self-aligned short channel organic thin film transistors (OTFTs) with significantly reduced parasitic capacitance. The surface topology resulting from the imprinted prism-like structures enables accurate alignment of both the gate and source-drain electrodes. The parasitic overlap capacitance was reduced by 80%, which enables twice higher transition frequency (fT = 10.1 kHz) compared with conventional top-contact OTFT devices. The prism-OTFTs were applied to both p-type (pentacene) and n-type (C60) organic semiconductors to implement low voltage complementary inverters.

Self-Aligned Carbon Nanotube Thin-Film Transistors on Flexible Substrates With Novel Source–Drain Contact and Multilayer Metal Interconnection

This paper presents the development and characterization of self-aligned carbon nanotube thin-film transistors (CNT-TFT) on flexible substrates. The channel consisting of dense, aligned, 99% pure semiconducting single-walled CNT is deposited using the dip-coat technique on a sacrificial substrate and then transferred on the device substrate. The source, drain, and gate structures are formed by the ink-jet printing technique. A novel source-drain contact formation using wet droplet of silver ink prior to the CNT thin-film application has been developed to enhance source-drain contact with the CNT channel. Bending test data on CNT-TFT test structures show minimal change (less than 10%) in their performance. Moreover, a special multilayer metal interconnection technology is demonstrated for flexible electronics applications. Bending test data on via test structure show change in resistance by less than 5%.

Dielectric-tuned Diamondlike Carbon Materials for High-performance Self-aligned Graphene-channel Field Effect Transistors

ABSTRACTThe ‘DLC-GFET’, a graphene field effect transistor with a diamondlike carbon (DLC) top-gate dielectric film, is presented. The DLC film was formed ‘directly’ onto the graphene channel without forming passivation interlayers using our original photoemission-assisted plasma-enhanced chemical vapor deposition (PA-CVD), where the plasma was precisely controlled by photoemission from the sample with quite low electric power to minimize plasma damage to the channel. The DLC-GFET exhibits clear ambipolar characteristics with a slightly positive shift of the neutral points (Dirac voltages). Relatively high transconductances were obtained as 14.6 (8.8) mS/mm in the n (p) channel modes, respectively, with a thick gate dielectric of 48 nm and a long gate length of 5 μm, promising vertical scaling-down to improve the high-frequency performance. The positive shift of the Dirac voltage is due to unintentional hole doping from oxygen species in the DLC film into the graphene channel, promising a minute modulation doped structure with oxygen to overcome high resistance in the access region. Hence, a DLC film deposited by PA-CVD is a candidate for the gate dielectric on graphene.

Self-Aligned Top-Gate Oxide Thin-Film Transistor Formed by Aluminum Reaction Method

We developed a novel highly reliable self-aligned top-gate oxide semiconductor thin-film transistor (TFT) formed by the aluminum (Al) reaction method. In this method, Al diffusion into the oxide semiconductor was observed. The low sheet resistivity of the source/drain regions was attributed to Al working as a donor in the oxide semiconductor. The TFTs with 4 µm channel length exhibited a field-effect mobility of 9.8 cm2 V-1 s-1, a threshold voltage of -1.5 V, and a subthreshold swing of 0.22 V/decade. Highly reliable TFTs were obtained after 300 °C annealing without increasing the sheet resistivity of source/drain regions.

Self-Aligned Top-Gate Oxide Thin-Film Transistor Formed by Aluminum Reaction Method

Self-Aligned Top-Gate Oxide Thin-Film Transistor Formed by Aluminum Reaction Method

Self-Aligned Coupled Nanowire Transistor

The integration of multiple functionalities into individual nanoelectronic components is increasingly explored as a means to step up computational power, or for advanced signal processing. Here, we report the fabrication of a coupled nanowire transistor, a device where two superimposed high-performance nanowire field-effect transistors capable of mutual interaction form a thyristor-like circuit. The structure embeds an internal level of signal processing, showing promise for applications in analogue computation. The device is naturally derived from a single NW via a self-aligned fabrication process.

Performance trade-offs in polysilicon source-gated transistors

Self-aligned Schottky-source source-gated transistors (SGTs) have been made in polysilicon. The structures enable a direct comparison to be made between a SGT and a standard thin-film field-effect transistor (FET) on the same device. SGTs having excellent characteristics have been fabricated, with intrinsic gains approaching 10,000. The effects of bulk doping in the polysilicon and of the source barrier modification implant are considered in the context of the electrical output characteristics. It is shown that the choice of source length is a tradeoff between device speed and variations in current output due to variability during fabrication.

Scalable fabrication of self-aligned graphene transistors and circuits on glass.

Graphene transistors are of considerable interest for radio frequency (rf) applications. High-frequency graphene transistors with the intrinsic cutoff frequency up to 300 GHz have been demonstrated. However, the graphene transistors reported to date only exhibit a limited extrinsic cutoff frequency up to about 10 GHz, and functional graphene circuits demonstrated so far can merely operate in the tens of megahertz regime, far from the potential the graphene transistors could offer. Here we report a scalable approach to fabricate self-aligned graphene transistors with the extrinsic cutoff frequency exceeding 50 GHz and graphene circuits that can operate in the 1-10 GHz regime. The devices are fabricated on a glass substrate through a self-aligned process by using chemical vapor deposition (CVD) grown graphene and a dielectrophoretic assembled nanowire gate array. The self-aligned process allows the achievement of unprecedented performance in CVD graphene transistors with a highest transconductance of 0.36 mS/μm. The use of an insulating substrate minimizes the parasitic capacitance and has therefore enabled graphene transistors with a record-high extrinsic cutoff frequency (> 50 GHz) achieved to date. The excellent extrinsic cutoff frequency readily allows configuring the graphene transistors into frequency doubling or mixing circuits functioning in the 1-10 GHz regime, a significant advancement over previous reports (∼20 MHz). The studies open a pathway to scalable fabrication of high-speed graphene transistors and functional circuits and represent a significant step forward to graphene based radio frequency devices.

Self-Aligned U-Gate Carbon Nanotube Field-Effect Transistor with Extremely Small Parasitic Capacitance and Drain-Induced Barrier Lowering

A novel self-aligned U-gate structure for carbon nanotube (CNT) field-effect transistors (FETs) is introduced and shown to yield excellent dc properties and high reproducibility that are comparable with that of the best CNT FETs based on the previously developed self-aligned device structures. In particular the subthreshold swing of the U-gate FET is 75 mV/dec and the drain-induced barrier lowering is effectively zero, indicating that the electrostatic potential of the whole CNT channel is most efficiently controlled by the U-gate and that the CNT device is a well-behaved FET. Moreover the high-frequency response of the U-gate FET is investigated, and the parasitic capacitance of the device is measured and shown to be one magnitude smaller than that of the previously developed self-aligned device structures. Direct frequency domain measurements show that the U-gate CNT FETs can operate up to 800 MHz, which is also higher than previously reported values. The large improvement in the device high-frequency behavior is largely due to the replacement of the high-κ dielectric material between the source/drain and the gate by a vacant space with κ ≈ 1, and the significant reduction in the device parasitic capacitance renders the U-gate CNT FETs promising for rf applications.

All inkjet-printed, fully self-aligned transistors for low-cost circuit applications

Layer-to-layer registration is a significant problem in printed electronics since parasitic overlap capacitances resulting from the poor registration of conventional printers substantially degrade device operating speeds. To overcome this, a novel inkjet printing process was utilized to demonstrate an all inkjet-printed and fully self-aligned transistor, as well as fully self-aligned inverters for the first time. Self-alignment of transistor source/drain electrodes to gates was achieved by a printed wetting-based roll-off process, resulting in an improved overlap capacitance as small as 0.14–0.23 pF mm −1. Circuit building blocks including transistor arrays and inverters were demonstrated using a novel self-split source/drain and a self-aligned interconnect printing technique. Due to the substantial reduction in overlap capacitance, demonstrated inverters showed a propagation delay as low as 0.488 ms at a fan-out of 1, despite using materials with mobility of 0.01 cm 2 V −1 s −1, thus showing a performance that is suitable for use in a range of low-cost electronics applications, realized using a simple, scalable process.

Intrinsic Gain in Self-Aligned Polysilicon Source-Gated Transistors

Thin-film self-aligned source-gated transistors (SGTs) have been made in polysilicon. The very high output impedance of this type of transistor makes it suited to analog circuits. Intrinsic voltage gains of greater than 1000 have been measured at particular drain voltages. The drain voltage dependence of the gain is explained based on the device physics of the SGT and the fact that a pinchoff occurs at both the source and the drain. The results obtained from these devices, which are far from optimal, suggest that, with a proper design, the SGT is well suited to a wide range of analog applications.

Analysis of Self-Heating-Related Instability in Self-Aligned p-Channel Polycrystalline-Silicon Thin-Film Transistors

Self-heating-related instabilities have been studied in p-channel polycrystalline-silicon thin-film transistors. The spatial distribution of the interface-state and fixed-oxide-charge densities generated during self-heating experiments has been analyzed and quantitatively determined by using negative-bias temperature stress experiments and 2-D numerical simulations. In addition, the observed asymmetry in the output characteristics with respect to source/drain contact reversal is also perfectly reproduced, confirming the validity of the proposed model.

Fabrication of self-aligned TFTs with a ultra-low temperature polycrystalline silicon process on metal foils

We have fabricated self-aligned thin-film transistors (TFTs) using a ultra-low temperature ( T < 200 °C) polycrystalline silicon process on stainless steel foil substrates. The overall processing scheme and technical details were discussed from the viewpoint of electrical and mechanical stabilities. Large grain poly-Si films were obtained with sequential lateral solidification (SLS) method. Plasma enhanced atomic layer deposition (PEALD) method was used to form Al 2O 3 gate dielectric films. The TFT performances were enhanced by plasma oxidation of the polycrystalline Si surface prior to Al 2O 3 gate dielectric film deposition. The fabricated TFT showed a field effect mobility of 95 cm 2/Vs, a threshold voltage of −3 V and a sub-threshold swing of 0.45 V/dec.

Carrier Mobility Variations in Self-Aligned Germanium MOS Transistors

Tungsten gate germanium MOS transistors have been manufactured on bulk germanium platforms. Hole mobility in the range 450 cm2/Vs has been achieved on bulk germanium, but mobility is reduced during the densification of thinner dielectrics at 600C. This may be due to the formation of volatile GeO at the interface during densification. Low temperature measurements of the thinner dielectric device indicate that lattice scattering is dominant at room temperature for the device where the densification was omitted and the excellent subthreshold slopes at low temperatures also indicate devices of good quality.

Dual-Gate Single-Electron Transistor with Silicon Nano Wire Channel and Surrounding Side Gates

In this paper, we propose a novel self-aligned dual-gate single-electron transistor having nano wire channel and surrounding side gates. By restricting the control gate effect to the top surface of the channel and intensifying the depletion effect through the surrounding side gates, the parasitic metal–oxide–silicon field-effect transistor (MOSFET) current and the quantum dot size are expected to be decreased. These advantages of the proposed structure are investigated through three-dimensional (3D) device simulation. In addition, the devices are fabricated by utilizing the silicon process and their electrical characteristics are analyzed at both room temperature and low temperature. Also, diverse device parameters are extracted from the measurement results, and they are systematically compared.

Carrier Mobility Variations in Self-Aligned Germanium MOS Transistors

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Fabrication and Characteristics of Self-Aligned Dual-Gate Single-Electron Transistors

Single-electron transistors that have electrical tunneling barriers are fabricated, and Coulomb oscillation peaks and negative differential transconductance are observed at room temperature (300 K). Operation characteristics and multioscillation peaks are further investigated at low temperature (80 K). The period of Coulomb oscillation is 2.3 V due to an ultrasmall control gate capacitance, and oscillation peaks are shifted through the side gate bias, which is explained by the derived stability plot for dual-gate structures. Even with the side gates electrically floating, the device still operates as a single-electron transistor since the p-n junction barrier plays a role of tunneling barrier. In addition, by changing the bias condition, double dots are formed along the channel and peak splitting is observed.

Source/Drain Formation of Self-Aligned Top-Gate Amorphous GaInZnO Thin-Film Transistors by $\hbox{NH}_{3}$ Plasma Treatment

The source/drain region of amorphous GaInZnO thin-film transistor with self-aligned top-gate structure was defined by simple NH3 plasma treatment instead of complicated processes, such as ion implantation and activation. When the source/drain region of active layer was exposed to NH3 gas plasma, the series resistance of the transistor decreased considerably. It exhibited electrical properties, such as a field-effect mobility of 6 cm2/V middots, a threshold voltage of 0.21 V, and a subthreshold swing of 0.23 V/dec.