Self-aligned Silicide Process Research Articles

Process optimization of titanium self-aligned silicide formation through evaluation of sheet resistance by design of experiment methodology

A low-resistivity titanium silicide (TiSi2) is crucial as a gate and source/drain material in microelectronic device fabrication, offering notable properties to enhance device performance. This study aims to experimentally determine the optimum process parameters, including arsenic doping dosage, titanium thickness, and two-step rapid thermal process (RTP) temperature, for the sheet resistance of titanium self-aligned silicide process using a design of experiment methodology. The results demonstrate that both the thickness of the titanium and the temperature of the RTP play crucial roles in determining the sheet resistance of TiSi2. Statistical analysis reveals that increasing the titanium thickness or the temperature of the first-step RTP (RTP-1) could reduce the sheet resistance. Additionally, an optimal second-step RTP (RTP-2) temperature is critical to yield low-resistivity TiSi2 by completely converting C49- to C54-phase. The optimum process conditions for obtaining low sheet resistance are a titanium thickness of 32–35 nm, RTP-1 temperature of 720–750 °C for 75 s, and RTP-2 temperature of 860 °C for 20 s. Moreover, surface amorphization of the polysilicon by arsenic ion implantation before the deposition of Ti/TiN films also plays a crucial role in the formation of C54-TiSi2. The lowest sheet resistance achieved was 3.91 Ω/sq with an arsenic dosage of 1 × 1014 cm−2. The optimum condition was adopted for forming a submicron polysilicon gate, providing a promising approach for designing the process parameters for titanium self-aligned silicide formation to achieve low resistance in nanoscale electronic devices.

Enhanced thermoelectric properties of cobalt silicide-silicon heterostructured nanowires

Silicon nanowires (SiNWs) have attracted attention as promising high efficiency thermoelectric materials by significantly improving the thermoelectric efficiency of silicon. Here, we have fabricated cobalt silicide/silicon heterostructure on both ends of nanowires using self-aligned silicide (salicide) process. By forming cobalt silicide (CoSi2) layer on SiNWs, the thermal conductivity of SiNWs with diameters of 200, 350, and 500 nm decrease to 25.1, 31.3, and 38.1 W·m−1·K−1, respectively, which is about 8% reduction on average. Since the phonon nanoinclusion scattering is influenced by the density of the nanoinclusions, the thermal conductivity tends to decrease as the volume fraction of CoSi2 in SiNWs increases. The Seebeck coefficient of the heterostructured nanowires increases to 255 μV/K, which is mainly attributed to the low-energy charge carrier filtering effect due to the Schottky barrier at the CoSi2/Si interfaces. The measurements show that the figure-of-merit ZT of the heterostructured nanowires is improved by 10% on average compared with the conventional SiNWs. Consequently, the CoSi2/Si heterostructured nanowires enhance the thermoelectric properties of SiNWs effectively by suppressing phonon transport and improving electron flow.

Investigation of a Self-Aligned Cobalt Silicide Process for Ohmic Contacts to Silicon Carbide

Previous studies showed that cobalt silicide can form ohmic contacts to p-type 6H-SiC by directly reacting cobalt with 6H-SiC. Similar results can be achieved on 4H-SiC, given the similarities between the different silicon carbide polytypes. However, previous studies using multilayer deposition of silicon/cobalt on 4H-SiC gave ohmic contacts to n-type. In this study, we investigated the cobalt silicide/4H-SiC system to answer two research questions. Can cobalt contacts be self-aligned to contact holes to 4H-SiC? Are the self-aligned contacts ohmic to n-type, p-type, both or neither? Using x-ray diffraction, it was found that a mixture of silicides (hbox {Co}_2hbox {Si} and CoSi) was reliably formed at 800^circ C using rapid thermal processing. The cobalt silicide mixture becomes ohmic to epitaxially grown n-type (1times 10^{19} hbox {cm}^{-3}) if annealed at 1000^circ C, while it shows rectifying properties to epitaxially grown p-type (1times 10^{19} hbox {cm}^{-3}) for all tested anneal temperatures in the range 800–1000^circ C. The specific contact resistivity (rho _mathrm{C}) to n-type was 4.3 times 10^{-4} mathrm {Omega },hbox {cm}^{2}. This work opens the possibility to investigate other self-aligned contacts to silicon carbide.

Selection of the first Ni silicide phase by controlling the Pt incorporation in the intermixed layer

During the deposition of a Ni film on a Si substrate, an intermixed layer usually forms at the Ni/Si interface. In this work, the influence of Pt incorporation in this intermixed layer on the phase formation sequence and especially on the first phase formation is studied by in situ-XRD measurements and atom probe tomography (APT). Four different samples were elaborated where the intermixed layer was modified by deposition of a 3 nm of Ni or Ni(10 at% Pt) on the Si substrate prior to the deposition of Ni(10 at%Pt) or Ni film respectively. These results show that the formation of the first phase changes between δ-Ni2Si and θ-Ni2Si depending on the Pt concentration integrated in the intermixed layer. Using this selection method to control the formation of the first phase, can impact the self-aligned silicide process used by the industry.

Ni(Pt)-silicide contacts on CMOS devices: Impact of substrate nature and Pt concentration on the phase formation

Ni silicides used as contacts in source/drain and gate of advanced CMOS devices were analyzed by atom probe tomography (APT) at atomic scale. These measurements were performed on 45nm nMOS after standard self-aligned silicide (salicide) process using Ni(5at.% Pt) alloy. After the first annealing (RTA1), δ-Ni2Si was the only phase formed on gate and source/drain while, after the second annealing (RTA2), two different Ni silicides have been formed: NiSi on the gate and δ-Ni2Si on the source and drain. This difference between source/drain and gate regions in nMOS devices has been related to the Si substrate nature (poly or mono-crystalline) and to the size of the contact. In fact, NiSi seems to have difficulties to nucleate in the narrow source/drain contact on mono-crystalline Si. The results have been compared to analysis performed on 28nm nMOS where the Pt concentration is higher (10at.% Pt). In this case, θ-Ni2Si is the first phase to form after RTA1 and NiSi is then formed at the same time on source (or drain) and gate after RTA2. The absence of the formation of NiSi from δ-Ni2Si/Si(100) interface compared to θ-Ni2Si/Si(100) interface could be related to the difference of the interface energies. The redistributions of As and Pt in different silicides and interfaces were measured and discussed. In particular, it has been evidenced that Pt redistributions obtained on both 45 and 28nm MOS transistors correspond to respective Pt distributions measured on blanket wafers.

Fluid-kinetics enhanced selective etching process of NiPt film by piranha chemistry in silicide formation for complementary metal oxide semiconductor fabrication

NiPtSi is a prime candidate for the complementary metal-oxide-semiconductors CMOS self-aligned silicidation process beyond the 22nm node. The formation of NiPt silicide in smaller geometries demands more Platinum (Pt) additive to control the silicide quality and a more capable NiPt selective etching process to remove surface residual metals for complementing the formation of silicide. Both higher Pt selective etch rate and lower surface material loss are desired in NiPt selective etching process.High temperature (>150°C) sulfuric acid base piranha chemistry in fresh dispensing on wafer can etch Pt with less damage to the exposed wafer surface. By using (1) a larger mass-to-charge density Pt redox reaction zone in the electrochemistry spectrum of the Pt redox behavior, (2) stronger chemical fluid kinetics and (3) intensified voltammetric cycles, the Pt selective removal rate can be boosted. Two types of wet chemical processors are used to examine the fluid-chemical kinetics effect on the Pt selective etching rate. It is shown that higher chemical flow rates and stronger fluid-kinetics can enhance the Pt transport behavior. The collateral wafer surface material loss rate also increases by higher chemical flow rates, but the amount of total material loss actually reduces due to a greater reduction in the required process time. The fluid-kinetics enhanced selective etching process can cover a wider range of NiPt film conditions (5% Pt, up to 200Å, 10% Pt up to 180Å).

Label-Free and Real-Time Immunodetection of the Avian Influenza A Hemagglutinin Peptide Using a Silicon Field-Effect Transistor Fabricated by a Nickel Self-Aligned Silicide Process

Electrical immunodetection of the avian influenza A (H5N1) hemagglutinin (HA) peptide, the IN peptide, with anti-HA antibody was demonstrated using a field-effect transistor (FET) with an n-type silicon (Si) channel and a nickel (Ni) self-aligned silicide source/drain that was fabricated by a conventional top-down process. The specific binding of the IN peptide with anti-HA antibody in phosphate buffered saline (PBS) occurs on the patterned SiO2 surface through covalent linkage. Positive ions in the buffer create majority carriers in the n-type Si channel, leading to a rapid increase in current across that channel. However, specific binding of the negatively charged antigens on the SiO2 surface overlaying the Si channel results in the reduction of electrons induced in the Si channel by the positive ions, causing a significant decrease in the channel current. The settling time for obtaining a stable signal change, driven by the negatively charged antigens bound to antibody, extrapolates to approximately 32s. [doi:10.2320/matertrans.M2012068]

Theoretical investigation of silicide Schottky barrier detector integrated in horizontal metal-insulator-silicon-insulator-metal nanoplasmonic slot waveguide

An ultracompact integrated silicide Schottky barrier detector (SBD) is designed and theoretically investigated to electrically detect the surface plasmon polariton (SPP) propagating along horizontal metal-insulator-silicon-insulator-metal nanoplasmonic slot waveguides at the telecommunication wavelength of 1550 nm. An ultrathin silicide layer inserted between the silicon core and the insulator, which can be fabricated precisely using the well-developed self-aligned silicide process, absorbs the SPP power effectively if a suitable silicide is chosen. Moreover, the Schottky barrier height in the silicide-silicon-silicide configuration can be tuned substantially by the external voltage through the Schottky effect owing to the very narrow silicon core. For a TaSi(2) detector with optimized dimensions, numerical simulation predicts responsivity of ~0.07 A/W, speed of ~60 GHz, dark current of ~66 nA at room temperature, and minimum detectable power of ~-29 dBm. The design also suggests that the device's size can be reduced and the overall performances will be further improved if a silicide with smaller permittivity is used.

Optical metrology of Ni and NiSi thin films used in the self-aligned silicidation process

The thickness-dependent optical properties of nickel metal and nickel monosilicide (NiSi) thin films, used for self-aligned silicidation process, were characterized using spectroscopic ellipsometry. The thickness-dependent complex dielectric function of nickel metal films is shown to be correlated with the change in Drude free electron relaxation time. The change in relaxation time can be traced to the change in grain boundary (GB) reflection coefficient and grain size. A resistivity based model was used as the complementary method to the thickness-dependent optical model to trace the change in GB reflection coefficient and grain size. After silicidation, the complex dielectric function of NiSi films exhibit non-Drude behavior due to superimposition of interband absorptions arising at lower frequencies. The Optical models of the complete film stack were refined using x-ray photoelectron spectroscopy, Rutherford backscattered spectroscopy, and x-ray reflectivity (XRR).

Anomalous Nickel Silicide Encroachment in n-Channel Metal–Oxide–Semiconductor Field-Effect Transitors on Si(110) Substrates and Its Suppression by Si+ Ion-Implantation Technique

A novel low-leakage-current nickel self-aligned-silicide (SALICIDE) process in n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) on Si(110) substrates is reported. Anomalous nickel silicide encroachment in the <110> direction in nMOSFETs on Si(110) substrates is found for the first time. This encroachment causes anomalous off-state leakage current (Ioff) in nMOSFETs on Si(110) substrates. In particular, in the case of the <110> channel on Si(110) substrates, Ni atoms easily diffuse in the <110> direction, and nickel silicide preferentially grows in the <110> direction. As a result, anomalous leakage current between the drain and the source occurs, and the leakage current seriously degrades transistor performance. In order to overcome these problems, we propose a method of suppressing anomalous Ioff on Si(110) substrates by Si+ ion-implantation technique prior to the nickel SALICIDE process. This method is effective for suppressing the encroachment of nickel silicide and realizing low-leakage complementary metal–oxide–semiconductor (CMOS) devices on Si(110) substrates.

Nickel Selective Etching Studies for Self-Aligned Silicide Process in Ge and SiGe-Based Devices

The limitations of the H2SO4/H2O2/H2O mixture (diluted SPM chemistry) as a reagent for the nickel selective etching step of the salicidation process when silicon is replaced by silicon- germanium alloys or pure germanium is investigated. When the Ge content in SiGe is higher than 30%, SPM is not suitable anymore due to the high etch rate of the germanosilicide layer. This high etch rate is related to the poor stability of the Ge oxide in aqueous solutions. For Ge contents above 30%, H2SO4 96% is proposed as a selective etching reagent instead of SPM. With this chemistry, a very high Ni/NiSiGe selectivity and a good Ni/NiGe selectivity are obtained, since only 10% of the germanide layer is attacked while the Ni layer is completely removed.

A novel self-aligned process for platinum silicide nanowires

Directly accessible, ultralong, uniform platinum silicide nanowires in PtSi and Pt 2Si are mass-fabricated by combining a sidewall transfer lithography (STL) technology and a self-aligned silicide process. The STL technology is based on standard Si technology. The self-aligned platinum silicide (PtSi x ) process consists of two sequential steps in a single run: a silicidation step in N 2 to ensure a controllable silicide formation followed by an oxidation step in O 2 to form a reliable protective SiO x layer on top of the grown PtSi x . The achieved nanowires are characterised by a low resistivity: 26 ± 3 and 34 ± 2 μΩ cm for the Pt 2Si- and PtSi-dominated nanowires.

Nickel Selective Etching Studies for Self-Aligned Silicide Process in Ge-Based Devices

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Robust, scalable self-aligned platinum silicide process

A robust, scalable PtSix process is developed. The process consists of two consecutive annealing steps in a single run; the first is silicidation of Pt films on Si substrates carried out in N-2, wh ...

Formation of Nickel Self-Aligned Silicide by Using Cyclic Deposition Method

We have developed a novel nickel self-aligned silicide (salicide) process for future scaled metal-oxide-semiconductor field-effect transistors (MOS-FETs). Ni/Si multi-layered structures were fabricated by the cyclic deposition of Ni and Si. Nickel monosilicide (NiSi) films with a low resistivity, a uniform thickness, and a good morphology were obtained on Si(100) substrates after annealing at 400–600°C. Nickel silicide formed on SiO2 can be removed by wet etching if the total atomic number ratio of Ni to Si in the deposited layers is larger than unity. This shows that the nickel salicide process is possible by our method. We have fabricated MOS-FET structures with NiSi and confirmed that the consumption of Si in the substrate is much lower in our method than in the conventional method.

Schottky-Barrier Source/Drain MOSFETs on Ultrathin SOI Body With a Tungsten Metallic Midgap Gate

This letter presents a simple low-temperature process to fabricate Schottky-barrier (SB) MOSFETs that integrates a midgap metallic gate (tungsten). The device architecture is based on a thin (10 nm) and lowly doped silicon-on-insulator film that provides a threshold voltage of -0.3 V independent on the depletion charge and therefore not sensitive to variations in film thickness and doping. A gate encapsulation technique using an SiO/sub 2/-like hydrogen silsesquioxane capping layer features 15-nm-wide spacers and ensures the compatibility with the PtSi self-aligned silicide process. Long-channel devices present an ideal subthreshold swing of 60 mV/dec, over six decades of I/sub on//I/sub off/ without any sign of sublinear upward bending of the I/sub DS/--V/sub DS/ curves at low drain voltage.

NiSi integration in a non-selective base SiGeC HBT process

A self-aligned nickel silicide (salicide) process is integrated into a non-selective base SiGeC HBT process. The device features a unique, fully silicided base region that grows laterally under the emitter pedestal. This Ni(SiGe) formed in this base region was found to have a resistivity of 23–24 μΩ cm. A difference in the silicide thickness between the boron-doped SiGeC extrinsic base region and the in situ phosphorous-doped emitter region is observed and further analyzed and confirmed with a blanket wafer silicide study. The silicided device exhibited a current gain of 64 and HF device performance of 39 and 32 GHz for f t and f MAX, respectively.

In situ analysis of epitaxial cobalt silicide reaction on silicon (0 0 1)

Formation process of CoSi2 on Si(0 0 1) was investigated with in situ reflection high-energy electron diffraction analysis for developing a self-aligned silicide (salicide) process of advanced silicon transistors. A thin Co layer deposited onto a wet chemically oxidized Si(0 0 1) surface silicided at 550°C to form epitaxial CoSi2(0 0 1) without developing polycrystalline subsilicide phase. The oxide remained on the surface up to 750°C and kept the surface flat until its evaporation. It was thus revealed that chemically formed thin oxide on Si(0 0 1) surface is an effective reaction control layer that acts as a reaction barrier to Co/Si subsilicide formation and as a kinematical barrier to surface migration of growing species. These conditions are necessary for fabricating flat and thin epitaxial CoSi2 layers.

Applications of Ni-based silicides to 45 nm CMOS and Beyond

ABSTRACTThis paper presents an overview of Ni-alloy (Ni, Ni-Pt and Ni-Ta) silicide development for the 45 nm node and beyond, including applications to self-aligned silicide (SALICIDE) processes, reaction with SiGe and strained Si on SiGe, and applications to fully silicided (FUSI) gates. Key SALICIDE issues addressed include the use of spike or low temperature rapid thermal processes (RTP) to control silicidation and junction leakage on small features, factors affecting the formation of epitaxial pyramidal NiSi2 grains, and NiSi thermal stability and agglomeration kinetics. Alloying with Pt or Ta is shown to improve thermal stability of NiSi films, although with quite different behaviors. While Pt is incorporated predominantly in solution in NiSi, Ta segregates to the surface of the films. Ni-Pt alloy silicides were also found to achieve low sheet resistance on narrow gates, low contact resistivity and low junction leakage, making them attractive for CMOS applications. For the Ni/SiGe reaction, a narrower RTP process window for low sheet resistance and a lower activation energy for agglomeration were observed when compared to the Ni/Si reaction. The lower thermal stability was correlated to Ge segregation from the Ni(SiGe) films. The Ni/doped poly-Si reaction was studied for FUSI gate applications, showing a retardation of the silicidation kinetics for high B doses and a large pile- up of dopants (for As, B or P) at the NiSi/SiO2 interface due to dopant snowplow during silicidation. The work function (WF) of NiSi was observed to shift with the addition of dopants, effect attributed to modifications of the interface dipole by the pile-up of dopants. No significant degradation was observed when comparing gate oxide breakdown statistics for Ni FUSI to conventional poly-Si gates. The process window for a FUSI gate-last process (performed after S/D Ni silicidation) was evaluated showing a potential integration problem due to possible degradation of the S/D silicide during the FUSI gate reaction.

Nickel-based contact metallization for SiGe MOSFETs: progress and challenges

The Ni-based self-aligned silicide process has attracted a rapidly growing interest for contact metallization in Si technology, as the device dimensions are scaled down into the sub-100 nm regime. Incorporation of Ge in the electrodes of a MOSFET, i.e. gate and source/drain, in order to further enhance device performance, has made the study of Ni–Si 1− x Ge x interactions a scientifically and technologically important issue. Among the different germanosilicides of Ni, NiSi 1− u Ge u (i.e. mono-germanosilicide, with u possibly different from x in the Si 1− x Ge x ) is the most desirable phase due to its low specific resistivity of 12–25 μΩcm. The focus of the present work is placed on issues concerning the phase and morphology stability of NiSi 1− u Ge u on single-crystal and polycrystalline Si 1− x Ge x substrates. The related experimental data from our recent work are analysed with reference to two classics on the formation of silicides by d’Heurle [J. Mater. Res. 3 (1988) 167] and by d’Heurle and Gas [J. Mater. Res. 1 (1986) 205]. Influences of C and Pt on the stability of NiSi 1− u Ge u are also covered. The electrical properties of the NiSi 1− u Ge u –Si 1− x Ge x contact are discussed referring to our latest experimental results.