Self-aligned Shallow Trench Isolation Research Articles

Characteristics of Sub-50 nm NAND Flash Devices with Various Self-Aligned Shallow Trench Isolation Depths

The program efficiency and endurance characteristics of sub-50 nm NAND flash devices with various self-aligned shallow trench isolation (SA-STI) depths are investigated. Although a large SA-STI depth improves the neighboring floating gate coupling issue and gate coupling ratio, a low program efficiency is also introduced. In addition, lower endurance characteristics are observed in the device with a large SA-STI depth than in the device with a small SA-STI depth. The mechanisms underlying such unfavorable results are discussed on the basis of experimental data and technology computer-aided design simulations.

Novel Negative <formula formulatype="inline"><tex Notation="TeX">$Vt$</tex></formula> Shift Phenomenon of Program–Inhibit Cell in <formula formulatype="inline"><tex Notation="TeX">$\hbox{2}X{-}\hbox{3}X\hbox{-}\hbox{nm}$</tex> </formula> Self-Aligned STI nand Flash Memory

A novel program-inhibit phenomenon of “negative” cell <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vt</i> shift has been investigated for the first time in 2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</i> - 3 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</i> -nm self-aligned shallow trench isolation nand Flash memory cells. The negative <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vt</i> shift is caused in an inhibit cell when along-word-line adjacent cell is programming. The magnitude of the negative shift becomes larger in the case of higher program voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PGM</sub> ), lower field oxide height, slower program speed of the adjacent cell, and high <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vt</i> of victim cell. The experimental results suggest that the mechanism of negative <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vt</i> shift is attributed to hot holes that are generated by FN electron injection from channel/junction to the control gate. This phenomenon will become worse with cell size scaling since hot hole generation is increased by increasing the electron injection due to narrower floating gate space. Therefore, this negative <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vt</i> shift phenomenon is one of the new scaling limiters of nand Flash memory cell, which needs to be managed for 2 and 3 b/cell in 2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</i> nm and beyond nand Flash memories.

A New Recess Method for SA-STI nand Flash Memory

In this letter, we propose a new shallow trench isolation (STI) recess effect on the self-aligned STI of nand Flash memory devices. In the current nand Flash cell design, increasing the recess depth of STI recess yields a higher gate coupling ratio and lower floating-gate (FG) interference to achieve better immunity to process fluctuation. However, the current design is limited by significantly slower Fowler–Nordheim (FN) erase speed and degraded channel characteristics. Slow erase speed is caused by the accumulation of holes around channel edges, while the degraded channel is owing to FN cycling stress-induced interface damage. The proposed STI recess structure maintains a proper distance between the channel edge and the control gate, as well as blocks the FG interference without increasing cell-to-cell spacing.

Edge Profile Effect of Tunnel Oxide on Erase Threshold-Voltage Distributions in Flash Memory Cells

The erase threshold-voltage (VT) distribution in Flash electrically erasable programmable read-only memory cells was investigated versus the tunnel oxide edge profiles in self-aligned shallow trench isolation (SA-STI) and self-aligned poly (SAP) cells. The capacitive coupling with offset voltage correction is transcribed into VT transient for simulating erase VT dispersion without numerous full structure device simulations. It is shown that SAP gives rise to smaller VT dispersion, compared with SA-STI. The VT dispersion resulting from variations in dielectric thickness and oxide edge profiles is shown to fall far short of observed VT distribution, calling for examination of additional process and cell parameters

A 1.8-V 256-Mb Multilevel Cell NOR Flash Memory With BGO Function

This paper describes a 1.8-V-only 256-Mb four-level-cell (2 b/cell) NOR flash memory with background operation (BGO) function fabricated in a 130-nm CMOS self-aligned shallow trench isolation (SA-STI) process technology. The new memory array architecture is adopted in which the flash source is connected by local interconnect to reduce the source resistance and constrain the floating-gate coupling effect. The mirrored current sensing read architecture for multilevel-cell operation at a supply voltage of 1.8 V has realized a fast asynchronous random access time (67 ns) and burst read at 54 MHz. A high speed and high reliability of program/erase cycling (100 k) has been achieved by dual-step pulse program algorithm and optimized erase sequence. Page program time and block erase time are 1.54 ms/2 kb and 538 ms/1 Mb, respectively