Self-aligned Quadruple Patterning Research Articles

Application of Self-aligned Quadruple Patterning to Fabrication of Nanoimprint Mold with Sub-12-nm Half-pitch

Application of Self-aligned Quadruple Patterning to Fabrication of Nanoimprint Mold with Sub-12-nm Half-pitch

Plasma enhanced atomic layer deposition of silicon nitride using magnetized very high frequency plasma

To obtain high-quality SiN x films applicable to an extensive range of processes, such as gate spacers in fin field-effect transistors (FinFETs), the self-aligned quadruple patterning process, etc, a study of plasma with higher plasma density and lower plasma damage is crucial in addition to study on novel precursors for SiN x plasma-enhanced atomic layer deposition (PEALD) processes. In this study, a novel magnetized PEALD process was developed for depositing high-quality SiN x films using di(isopropylamino)silane (DIPAS) and magnetized N2 plasma at a low substrate temperature of 200 °C. The properties of the deposited SiN x films were analyzed and compared with those obtained by the PEALD process using a non-magnetized N2 plasma source under the same conditions. The PEALD SiN x film, produced using an external magnetic field (ranging from 0 to 100 G) during the plasma exposure step, exhibited a higher growth rate (∼1 Å/cycle) due to the increased plasma density. Additionally, it showed lower surface roughness, higher film density, and enhanced wet etch resistance compared to films deposited using the PEALD process with non-magnetized plasmas. This improvement can be attributed to the higher ion flux and lower ion energy of the magnetized plasma. The electrical characteristics, such as interface trap density and breakdown voltage, were also enhanced when the magnetized plasma was used for the PEALD process. Furthermore, when SiN x films were deposited on high-aspect-ratio (30:1) trench patterns using the magnetized PEALD process, an improved step coverage of over 98% was achieved, in contrast to the conformality of SiN x deposited using non-magnetized plasma. This enhancement is possibly a result of deeper radical penetration enabled by the magnetized plasma.

Bayesian dropout approximation in deep learning neural networks: analysis of self-aligned quadruple patterning

BackgroundPredictive estimates of the final process outcome(s) of multistep, coupled processes can be difficult to make based on data measured at the various process steps. Self-aligned quadruple patterning (SAQP) is an example of such a process where the prediction of pitch-walk is desired at the various process steps.AimsBe able to both predict pitch-walk values and the uncertainty in the predicted values at SAQP process steps based on optical critical dimension (OCD) spectroscopy outputs (dimensions, angles, thicknesses, and so on) of mandrel, spacer, and other SAQP features.ApproachTrain a neural network using OCD-modeled values of an SAQP process to be able to predict SAQP pitch-walk at early process steps. Use Bayesian dropout approximation (BDA), a methodology using Bayesian inference with stochastic neural networks, to estimate uncertainty in the predicted SAQP pitch-walk.ResultsAble to predict pitch-walk values, and the uncertainty in the predictions, of the final SAQP structure after the deposition of the first spacer. The pitch-walk predictions become more accurate as OCD information from the bottom mandrel RIE and bottom spacer are added as inputs to the BDA network.ConclusionsIn contrast to a single output value that traditional neural networks would predict, BDA makes an estimated distribution of predictions, where the BDA network gives both a most likely value as well as a distribution of potential values. While this paper shows the power of BDA to predict SAQP pitch walk, it is expected that BDA will be a valuable tool to analyze many data sets in semiconductor manufacturing to help improve yield and performance.

(Digital Presentation) Extending the Application of Capacitively Coupled Plasma Etching Tools to the Front-End-of-Line Fin-Cut Etching Process for FinFET Mass Production

As FinFET scales down to advanced technology nodes, Self-aligned Quadruple Patterning (SaQP) scheme is widely deployed for Fin formation, where two mandrels (MD1 and MD2) and corresponding mandrel spacers (MD1SP and MD2SP) are patterned for accurate CD transferring. The Fin-cut etching process of the MD2SP Cutting is very critical for the patterning of the Standard Cell and the SRAM patterns. This work studies the application of the Front End of Line (FEoL) MD2SP Cutting process in both inductively coupled plasma (ICP) and capacitively coupled plasma (CCP) etchers. The mismatch between the two tools is observed and discussed in detail. For CCP tools, a degradation of line width roughness (LWR) and increase of critical dimension (CD) loading between dense and isolated patterns are observed. Compared with the ICP etchers, the CCP etchers have lower plasma dissociation and stronger physical bombardment of ions. Furthermore, it is harder to control the plasma density and directionality separately. To increase CCP tool applications in FEoL processes, we introduce a Silicon coating process to modify the photoresist (PR) during the CCP etching to harden the surface of the PR and enhance the LWR performance. Furthermore, the application of atomic layer etching (ALE) technology ensures the CD loading between the dense and isolated patterns. With the application of our study, we can broaden the application of CCP tools in FEoL for FinFET mass production.

(Digital Presentation) An Advanced Process Control Scheme for Fin Etching Process in Front-End-of-Line FinFET High Volume Production

As FinFET scales down to advanced technology nodes, Fin profile and Critical Dimension (CD) control are becoming a huge challenge due to the increased number of processes. For a stable wafer-to-wafer CD performance, Advanced Process Control (APC) system is widely deployed in high volume manufacturing production. In this work, we present a novel implementation of an APC-based fuzzy control system in the Fin etching process within the widely-used Self-aligned Quadruple Patterning (SaQP) scheme. Feed-forward APC is applied to the two processes: 1) Atomic Layer Deposition (ALD) process for fin hard-mask etching and 2) fin etching process with fuzzy control. With the deployment of the APC system, the inline metrology variation performance of Fin CD improved from ±3.5% to ±1.8%. The Cp and Cpk are increased by 29% and 32%, for various key inline parameters. The APC-based fuzzy control scheme shows great potential for the advanced nodes.

New bending mode in SAQP Si fins and its mitigation

Self-Aligned Quadruple Patterning (SAQP) is used in advanced CMOS-FET technologies to enable the formation of arrays of fins at sub-40 nm pitches. As these technology nodes keep scaling down and the fins get taller for performance improvement, the patterns become denser and present very high aspect ratio (HAR). The scaling trends make the fin pattern more subject to mechanical instabilities during the processing steps. We describe in this paper a specific mechanical fin bending mode linked to the SAQP scheme targeting 24 nm pitch, the HAR and the formation and recess steps of the isolating oxide. We investigated the evolution of fin bending throughout the fin and isolation formation. We observed fins start bending at the FCVD deposition step exhibiting rotation angles up to 3 degrees. The bending was then worsened along the subsequent process steps causing mechanical failure after fin reveal where up to 7–8° of bending angles were observed. After having studied the influence of the key process steps, we can report a path to mitigate this phenomenon. Finally, we propose a simple mechanical analysis to validate quantitatively the root cause and extrapolate the mechanical robustness of this system for further scaling nodes where fin pitch is reduced.

The Line Roughness Improvement in Self-aligned Multiple Patterning

Multi-patterning has been widely used in the semiconductor industry to enable the continued scaling requirement such as Fin, Gate, and critical Metal lines. Either Self-aligned Multiple Patterning (SaMP) or Litho-Etch/Litho-Etch (LELE) shows plasma etch become more dominant for the line edge and width roughness (LER/LWR) than single patterning technology [1]. To mitigate the strict line roughness requirements for advanced technology nodes (14nm and below), we proposed and demonstrated a novel nitrogen-based Inductively Coupled Plasma (ICP) treatment and an argon-based Capacitively Coupled Plasma (CCP) treatment on LER/LWR improvement, separately. Both recipes are optimized with an optimal design experiment (ODE) statistical method. The optimal organic mandrel etch recipe can improve the LER of the final pattern to 1.2nm. Furthermore, two effective Si mandrel post etch treatment (PET) methods are investigated: special surface plasma treatment and H2 anneal. The H2 anneal effect was found related to the capping layer, different from former published paper. We also found out the different chemistry in Spacer etch can impact line roughness but trade-off with defect performance. Finally, we achieved a 20% LWR improvement of final pattern in a self-aligned quadruple patterning (SAQP) without any side effect.

The Line Roughness Improvement in Self-Aligned Multiple Patterning

Multi-patterning has been widely adopted in the semiconductor manufacturing industry to enable the continued scaling requirement such as fin, gate, and critical metal lines. Either Self-aligned Multiple Patterning (SaMP) or Litho-Etch-Litho-Etch (LELE) shows plasma etch becomes more dominant for the line roughness than single patterning technology (1). To mitigate the strict line roughness requirements for advanced technology nodes, we demonstrated a novel nitrogen-based inductively coupled plasma (ICP) treatment. The recipe was optimized with an optimal design experiment (ODE). The optimal mandrel etch recipe coupled with HBr plasma curing can improve 60% line edge roughness (LER) of the final pattern. Furthermore, two post etch treatment (PET) methods were investigated on Si mandrel: special argon-based plasma treatment and hydrogen annealing. The hydrogen annealing effect was found related to the capping layer, different from previously published paper. Finally, we achieved a 20% line width roughness (LWR) improvement of final pattern in a self-aligned quadruple patterning (SaQP) without any side effect.

Line edge roughness metrology: recent challenges and advances toward more complete and accurate measurements

Two fundamental challenges of line edge roughness (LER) metrology are to provide complete and accurate measurement of LER. We focus on recent advances concerning both challenges inspired by mathematical and computational methods. Regarding the challenge of completeness: (a) we elaborate on the multifractal analysis of LER, which decomposes the scaling behavior of edge undulations into a spectrum of fractal dimensions similarly to what a power spectral density (PSD) does in the frequency domain. Emphasis is given on the physical meaning of the multifractal spectrum and its sensitivity to pattern transfer and etching; (b) we present metrics and methods for the quantification of cross-line (interfeature) correlations between the roughness of edges belonging to the same and nearby lines. We will apply these metrics to quantify the correlations in a self-aligned quadruple patterning lithography. Regarding the challenge of accuracy, we present a PSD-based method for a noise-reduced (sometimes called unbiased) LER metrology and validate it through the analysis of synthesized SEM images. Furthermore, the method is extended to the use of the height–height correlation functions to deliver noise-reduced estimation of the correlation length and the roughness exponent of LER.

Linewidth roughness of advanced semiconductor features using focused ion beam and planar-transmission electron microscope as reference metrology

Line edge roughness (LER) and linewidth roughness (LWR) of a semiconductor device are important measures for evaluating its performance. Conventionally, LER and LWR have been evaluated from critical dimension scanning electron microscope (CD-SEM) images. However, the problem with CD-SEM measurement is that the high-frequency image noise is large, and the resolution is not sufficiently high. In order to overcome the problem of image noise in CD-SEM measurement, some techniques have been proposed. In these methods, it is necessary to set the parameters for the model and processing, and it is required to verify the correctness of these parameters using reference metrology. We have already proposed a reference metrology using the focused ion beam process and planar transmission electron microscope (planar-TEM) method. In this study, we apply the proposed method to three new samples, namely self-aligned quadruple patterning fin-shaped field-effect transistor device, extreme ultraviolet lithography (EUV) conventional resist, and EUV new material resist. The LWR and the power spectral density (PSD) of LWR are calculated from the edge positions on planar-TEM images. We confirm that the LWR and the PSD of LWR can be measured with high accuracy and evaluate the difference between PSD by the proposed method and that by CD-SEM images. Furthermore, from comparisons with the PSD of the same sample obtained using CD-SEM, the validity of measurement of PSD and LWR by CD-SEM is verified.

Improvement of Line Width Roughness and Line Edge Roughness for Ultrascaled Finfet Technologies

As FinFET feature size scaling down, the fins are against more critical challenges by using either self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) method. Wiggling, line width roughness (LWR) and line edge roughness (LER) play more crucial roles at sub-14nm technology and beyond. Traditionally, post plasma treatment methods for photoresist are largely investigated to improve the LWR and LER. For the SADP and SAQP technology, pattern transferring is also another critical feature of dry etch process for pattern line wiggling. In this paper, both plasma photoresist treatment and dry etch process optimization are studied for improving LWR and LER.

Etch considerations for directed self-assembly patterning using capacitively coupled plasma

Alternative patterning strategies are pursued to push the device feature size below the physical limit of optical lithography as the semiconductor manufacturing industry is preparing for production at sub-10 nm technology node. Extreme ultraviolet (EUV) lithography, 193 nm immersion augmented with multiple patterning schemes (“self-aligned double patterning,” “self-aligned quadruple patterning”) and “directed self-assembly (DSA)” are being evaluated as alternatives to meet rising demands of aggressive patterning. EUV lithography reduces the number of processing steps, but it is yet to achieve full maturity in terms of resist materials, throughput, and manufacturability. DSA when augmented with 193 nm immersion guide prepatterns can aid in reducing the pitch of final structures. There is no infrastructure upgrade cost involved as the key processing steps of DSA are conducted in existing wafer track systems. The authors have successfully demonstrated DSA pattern transfer into metal hard masks for the back end of the line application and nonmetal hard masks for the front end of the line applications. However, DSA comes with its own challenges posed in the form of polymer-to-polymer selectivity, mask budget, post-lithography defects, mask shape, critical dimension control, and line edge roughness (LER). The authors address the challenge of selectivity and roughness correction by using spatially uniform low-density plasma obtained in dual (low and high) frequency midgap capacitively coupled plasma etcher. A parametric study of an O2/Ar gas chemistry based plasma etch of widely studied poly(styrene-block-methyl methacrylate) (PS-b-PMMA) films is used to describe how plasma parameters impact PMMA removal selective to PS and LER during plasma etch pattern transfer using DSA lithography. The effects of etchant gas concentration and deposition gas addition for preferential passivation of the PS mask are investigated during PMMA etch. Their results indicate modulation of ion energy through bias power adjustments can be used to improve selectivity. Zero bias power optimal; however, roughness degrades at this condition necessitating inclusion of other solutions. Controlled addition of hydrocarbon gas enhances the selectivity further. Low frequency peak-to-peak voltage and high frequency power most strongly correlate with LER; hydrocarbon addition has little effect. Relative balance between various fluxes and ion energy is needed to obtain the maximum reduction in roughness with the required selectivity.

Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing

Because of the delay of the next-generation lithography technologies, self-aligned double patterning (SADP) has become one of the major lithography solutions for sub-20-nm technology nodes. For advanced sub-10-nm nodes, self-aligned quadruple patterning (SAQP) or even self-aligned octuple patterning will be required. Due to considerable design complexity and unmanageable process variation, 1-D grid-based layout structure will be adopted, which can be achieved with sophisticated self-aligned multiple patterning (SAMP) process with the use of a cut mask. However, cut masks for arbitrary layouts are hardly manufacturable, because cut mask rules are limited by conventional 193-nm lithography. To the best of our knowledge, most of the existing SADP- and SAQP-aware detailed routers would fail to generate cut mask-friendly routing results for general SAMP. In this paper, we propose the first work of cut mask optimization with wire planning in SAMP full-chip routing. We first identify cut mask-aware routing rules to guide our router. Then, cut mask-aware wire planning, detailed routing, and postlayout modification techniques are proposed in the routing flow. Experimental results show that the proposed routing algorithms are effective in generating routing results with optimized cut masks.

A Routing Method Using Directed Grid-Graph for Self-Aligned Quadruple Patterning

A Routing Method Using Directed Grid-Graph for Self-Aligned Quadruple Patterning

Measuring self-aligned quadruple patterning pitch walking with scatterometry-based metrology utilizing virtual reference

Advanced technology nodes, 10 nm and beyond, employing multipatterning techniques for pitch reduction pose new process and metrology challenges in maintaining consistent positioning of structural features. A self-aligned quadruple patterning (SAQP) process is used to create the fins in FinFET devices with pitch values well below optical lithography limits. The SAQP process bears the compounding effects from successive reactive ion etch and spacer depositions. These processes induce a shift in the pitch value from one fin compared to another neighboring fin. This is known as pitch walking. Pitch walking affects device performance as well as later processes, which work on an assumption that there is consistent spacing between fins. In SAQP, there are three pitch walking parameters of interest, each linked to specific process steps in the flow. These pitch walking parameters are difficult to discriminate at a specific process step by singular evaluation technique or even with reference metrology, such as transmission electron microscopy. We will utilize a virtual reference to generate a scatterometry model to measure pitch walk for SAQP process flow.

Analysis of multi-e-beam lithography for cutting layers at 7-nm node

Technology node scaling to the 7-nm node, self-aligned quadruple patterning plus cutting/blocking is widely adopted as a lithography solution for critical line and space layers. The cutting/blocking process can be done by 193i or EUV lithography. Due to resolution requirements in both X/Y directions, 193i requires two or three exposures to accomplish the cutting/blocking process, and the overlay among the exposures must be controlled very tightly. EUV can accomplish cutting/blocking by one exposure. However, the extremely high cost of EUV tool and mask, together with not so high throughput, appears to suggest that EUV lithography is not a cost-effective solution. From both technical and cost perspectives, we explore the possibility of using multi-e-beam lithography as an alternative solution for 7-nm cutting/blocking layers. First, we analyze design rules, which define resolution and overlay requirements of the cutting/blocking patterns. Then we report the lithography performance data of our leading-edge multi-e-beam tool and compare them with the cutting/blocking requirements. Finally, we do the cost analysis. Our results indicate that multi-e-beam lithography has a cost per wafer per layer advantage if it can commit a resolution of 32-nm half pitch, an overlay of <2.8 nm, and a throughput of 5 to 10 wph.

Virtual fabrication using directed self-assembly for process optimization in a 14-nm dynamic random access memory

For directed self-assembly (DSA) to be deployed in advanced semiconductor technologies, it must reliably integrate into a full process flow. We present a methodology for using virtual fabrication software, including predictive DSA process models, to develop and analyze the replacement of self-aligned quadruple patterning with Liu–Nealey chemoepitaxy on a 14-nm dynamic random access memory (DRAM) process. To quantify the impact of this module replacement, we investigated a key process yield metric for DRAM, interface area between the capacitor contacts and transistor source/drain. Additionally, we demonstrate virtual fabrication of the DRAM cell’s hexagonally packed capacitors patterned with an array of diblock copolymer cylinders in place of fourfold litho-etch (LE4) patterning.

Self-aligned quadruple patterning to meet requirements for fins with high density

Self-aligned quadruple patterning to meet requirements for fins with high density

ASAP7: A 7-nm finFET predictive process design kit

We describe a 7-nm predictive process design kit (PDK) called the ASAP7 PDK, developed in collaboration with ARM Ltd. for academic use. The PDK is realistic, based on current assumptions for the 7-nm technology node, but is not tied to any specific foundry. The initial version assumes EUV lithography for key layers, a decision based on its present near cost-effectiveness and resulting simpler layout rules. Non-EUV layers assume appropriate multiple patterning schemes, i.e., self-aligned quadruple patterning (SAQP), self-aligned double patterning (SADP) or litho-etch litho-etch (LELE), based on 193-nm optical immersion lithography. The specific design rule derivation is explained for key layers at the front end of line (FEOL), middle of line (MOL), and back end of line (BEOL) of the predictive process modeled. The MOL and BEOL DRC rules rely on estimation of time dependent dielectric breakdown requirements using layer alignments determined with projected machine to machine overlay assumptions, with significant guard-bands where possible. A high density, low-power standard cell architecture, developed using design/technology co-optimization (DTCO), as well as example SRAM cells are shown. The PDK transistor electrical assumptions are also explained, as are the FEOL design rules, and the models include basic design corners. The transistor models support four threshold voltage (Vth) levels for both NMOS and PMOS transistors. Cadence Virtuoso technology files and associated schematic and layout editing, as well as netlisting are supported. DRC, LVS, and full parasitic extraction is enabled through Mentor Calibre decks.

Architectural strategies in standard-cell design for the 7 nm and beyond technology node

Standard-cell design and characterization are presented for 7-nm CMOS platform technology targeting low-power and high-performance applications with the tightest contacted poly pitch of 42 nm and a metallization pitch of 32 nm in the FinFET technology. Two standard-cell architectures for 7 nm, a 9-track library and a 7.5-track library have been designed, introducing an extra middle-of-line layer to enable an efficient layout of the 7.5-track cells. The 7.5-track cells are on average smaller than the 9-track cells. With the strict design constraints imposed by self-aligned quadruple patterning and self-aligned double patterning, careful design and technology co-optimization is performed.