Self-aligned Process Research Articles

Spectroscopic Analysis of Electrical Phenomena and Oxygen Vacancy Generation for Self-Aligned Fully Solution-Processed Oxide Thin-Film Transistors.

This work unveils critical insights through spectroscopic analysis highlighting electrical phenomena and oxygen vacancy generation in self-aligned fully solution-processed oxide thin-film transistors (TFTs). Ar inductively coupled plasma treatment was conducted to fabricate an amorphous indium zinc oxide (a-InZnO) TFT in a self-aligned process. Results showed that the Ar plasma-activated a-InZnO regions became conductive, which means that a homogeneous layer can act as both channel and electrode in the device. Several techniques were employed to probe specific aspects of the source-drain-channel interface in the fully solution-processed TFTs. X-ray absorption near-edge structure and Extended X-ray absorption fine structure were conducted to investigate the existence of oxygen vacancies, which is the main driving factor in inducing a conductive region. X-ray photoelectron spectroscopy was also used to explain the oxygen refilling mechanism. Ultraviolet Photoelectron Spectroscopy was conducted to analyze the valence band maximum and work function. Integration of these results facilitated the construction of the energy band diagram at the interface, wherein a Schottky barrier height of ∼0.37 eV was observed. By leveraging these techniques, insights into the electronic properties and performance of next-generation transistors are gained, enabling their future widespread adoption.

Innovative Integration of Dual Quantum Cascade Lasers on Silicon Photonics Platform.

For the first time, we demonstrate the hybrid integration of dual distributed feedback (DFB) quantum cascade lasers (QCLs) on a silicon photonics platform using an innovative 3D self-aligned flip-chip assembly process. The QCL waveguide geometry was predesigned with alignment fiducials, enabling a sub-micron accuracy during assembly. Laser oscillation was observed at the designed wavelength of 7.2 μm, with a threshold current of 170 mA at room temperature under pulsed mode operation. The optical output power after an on-chip beam combiner reached sub-milliwatt levels under stable continuous wave operation at 15 °C. The specific packaging design miniaturized the entire light source by a factor of 100 compared with traditional free-space dual lasers module. Divergence values of 2.88 mrad along the horizontal axis and 1.84 mrad along the vertical axis were measured after packaging. Promisingly, adhering to i-line lithography and reducing the reliance on high-end flip-chip tools significantly lowers the cost per chip. This approach opens new avenues for QCL integration on silicon photonic chips, with significant implications for portable mid-infrared spectroscopy devices.

Self-Aligned Edge Contact Process for Fabricating High-Performance Transition-Metal Dichalcogenide Field-Effect Transistors.

The persistent challenges encountered in metal-transition-metal dichalcogenide (TMD) junctions, including tunneling barriers and Fermi-level pinning, pose significant impediments to achieving optimal charge transport and reducing contact resistance. To address these challenges, a pioneering self-aligned edge contact (SAEC) process tailored for TMD-based field-effect transistors (FETs) is developed by integrating a WS2 semiconductor with a hexagonal boron nitride dielectric via reactive ion etching. This approach streamlines semiconductor fabrication by enabling edge contact formation without the need for additional lithography steps. Notably, SAEC TMD-based FETs exhibit exceptional device performance, featuring a high on/off current ratio of ∼108, field-effect mobility of up to 120 cm2/V·s, and controllable polarity─essential attributes for advanced TMD-based logic circuits. Furthermore, the SAEC process enables precise electrode positioning and effective minimization of parasitic capacitance, which are pivotal for attaining high-speed characteristics in TMD-based electronics. The compatibility of the SAEC technique with existing Si self-aligned processes underscores its feasibility for integration into post-CMOS applications, heralding an upcoming era of integration of TMDs into Si semiconductor electronics. The introduction of the SAEC process represents a significant advancement in TMD-based microelectronics and is poised to unlock the full potential of TMDs for future electronic technologies.

Achieving High-Performance Polymer-Wrapper-Free Aligned Carbon Nanotube Field-Effect Transistors Through Degradable Polymer Wrapping and Efficient Removal Techniques.

Semiconducting carbon nanotubes (s-CNTs) have emerged as a promising alternative to traditional silicon for ultrascaled field-effect transistors (FETs), owing to their exceptional properties. Aligned s-CNTs (A-CNTs) are particularly favored for practical applications due to their ability to provide higher driving current and lower contact resistance compared with individual s-CNTs or random networks. Achieving high-semiconducting-purity A-CNTs typically involves conjugated polymer wrapping for selective separation of s-CNTs, followed by self-assembly techniques. However, the presence of the polymer wrapper on A-CNTs can adversely impact electrical contact, gating efficiency, carrier transport, and device-to-device variations, necessitating its complete removal. While various methods have been explored for polymer removal, accurately characterizing the extent of removal remains a challenge. Traditional techniques such as absorption spectroscopy and X-ray photoelectron spectroscopy (XPS) may not accurately depict the remaining polymer content on A-CNTs due to their inherent detection limits. Consequently, the performance of FETs based on pure polymer-wrapper-free A-CNTs is unclear. In this study, we present an approach for preparing high-semiconducting-purity and polymer-wrapper-free A-CNTs using poly[(9,9-dioctylfluorenyl-2,7-dinitrilomethine)-(9,9-dioctylfluorenyl-2,7-dimethine)] (PFO-N-PFO), a degradable polymer, in conjunction with a modified dimension-limited self-alignment process (m-DLSA). Comprehensive transmission electron microscopy (TEM) characterizations, complemented by absorption and XPS characterizations, provide robust evidence of the successful near-complete removal of the polymer wrapper via a cleaning procedure involving acidic degradation, hot solvent rinsing, and vacuum annealing. Furthermore, top-gated FETs based on these high-semiconducting-purity and polymer-wrapper-free A-CNTs exhibit good performance metrics, including an on-current (Ion) of 2.2 mA/μm, peak transconductance (gm) of 1.1 mS/μm, low contact resistance (Rc) of 191 Ω·μm, and negligible hysteresis, representing a significant advancement in the CNT-based FET technology.

Demonstration of a lateral p-NiO/n-GaN JFET fabricated by selective-area regrowth

In this paper, we demonstrated experimentally a lateral GaN-based junction field effect transistor (JFET). A selective area regrowth of p-NiO on the as-grown n-GaN channel layer was developed by magnetron sputtering at room temperature to form the p–n junction. A self-aligned gate process and a post metal annealing process were employed to improve the device performances. The measured results show that the annealed JFET exhibits an ON/OFF ratio exceeding 106 and a higher breakdown voltage up to 814 V without any terminal structure. The breakdown voltage is determined by the reverse breakdown of parasitic PN junction between gate and drain. Further, the threshold voltage of the p-NiO/n-GaN JFET exhibits excellent temperature stability in the range of 300–500 K.

A symmetric heterogate dopingless electron-hole bilayer TFET with ferroelectric and barrier layers

In this paper, a symmetric heterogate dopingless electron–hole bilayer tunnel field-effect transistor with a ferroelectric layer and a dielectric barrier layer (FBHD-EHBTFET) is proposed. FBHD-EHBTFET can not only avoid random doping fluctuation and high thermal budget caused by doping, but also solve the issue that conventional EHBTFETs are unable to use the self-alignment process during device manufacturing. The simultaneous introduction of the symmetric heterogate and dielectric barrier layer can significantly suppress off-state current (I off). Ferroelectric material embedded in the gate dielectric layer can enhance electron tunneling, contributing to improving on-state current (I on) and steepening average subthreshold swing (SS avg). By optimizing various parameters related to the gate, ferroelectric layer, and dielectric barrier layer, FBHD-EHBTFET can obtain the I off of 1.11 × 10–18 A μm−1, SS avg of 12.5 mV/dec, and I on of 2.59 × 10–5 A μm−1. Compared with other symmetric dopingless EHBTFETs, FBHD-EHBTFET can maintain high I on while reducing its I off by up to thirteen orders of magnitude and SS avg by at least 51.2%. Moreover, investigation demonstrates that both interface fixed charge and interface trap can increase I off, degrading the off-state performance of device. The study on FBHD-EHBTFET-based dynamic random access memory shows that it has the high read-to-current ratio of 1.1 × 106, high sense margin of 0.42 μA μm−1, and long retention time greater than 100 ms, demonstrating that it has great potential in low-power applications.

Integration of buried nanomagnet and silicon spin qubits in a one-dimensional fin structure

We adopt a buried nanomagnet (BNM) technology on a one-dimensional (1D) array of silicon spin qubits, and its availability was investigated using numerical simulations. The qubit array is formed in the center of the Si fin and the nanomagnet is buried in the lower lateral part of the qubits. The nanomagnet placed near the qubit generates a strong slanting magnetic field in the qubit, enabling X-gate operation approximately 15 times faster than in conventional cases. Furthermore, the formation of a BNM using a self-aligned process suppresses the dimensional variation of the nanomagnet caused by process variation, thereby mitigating the slanting field fluctuation and fidelity degradation. In addition, even for multiple qubits formed in the Si fin, the BNM with excess length generated a uniform slanting field, mitigating fidelity degradation and enabling all qubits to operate using a single-frequency microwave. Therefore, the proposed structure is useful for 1D integrated structures.

NbTiN SQUID-on-tip fabricated by self-aligned deposition using reactive DC magnetron sputtering

We fabricate superconducting quantum interference devices (SQUIDs) made of niobium-titanium nitride (NbTiN) thin films on the apex of sharp quartz capillaries. By incorporating reactive DC magnetron sputtering into the self-aligned deposition process for the SQUID-on-tip (SOT) fabrication, we produce NbTiN SOT devices with an effective diameter of ∼100 nm. The ø110 nm device has a superconducting transition temperature of 13.2 K, magnetic flux noise down to 0.7 μΦ0/Hz0.5 (4 K), and operating temperatures of 1.8–10 K. The developed technique enables the synthesis of nitride and other superconductors, thereby expanding the range of materials available for SOT devices.

High-Performance LiNbO3 Domain Wall Memory Devices with Enhanced Selectivity via Optimized Metal-Semiconductor Contact.

Lithium niobate (LiNbO3) single-crystal nanodevices featuring elevated readout domain wall currents exhibit significant potential for integrated circuits in memory computing applications. Nevertheless, challenges stem from suboptimal electrode-LiNbO3 single crystal contact characteristics, which impact the stability of high currents within these devices. In this work, we concentrate on augmenting the domain wall current by refining the fabrication processes of domain wall random access memory (DWRAM). Each LiNbO3 domain wall nanodevice was fabricated using a self-aligned process. Device performance was significantly enhanced by introducing a 10 nm interlayer between the LiNbO3 and Cu electrodes. A comparative analysis of electrical properties was conducted on devices with interlayers made of chromium (Cr) and titanium (Ti), as well as devices without interlayers. After the introduction of the Ti interlayer, the device's coercive voltage demonstrated an 82% reduction, while the current density showed a remarkable 94-fold increase. A 100 nm sized device with the Ti interlayer underwent positive down-negative up pulse testing, demonstrating a writing time of 82 ns at 8 V and an erasing time of 12 μs at -9 V. These operating speeds are significantly faster than those of devices without interlayers. Moreover, the enhanced devices exhibited symmetrical domain switching hysteresis loops with retention times exceeding 106 s. Notably, the coercive voltage (Vc) dispersion remained narrow after more than 1000 switching cycles. At an elevated temperature of 400 K, the device's on/off ratio was maintained at 105. The device's embedded selector demonstrated an ultrahigh selectivity (>106) across various reading voltages. These results underscore the viability of high-density nanoscale integration of ferroelectric domain wall memory.

Plasma enhanced atomic layer deposition of silicon nitride using magnetized very high frequency plasma

To obtain high-quality SiN x films applicable to an extensive range of processes, such as gate spacers in fin field-effect transistors (FinFETs), the self-aligned quadruple patterning process, etc, a study of plasma with higher plasma density and lower plasma damage is crucial in addition to study on novel precursors for SiN x plasma-enhanced atomic layer deposition (PEALD) processes. In this study, a novel magnetized PEALD process was developed for depositing high-quality SiN x films using di(isopropylamino)silane (DIPAS) and magnetized N2 plasma at a low substrate temperature of 200 °C. The properties of the deposited SiN x films were analyzed and compared with those obtained by the PEALD process using a non-magnetized N2 plasma source under the same conditions. The PEALD SiN x film, produced using an external magnetic field (ranging from 0 to 100 G) during the plasma exposure step, exhibited a higher growth rate (∼1 Å/cycle) due to the increased plasma density. Additionally, it showed lower surface roughness, higher film density, and enhanced wet etch resistance compared to films deposited using the PEALD process with non-magnetized plasmas. This improvement can be attributed to the higher ion flux and lower ion energy of the magnetized plasma. The electrical characteristics, such as interface trap density and breakdown voltage, were also enhanced when the magnetized plasma was used for the PEALD process. Furthermore, when SiN x films were deposited on high-aspect-ratio (30:1) trench patterns using the magnetized PEALD process, an improved step coverage of over 98% was achieved, in contrast to the conformality of SiN x deposited using non-magnetized plasma. This enhancement is possibly a result of deeper radical penetration enabled by the magnetized plasma.

First Self-Aligned Heliostat Prototype at the Plataforma Solar de Almeria

It is a generally admitted fact that the optical aligning process of faceted heliostats in a Solar Power Tower Plant (SPTP), also called heliostat canting, introduces an assembly time penalization as well as a potential error in heliostat optics conformation [1, 2]. This double penalization influences both the solar field setup time and the optical quality of the SPTP. Aware of this fact, in 2014 the Plataforma Solar de Almeria (PSA) developed and patented a method to self-align facets and thus avoid the critical canting phase of a heliostat [3]. To experimentally demonstrate the feasibility of the self-aligning facet process, a small reflector composed of six facets and 9m2 of reflecting surface was designed and fabricated. The success of that experience has led to the development of a first 18.5m2 prototype of a self-aligned heliostat, which has been installed at the CESA-1 Heliostat Field (PSA) in 2022.

Process optimization of titanium self-aligned silicide formation through evaluation of sheet resistance by design of experiment methodology

A low-resistivity titanium silicide (TiSi2) is crucial as a gate and source/drain material in microelectronic device fabrication, offering notable properties to enhance device performance. This study aims to experimentally determine the optimum process parameters, including arsenic doping dosage, titanium thickness, and two-step rapid thermal process (RTP) temperature, for the sheet resistance of titanium self-aligned silicide process using a design of experiment methodology. The results demonstrate that both the thickness of the titanium and the temperature of the RTP play crucial roles in determining the sheet resistance of TiSi2. Statistical analysis reveals that increasing the titanium thickness or the temperature of the first-step RTP (RTP-1) could reduce the sheet resistance. Additionally, an optimal second-step RTP (RTP-2) temperature is critical to yield low-resistivity TiSi2 by completely converting C49- to C54-phase. The optimum process conditions for obtaining low sheet resistance are a titanium thickness of 32–35 nm, RTP-1 temperature of 720–750 °C for 75 s, and RTP-2 temperature of 860 °C for 20 s. Moreover, surface amorphization of the polysilicon by arsenic ion implantation before the deposition of Ti/TiN films also plays a crucial role in the formation of C54-TiSi2. The lowest sheet resistance achieved was 3.91 Ω/sq with an arsenic dosage of 1 × 1014 cm−2. The optimum condition was adopted for forming a submicron polysilicon gate, providing a promising approach for designing the process parameters for titanium self-aligned silicide formation to achieve low resistance in nanoscale electronic devices.

Driving Principle and Stability Analysis of Vertical Comb-Drive Actuator for Scanning Micromirrors.

We have developed a manufacturing process for micromirrors based on microelectromechanical systems (MEMS) technology. The process involves designing an electrostatic vertically comb-driven actuator and utilizing a self-alignment process to produce a height difference between the movable comb structure and the fixed comb structure of the micromirror. To improve the stability of the micromirror, we propose four instability models in micromirror operation with the quasi-static driving principle and structure of the micromirror considered, which can provide a basic guarantee for the performance of vertical comb actuators. This analysis pinpoints factors leading to instability, including the left and right gap of the movable comb, the torsion beams of the micromirror, and the comb-to-beams distance. Ultimately, the voltages at which device failure occurs can be determined. We successfully fabricated a one-dimensional micromirror featuring a 0.8 mm mirror diameter and a 30 μm device layer thickness. The height difference between the movable and fixed comb structures was 10 μm. The micromirror was able to achieve a static mechanical angle of 2.25° with 60 V@DC. Stable operation was observed at voltages below 60 V, in close agreement with the theoretical calculations and simulations. At the driving voltage of 80 V, we observed the longitudinal displacement movement of the comb fingers. Furthermore, at a voltage of 129 V, comb adhesion occurred, resulting in device failure. This failure voltage corresponds to the lateral torsional failure voltage.

Investigation into the Co-Phase Detection Methodology for Segmented Plane Mirrors Utilizing Grazing Incidence Interferometry

Segmented plane mirrors constitute a crucial component in the self-aligned detection process for large-aperture space optical imaging systems. Surface shape errors inherent in segmented plane mirrors primarily manifest as tilt errors and piston errors between sub-mirrors. While the detection and adjustment techniques for tilt errors are well-established, addressing piston errors poses a more formidable challenge. This study introduces a novel approach to achieve long-range, high-precision, and efficient co-phase detection of segmented plane mirrors by proposing a segmented plane mirror shape detection method based on grazing incidence interferometry. This method serves to broaden the detection range of piston errors, mitigate the issue of the 2π ambiguity resulting from piston errors in co-phase detection, and extend the detection capabilities of the interferometer. By manipulating the incident angle of the interferometer, both rough and precise adjustments of the segmented plane mirrors can be effectively executed.

Highly Customizable 3D Microelectrode Arrays for In Vitro and In Vivo Neuronal Tissue Recordings.

Planar microelectrode arrays (MEAs) for - in vitro or in vivo - neuronal signal recordings lack the spatial resolution and sufficient signal-to-noise ratio (SNR) required for a detailed understanding of neural network function and synaptic plasticity. To overcome these limitations, a highly customizable three-dimensional (3D) printing process is used in combination with thin film technology and a self-aligned template-assisted electrochemical deposition process to fabricate 3D-printed-based MEAs on stiff or flexible substrates. Devices with design flexibility and physical robustness are shown for recording neural activity in different in vitro and in vivo applications, achieving high-aspect ratio 3D microelectrodes of up to 33:1. Here, MEAs successfully record neural activity in 3D neuronal cultures, retinal explants, and the cortex of living mice, thereby demonstrating the versatility of the 3D MEA while maintaining high-quality neural recordings. Customizable 3D MEAs provide unique opportunities to study neural activity under regular or various pathological conditions, both in vitro and in vivo, and contribute to the development of drug screening and neuromodulation systems that can accurately monitor the activity of large neural networks over time.

Ultrashort vertical-channel MoS2 transistor using a self-aligned contact

Two-dimensional (2D) semiconductors hold great promises for ultra-scaled transistors. In particular, the gate length of MoS2 transistor has been scaled to 1 nm and 0.3 nm using single wall carbon nanotube and graphene, respectively. However, simultaneously scaling the channel length of these short-gate transistor is still challenging, and could be largely attributed to the processing difficulties to precisely align source-drain contact with gate electrode. Here, we report a self-alignment process for realizing ultra-scaled 2D transistors. By mechanically folding a graphene/BN/MoS2 heterostructure, source-drain metals could be precisely aligned around the folded edge, and the channel length is only dictated by heterostructure thickness. Together, we could realize sub-1 nm gate length and sub-50 nm channel length for vertical MoS2 transistor simultaneously. The self-aligned device exhibits on-off ratio over 105 and on-state current of 250 μA/μm at 4 V bias, which is over 40 times higher compared to control sample without self-alignment process.

Selective growth of vanadium dioxide on patterned Al/SiO2 substrates by metal–organic chemical vapor deposition

The area-selective growth of vanadium dioxide can provide a valuable self-aligned process promising for novel oxide electronics compatible with silicon technology.

Optimization of measurement in self-aligned liquid crystal optical control devices with two-slit Young’s experiment

We have investigated an interference experiment of the two-slit Young experiment using an improved self-alignment (SA) liquid crystal optical control device structure. The newly developed SA process and optimization of slit structure and slit width were redesigned to micron size in order to make the interference pattern clear. As a result, we observed a clear NOT logic operation where the center peak intensity of the incident light is inverted.

A Novel SiC Trench MOSFET with Self-Aligned N-Type Ion Implantation Technique.

We propose a novel silicon carbide (SiC) self-aligned N-type ion implanted trench MOSFET (NITMOS) device. The maximum electric field in the gate oxide could be effectively reduced to below 3 MV/cm with the introduction of the P-epi layer below the trench. The P-epi layer is partially counter-doped by a self-aligned N-type ion implantation process, resulting in a relatively low specific on-resistance (Ron,sp). The lateral spacing between the trench sidewall and N-implanted region (Wsp) plays a crucial role in determining the performance of the SiC NITMOS device, which is comprehensively studied through the numerical simulation. With the Wsp increasing, the SiC NITMOS device demonstrates a better short-circuit capability owing to the reduced saturation current. The gate-to-drain capacitance (Cgd) and gate-to-drain charge (Qgd) are also investigated. It is observed that both Cgd and Qgd decrease as the Wsp increases, owing to the enhanced screen effect. Compared to the SiC double-trench MOSFET device, the optimal SiC NITMOS device exhibits a 79% reduction in Cgd, a 38% decrease in Qgd, and a 41% reduction in Qgd × Ron,sp. A higher switching speed and a lower switching loss can be achieved using the proposed structure.

Design and fabrication of cryogenic multiplexing control chip

This paper presents a design and fabrication process of a cryogenic multiplexing control chip (MCC) for superconducting quantum computers. The working temperature of MCC can be 10 ∼ 30 mK, because it could be integrated with quantum processor in the same package. With a multiplexing ratio of 1:4 and designed working frequency 4–8 GHz, the MCC is a non-reciprocity device which consisted of bandpass filters and isolators, which are based on tunable inductor bridges (TIB). The MCC chip size is 6 × 6 mm2 and includes λ/2 coplanar waveguides resonators, superconducting quantum interference device arrays, capacitors, low pass filters, baluns and bias lines. Adopting self-aligned process of Josephson junctions, the fabrication of MCC constitutes four lithography masks. The modular design of MCC could facilitate the development of large-scale superconducting quantum computers.