Self-aligned Layer Research Articles

Polyimide-free liquid crystal devices with carbon nanotube-based electrodes

A novel type of polyimide-free liquid crystal (LC) device has been fabricated using layer-by-layer (LBL) deposition of carbon nanotube-based electrodes and in situ formation of self-aligning amphiphilic graft copolymer layer. The LBL-processed organic electrodes showed high transparency comparable to indium tin oxide (ITO) and the self-aligned layer of amphiphilic graft copolymer on organic electrodes provided a stable vertical alignment of LCs. Moreover, the proposed LC device resulted in voltage-dependent driving characteristics suitable for display application. This functional organic electrode layer has potential for application in a flexible display to replace conventional ITO electrode and polyimide alignment layer.

Filling Narrow Trenches by Iodine-Catalyzed CVD of Copper and Manganese on Manganese Nitride Barrier/Adhesion Layers

We present a process for the void-free filling of sub-100 nm trenches with copper or copper-manganese alloy by chemical vapor deposition (CVD). Conformally deposited manganese nitride serves as an underlayer that initially chemisorbs iodine. CVD of copper or copper-manganese alloy releases the adsorbed iodine atoms from the surface of the manganese nitride, allowing iodine to act as a surfactant catalyst floating on the surface of the growing copper layer. The iodine increases the growth rate of the copper and manganese by an order of magnitude. As the iodine concentrates near the narrowing bottoms of features, void-free, bottom-up filling of CVD of pure copper or copper-manganese alloy is achieved in trenches narrower than 30 nm with aspect ratios up to at least 5:1. The manganese nitride films also show barrier properties against copper diffusion and enhance adhesion between copper and dielectric insulators. During post-deposition annealing, manganese in the alloy diffuses out from copper through the grain boundaries and forms a self-aligned layer that further improves adhesion and barrier properties at the copper/insulator interface. This process provides nanoscale interconnects for microelectronic devices with higher speeds and longer lifetimes.

Structure and rheology of nanocrystalline cellulose

Sulfate hydrolysis and high-pressure homogenization were combined to reduce the size of microcrystalline cellulose to the nanoscale. The obtained needle-shaped nanocrystals showed a relative uniform size with length of 90±50nm and width of 10±4nm. Rheology and phase transition of the nanocrystal colloids were studied. The flowability and modulus of the colloids showed a strong relationship with frequency, temperature, and concentration of the nanocrystals. Nanocrystals self-assembled into a liquid crystal phase in colloids and even in the dried film. Structure and morphology of the ordered liquid crystalline phase were characterized by scanning electron microscope and polarized optical microscope. It was found that cellulose nanocrystals were self-aligned layer by layer, which was responsible for the color of the dried film and also allowed an ordered layered microporous foam from the freeze-dried nanocrystalline colloids.

Experimental evidence of Si nanocluster δ-layer formation in the vicinity of ion-irradiated SiO2–Si interfaces

Predictions on formation and self-alignment of Si nanocrystals (NCs) at ion-irradiated SiO2–Si interfaces have been verified by cross-section transmission electron microscopy (TEM). The model is based on ion-mixing of SiO2–Si interfaces resulting in a region of SiOx (x<2). During annealing, the interface restores and in the tail of the mixing profile Si excess precipitates and forms a self-aligned layer of Si NCs in SiO2. This Si NC δ-layer structure can hardly be observed by conventional TEM techniques due to the very low mass contrast of tiny Si NCs embedded in SiO2. Here, a contrast enhancing method is presented based on alloying these Si NCs with Ge. For this purpose, a thin Ge layer is embedded into the oxide sufficiently far from the interface mixing range, thus, preventing interference with the Si precipitate formation. During annealing, diffusing Ge monomers attach to the Si NCs, mainly due to the energetically favored Si–Ge bond, resulting in Si1−xGex NCs with an enhanced mass contrast in TEM.

Self-Aligned, Insulating-Layer Structure for Integrated Fabrication of Organic Self-Assembled Multilayer Electronic Devices

We demonstrate an approach for fabricating nanometer-scale devices with minimal device areas while still retaining compatibility with integrated metal wiring. A self-aligned layer of silicon oxide evaporated on top of a thin (25 nm) gold film deposited on a substrate with an etched step ensures that only a fraction of the gold, along the step edge, is exposed. Self-assembled multilayers of 11-mercaptoundecanoic acid (MUA) were grown on the exposed gold to define an arbitrarily long device length. A second, evaporated gold layer served as second electrode. Devices with between 3 and 7 MUA layers were insulating, with currents that decreased exponentially with the number of MUA layers.

Buried, self-aligned barrier layer structures for perovskite-based memory devices comprising Pt or Ir bottom electrodes on silicon-contributing substrates

The integration of noble metal electrodes into semiconductor memory devices incorporating ferroelectric or high dielectric constant ε materials is expected to require deposition of a conductive, oxidation-resistant barrier material between the noble metal and the silicon contact. Described is an alternative type of barrier layer structure which is formed as buried, self-aligned layer during oxygen-ambient annealing after noble metal deposition on silicon-contributing substrates. Reactions of Pt(20 nm) and Ir(20 nm) films with substrates of single crystalline silicon (c-Si), polycrystaline silicon (poly-Si), and tungsten silicide (WSix/Si with x=2.4–2.8) were examined after anneals in atmospheric pressure ambients of oxygen or nitrogen at temperatures of 640–700 °C, a temperature range of interest for high-epsilon materials deposition. While Pt(20 nm) films reacted with silicon and WSix/Si during oxygen annealing to form a mixture of Pt silicides and Pt, Ir(20 nm) films on the same substrates did not form any iridium silicides during oxygen annealing. In all cases, unreacted noble metal M was left due to the formation of an oxygen-containing M–O–Si barrier which interfered with the silicidation reaction. In contrast to these results for oxygen annealing, the Pt and Ir films were completely consumed by silicidation reactions during anneals in nitrogen. Qualitative through-film resistance measurements indicated that the M–O–Si barrier layers formed during oxygen annealing were at least moderately conductive for the cases of M=Ir on silicon and M=Ir or Pt on WSi2.8(300 nm)/Si, a prerequisite for the use of these electrode barrier structures in high-density dynamic random access memory.