Self-aligned Gate Structure Research Articles

Semiconductor quantum point contact fabricated by lithography with an atomic force microscope

We report on the experimental realization of a quantum point contact in a semiconductor heterostructure by lithography with an atomic force microscope (AFM). A thin, homogeneous titanium film on top of the chip surface was patterned by local anodic oxidation, induced by a current applied to an n-doped AFM tip. We demonstrate that self-aligned gate structures in the sub-micron regime can be fabricated with this technique.

Technique for fabricating self-aligned gates onto silicon field emitter arrays

A technique for fabricating self-aligned gate structures onto pre-existing silicon field emitter arrays is introduced in detail in this article. The gate-controlled field emission characteristics of the resulting devices are also described.

Fluorinated Gate Oxide Films Utilized in Polysilicon Thin Film Transistors

ABSTRACTSilicon dioxide films have been grown on polysilicon films at low temperatures in dry ambients by utilizing NF3 - enhanced oxidation, which affords markedly enhanced oxidation kinetics. This facilitates thin film transistor applications, for which low thermal budget processing is essential. The grown oxide films are thicker than corresponding oxides grown on (100) single crystal silicon. Thin film transistors having a polysilicon self-aligned gate structure were fabricated on polycrystalline silicon. The gate oxide films were thermally grown by NF3 -enhanced oxidation at 650°C or 800°C. Electrical characterization of the TFTs having 800°C gate oxides showed on/off current ratios up to 5×107, effective electron mobilities (μneff) of 26 to 38 cm2/Vsec, threshold voltage (VT) values of 0±0.7 V and subthreshold swing (S) values as low as 0.3 V/dec. The devices were stable under dc electrical stressing at a field of 3 MV/cm. Further, the source to drain current activation energy was determined as a function of the gate voltage. The 650°C gate oxide TFTs exhibited on/off current ratio of 105, VT of 3.5 V, Uneffof10 cm2/V.sec and S of 0.7 V/dec.

Refractory and silicide gate metallisations for GaAs MESFET's

Abstract Driven by the need for high device reliability in MESFET power transistors operating at elevated temperatures, and more recently the development of self-aligned gate structures, high stability contacts are being investigated in many laboratories. This paper will consider two classes of metallisations that have proved very promising. These include the refractory metals such as W, Ta and Ti together with the refractory silicides such as TaSi x TiSi x and WSi x . The work carried out in this area will be reviewed and appraised. The basic interface has been characterised by the use of RBS and SIMS studies. More recent studies have been concerned with the use of these results in the fabrication and evaluation of transistor structures.

Orientation and ion-implanted transverse effects in self-aligned GaAs MESFET's

The orientation dependence of the threshold voltage and device transconductance of ion-implanted GaAs FET's has been investigated and modeled. The threshold voltages of the devices along the [011] and [01 \bar{1} ] directions are different when the gate length is short (≤ 3 µm). Experimental results and theoretical calculations show that this is primarily due to the strain in the active channel, induced by the dielectric overlayer. For the short self-aligned gate structure, the lateral spread of the ion-implanted n+layer is important as well. When these two effects are taken into account, calculated results agree well with the experimental data for standard self-aligned gate structures, and self-aligned structures with a sidewall or T-gate, fabricated using lamp- or furnace-annealing processes. This model also allows us to simulate the threshold voltage and transconductance dependence on the annealing time for different device parameters (such as gate length and channel doping)and process variables (i.e., sidewall or T-gate dimensions and impurity diffusion constant). We also calculated the gate length dependence of the transconductance for devices fabricated using a sidewall process. Results of this calculation are compared with the experimental data for different sidewall thicknesses.

Ultrahigh speed high electron mobility transistor large scale integration technology

Current status and recent advances in high electron mobility transistor (HEMT) technology for high performance very large scale integration (VLSI) are presented with the focus on material, self-alignment device fabrication, and HEMT large-scale integration (LSI) implementations. HEMT is a very promising device for ultrahigh speed LSI/VLSI due to the supermobility GaAs/AlGaAs heterojunction structure. The technological challenges for large scale integrations are discussed with refined HEMT with self-aligned gate structure, controllability of device parameters, and molecular beam epitaxy material problems. Master–slave flip–flop, divide-by-two circuits achieved the internal logic delay of 22 ps per gate at 77 K at a fan-out of about 2, roughly three times faster than that of GaAs metal-semiconductor field-effect transistor technology. HEMT has already made it possible to develop 16 kb static random access memory (RAM) and a 1.5-kgate gate array, demonstrating high speed LSI operations. With submicron gates, as well as advanced material technologies, a HEMT 64 kb static RAM with subnanosecond access operation and 10 kgate logic LSI with sub-100-ps logic delays, will be achieved.

Recent advances inultra-high-speed HEMT technology

Current status and recent advances in high electron mobility transistor (HEMT) technology for high-performance VLSI are presented with a focus on material, self-alignment device fabrication, and HEMT LSI implementations. HEMT is a very promising device for ultra-high-speed LSI/VLSI due to the supermobility GaAs/AlGaAs heterojunction structure. The technological challenges for large-scale integration are discussed with the refined HEMT with self-aligned gate structure, controllability of device parameters, and MBE material problems. Master-slave flip-flop divide-by-two circuits achieved an internal logic delay of 22 ps per gate at 77 K at a fan-out of about 2, roughly three times faster than that of GaAs MESFET technology. HEMT has already made it possible to develop a 4 kbit static RAM's and 1.5 kgate gate array, demonstrating high-speed operations. With submicron gates, as well as advanced material technologies, a HEMT 64 kbit static RAM with subnanosecond access operation and 10 kgate logic LSI with subhundred-picosecond logic delays will be achieved.

IBM multichip multilayer ceramic modules for LSI chips—design for performance and density : Bernard T. Clark and Yates M. Hill. IEEE Trans. Components, Hybrids Mfg Technology. Chmt-3, (1) 89 (March 1980)

Driven by the need for high device reliability in MESFET power transistors operating at elevated temperatures, and more recently the development of self-aligned gate structures, high stability contacts are being investigated in many laboratories. This paper will consider two classes of metallisations that have proved very promising. These include the refractory metals such as W, Ta and Ti together with the refractory silicides such as TaSix TiSix and WSix. The work carried out in this area will be reviewed and appraised. The basic interface has been characterised by the use of RBS and SIMS studies. More recent studies have been concerned with the use of these results in the fabrication and evaluation of transistor structures.

Fabrication of Integrated CMOS Transistors using Electron Lithography and Ion Implantation

Electron lithography and ion implantation have been used in the fabrication of integrated complementary P-channel and N-channel transistors. A digitally controlled single electron beam system, the Electron Micropattern Generator, aligned and exposed the eight mask levels required. The cumulative alignment tolerance was 3 μ. Fabricated devices had channel lengths of 1, 2, and 6 μ, and drain-source breakdown voltages of − 22 and + 12 V for the P- and N-type, respectively. Ion implantation was used to produce self-aligned gate structures by extending the diffused source and drain contact regions to the gate edges. The implantation masks consisted of 3000 Å aluminum and 7700 Å PMM resist. Boron and phosphorus ions were implanted at 50 and 100 keV, respectively at dosages ranging from 1×1014 to 1×1015 ions/cm2. Sintering and annealing operations were performed at 500 °C for 10 min in N2 atmosphere. Sheet resistances ranged from 2700 to 1000 Ω/□ for implanted boron and 700−240 Ω/□ for the phosphorus. Evolving high-density circuits require shallow P-well junctions (≈ 2.7μ) and contact regions (≈ 0.7μ) in N-type 〈100〉 oriented silicon of 0.35 Ω-cm resistivity. Evaluation of the transistors showed enhancement mode operation with VTP=−4.8 V and VTN=+1.4 V using a gate dielectric structure consisting of CVD sandwich layers of 125 Å SiO2 plus 750 Å Si3N4, yielding average surface state density of 6×1011 charges/cm2. Evaluation of diffused and implanted transistors, as well as resistors, will be discussed.

Ion-implanted MOS technology

Abstract This paper discusses the current state of ion-implantation as applied to MOS technology. It is shown how impurity doping by ion-implantation is used to produce self-aligned MOS gate structures. The reduction in circuit capacitance gives the designer a choice of higher switching speed or lower power dissipation. The availability of a linear resistor of value 1–10 kω/□ allows many new circuit techniques to be applied to monolithic circuits. This paper discusses ion-implantation technology, device design, and circuit performance. A number of implanted circuits are shown. Finally, improvements to the present technology which are still in the R & D phase are described.

Silicon-gate technology

Silicon-gate technology provides an advantageous approach for implementing large-scale integrated arrays of field-effect transistors. Its advantages-principally resulting from the low threshold voltage and the self-aligned gate structure buried under an insulator-ease the problem of interfacing these circuits to bipolar integrated circuits and increase both their performance and functional density, making MOS integrated circuits easier and more economical to use. This article reviews recent progress with this technology and shows its application to the construction of complex digital functions as illustrated by a memory circuit.

Insulated gate field effect transistor integrated circuits with silicon gates

The Silicon Gate Technology is a new approach to fabricating insulated gate field effect transistor circuits, in which the metal gate electrode is replaced by a doped, silicon electrode. The work function difference between the gate electrode and semiconductor bulk will now be determined by the doping of the gate electrode. This leads to normally off p-channel devices with threshold voltages typically between 1.1 v and 2.5 v on material with 1000A gate oxide. It is a self-aligned gate structure and has a buried-gate electrode which allows crossover of gate regions and closer spacing of source-drain contact. The fabrication needs 4 masking steps and was found to be compatible with existing planar technology.

SB-IGFET, II: An ion implanted IGFET using Schottky barriers

Insulated-gate field-effect transistors have been made, which combine the advantages inherent to Schottky barrier source and drain electrodes with ion implantation. This device has a self-aligned gate structure achieved by using the thick gate electrode as a mask during the ion implantation process.