Selective Wet Etching Research Articles

Ge0.75Sn0.25 on insulator metal-semiconductor-metal photodetector by layer transfer technique

Abstract The Ge0.75Sn0.25 alloy, which is lattice matched to the InP, has the potential to create a high-quality GeSn-on-insulator (GeSnOI) structure for group IV optoelectronic devices. A Ge0.75Sn0.25OI metal-semiconductor-metal (MSM) photodetector was fabricated through the layer transfer technique using DiVinyl Siloxane bis-Benzocyclobuten (DVS-BCB) polymer as an adhesive and highly selective wet etching of InP substrate over GeSn, Si, SiO2 and DVS-BCB. The photoresponse of the Ge0.75Sn0.25OI MSM photodetector at a wavelength of 1550 nm was evaluated using a modulated laser and lock-in method, achieving a responsivity and a noise equivalent power (NEP) of ∼3 × 10−6 A W−1 and ∼1 × 10−6 W/Hz0.5, respectively. The thermal budget for fabricating Ge0.75Sn0.25OI MSM photodetector is below 220 °C, which is compatible with conventional Si back-end-of-the-line (BEOL) processing toward three-dimensional (3D) heterogeneous-integrated devices.

Micro Coriolis Mass Flow Sensor with Large Channel Diameter Realized by HNA Wet Etching.

This paper introduces a Coriolis mass flow and density sensor. The sensor is made using Surface Channel Technology (SCT) but with selective wet etching to create the channels. This method forms suspended microfluidic channels with a larger cross-sectional area. Because of this larger cross-sectional area, the sensor has a much higher flow range, up to 50 g h-1 (for water) with a pressure drop of 1 bar, compared to the standard SCT-based Coriolis sensor, which is only 1.2 g h-1. The channel has a semi-elliptical cross-sectional area, measuring 200 micrometers wide and 70 micrometers deep. The channel wall is made of a stack of thin films with a total thickness of 2.5 μm. Water, isopropyl alcohol (IPA), and nitrogen (N2) are used to test and evaluate the sensor's mass flow and density sensing performance.

Controlled Surface Polarity and Crystallinity of Gallium Nitride on Si (111) Using Atomic Layer Deposition for Selective Wet-Etch and STEM Analysis

Gallium nitride (GaN) has gained interest as photoelectronic materials and a buffer layer for other III-V deposition with applications in power electronics operated at high voltage and high temperature. The crystallinity and polarity of III-V semiconductors have a key role for the passivation layers on microLED, the formation of 2D electron gasses in high electron mobility transistors, and for templating growth of piezoelectric materials. The atomic layer annealing (ALA) was reported to improve the crystallinity of the III-V compounds (aluminum nitride) at low temperatures as compared to the conventional thermal ALD. In ALA, a pulse of ion bombardment is added to each ALD cycle to ensure polycrystalline film formation at low temperature. Polycrystalline GaN has been deposited by ALA at low temperatures even on amorphous substrates, but the polarity was not reported. The selective wet-etch process has several advantages for the III-V semiconductor device integration since the conventional plasma ion etching process is expensive, complicated, and leads to the surface damage by reactive plasma ion. The GaN surface polarity (N-polar or metal-polar) on sapphire was selectively etched by aqueous KOH solution. However, electrochemical etching study on the polarity of GaN ALD films has not yet been studied as types of ALD process. Figure 1a and 1b show the process parameter switching diagram for the GaN thermal ALD and GaN ALA processes, respectively. The chemical compositions of ALA and ALD GaN on Si were estimated by in-situ AES as shown in Figure 1c. Lower O content (below 3.3 at. %) and higher N/Ga atomic ratio were observed in the ALA GaN on Si (111) as compared to the thermal ALD GaN film (4.6 at. %). Figure 1d shows that the intensity of GaN (002) XRD pattern in thermal ALD GaN on Si was greatly improved in the GaN stacks (GaN thermal ALD/ALA/Si) with an ALA GaN buffer layer. The electrochemical behavior of the GaN ALD films was studied to elucidate the impact of surface polarity on selective KOH wet-etch. The linear sweep voltammograms of GaN thermal ALD and GaN ALA films in 1 M KOH solution were shown in Figure 1e. The applied potential was swept from zero (vs. Normal Hydrogen Electrode) to positive 3.7 V. The peak of current density at ~1.7 V was observed in the voltammogram of the GaN ALA film (N-polar), suggesting the occurrence of etching reaction by the dissolution and formation via the equations in Figure 1f. On the other hand, the absence of current density peak in the GaN thermal ALD film (Ga-polar) could suggest the unfavorable etching reaction as compared to the GaN ALA film. Figure 2a and 2b shows the HAADF-STEM images of ALD GaN on Si demonstrate highly ordered 3 nm x 5 nm ALD GaN layers with bright and dark regions. The circles of bright regions and the center of dark regions represent Ga atoms and tunnel points (empty element), respectively. The GaN polarity could be determined by drawing triangles connecting adjacent three tunnel points without the interruption of Ga. Using this method, upward triangles were obtained in the HAADF-STEM image (Figure 2a), suggesting the formation of N-polar GaN layers during the ALA GaN process on Si. Conversely, downward triangles from the STEM image of thermal ALD GaN /ALA GaN /Si (Figure 2b) suggested Ga-polar GaN during GaN thermal ALD process. The inset figures show the top-view SEM image of selectively wet-etched (30 min, 20 wt.% KOH (aq)) GaN films. The etched surface on the ALA GaN layers (inset of Figure 2a) indicated N-polar GaN surface. The inset SEM image in Figure 2b shows a nearly unchanged GaN surface in thermal ALD GaN /ALA GaN / Si is consistent with the Ga-polar GaN surface. These observations are in good agreement with the HAADF-STEM images.The data is consistent with being able to control the polarity of GaN by switching between thermal ALD and ALA. The ion bombardment in ALA promotes N-polar GaN while thermal ALD promotes metal polar GaN. This allows the facile formation of both electron and hole gas layers between ALA and ALD GaN. Figure 1

Notched Gate and Graded Gate Oxide Processing for Reduced Capacitance Application in RF MOSFETs

As the demands of RF applications are rising, optimization of internal MOSFETs capacitances is a key issue to improve the cut-off frequency. In this abstract we report the development of a novel N-MOS architecture processed on 8-inch SOI wafers. This architecture has a gate oxide with variable thickness along the channel and a reduced bottom gate length aiming at minimizing Gate to Drain/Source capacitance (1) (2). This improvement on Gate to Drain/Source capacitance mainly comes from a decrease in overlap capacitances as described in (3).The new process flow is composed as usual until Poly-Si gate etching. By controlling the species flow and process time during plasma etching steps, over etch at the bottom of the gate is performed (fig.1(a,b)). Poly-Si gate notching engineering is possible due to reduction of the passivation layer thickness at the bottom of the gate during plasma etch. As described in (4) the gate is first etched using a HBr/CL2/O2 chemistry until reaching close to the bottom of the gate, allowing the formation of a passivation layer made of SiOxCly and the anisotropy of the etch. To etch the remaining thickness HBr flow is augmented while CL2 and O2 flow are reduced, preventing formation of passivation layer. This leads to isotropic etch of the bottom gate and reduction of the gate length as regard to the top Poly-Si dimension. This over-etch reduces the physical gate length without changing the effective and the on-mask gate lengths, leading to overlap capacitance reduction.To produce gate oxide with variable thickness under gate sidewalls a two-steps process is performed. First, full plate oxide is grown before poly-Si deposition to act as middle gate thickness. Then undercut is performed, consisting of lateral etching of the gate oxide under gate sidewall after gate etch (fig.2.a). To achieve this undercut, hydrofluoric acid (HF) wet etch has been chosen. First trials with very low HF concentration become quickly saturated leading to small lengths under gate sidewalls (fig.2.b). Then more acidic solutions were used allowing satisfying undercut lengths (fig.2.c).Finally rapid thermal oxidation (RTO) is performed to obtain an oxide bird beak at both gate side as both Poly-Si gate and Si from the active region react with ambient O2 in the chamber. This leads to a gate oxide with variable thickness along the channel (fig.3(a.b)) which has both effects: to get smoother poly-Si foot and a down step in the active between channel and Source/Drain regions. During this process step, a built-in spacer on the gate sides for LDD implantation is formed. RTO process step has grown a thicker oxide over Source/Drain areas which has to be reduced to allow an accurate LDD implantation, this is done by anisotropic etching. After these new steps, the process goes back to a standard N-MOS process flow.Some early versions of the notched gate have been investigated (5), and these experiments and details on processing recipe seem promising for electrical results. As poly-Si foot has been smoothed and graded gate oxide (GGO) on top of overlaps region is formed. It would allow a reduction in parasitic capacitances improving cut-off frequency of RF applications.References RF LDMOSFET with Graded Gate Structure. Xu Shuming, Foo Pan Dow. Toronto : s.n., 2001. 1th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings. pp. 221-224. DOI:10.1109. Notched-Gate pMOSFET with ALD TiN/High-κ Gate Stack Formed by Selective Wet Etching. Zhang, D. Wu and J. Lu and P.-E. Hellström and M. Östling and S.-L. s.l. : The Electrochemical Society, Inc., 2004, Electrochemical and Solid-State Letters, Vol. 7, p. 228. 10.1149/1.1795612. A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs. Fabien Pregaldiny, Christophe Lallement,Daniel Mathiot. s.l. : Solid State Electronics, 2002, Vol. 46, pp. 2191–2198. https://doi.org/10.1016/S0038-1101(02)00248-4. Design of notched gate processes in high density plasmas. J. Foucher, G. Cunge, L. Vallier, and O. Joubert. s.l. : AVS: Science & Technology of Materials, Interfaces, and Processing, 2002, Vols. Journal of Vacuum Science & Technology B 20,. http://dx.doi.org/10.1116/1.1505959. Notched gate MOSFET for capacitance reduction in RF SOI technology. al, L. Antunes et. s.l. : 2023 IEEE International Conference on Design, Test and Technology of Integrated Systems (DTTIS), 2023. doi: 10.1109/DTTIS59576.2023.10348288. Figure 1

Effect of Polymer Type Additives in Selective Wet Etching of Si1-XGex- to Si-Film to Enhance Etch Rate Selectivity

To extend the scalability of the logic transistor beyond the 3-nm process, the architecture of the metal-oxide-semiconductor field-effect transistor (MOSFET) has changed from FinFET to gate-all-around FET (GAAFET). In addition, to continue the scaling of MOSFET further, various concepts of nanosheet architecture devices, including GAAFET, Forksheet FET, and Complementary FET, have been vigorously researched. To fabricate nanosheet devices, releasing Si channels via selective etching of Si1-xGex- to Si-layer is a key process. However, during the selective etching of Si1-xGex- to Si-layer, simultaneous etching of Si- with Si1-xGex-layer is inevitable. Therefore, protecting the Si-layer while selective etching of the Si1-xGex-layer is a major challenge to acquire uniform channel layers (i.e., Si-layers). In this study, to protect the Si-layer during the selective wet etching of Si1-xGex- to Si-film, we came up with an idea based on the concept of selective chemisorption of polymers on Si- rather on Si1-xGex-film. Functional groups of polymers can chemisorb onto the Si surface, followed by building the hindrance layer that prohibits the etching of Si-film. Thus, we tested the effect of polymer type additives in selective wet etching of Si1-xGex- to Si-film depending on the functional groups (carboxylic group, amine group, alcohol group, etc.) and the molecular weight. To characterize the etching amount of the Si-film during the selective wet etching of Si1-xGex- to Si-film, the wet etching of epitaxially grown 3-periods of Si1-xGex/Si multilayer on Si substrate was performed followed by high-resolution transmission electron microscopy (HR-TEM) analysis. When using a specific type of polymer additive during wet etching, the etching amount of Si-film was >0.5 nm within 2 minutes, while that using without any additive was ~0.8 nm within 2 minutes, indicating that polymer type additive can produce the hindrance layer successfully onto Si-film preventing the etching of Si-film. The HR-TEM images depending on polymer types and mechanism of protecting Si-film during the selective wet etching of Si1-xGex- to Si-film will be presented in detail. Acknowledgement This work was supported by the Technology Innovation Program (20022475, Development of wet Etchant capable of high selection etching in microprocesses below 10 nm) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea) References [1] Lee, Seung-Jae, et al. "Extremely high selective Si1−xGex-film wet etchant generating highly dissolved oxygen via peracetic acid oxidant for lateral gate-all-around FETs with a logic node of less than 3-nm." Chemical Engineering Journal 475 (2023): 146257.

(Invited) Selective Wet Etching of Semiconductor Materials by Novel Catalyst-assisted Modes

Metal-assisted chemical etching (MaCE) is an emerging technology in the formation of semiconductor surfaces with various structures and functions [1, 2]. In general, precious metals such as Pt and Ag are used as catalysts in this etching mode. By controlling solution conditions, a semiconductor surface in contact with a catalyst can be etched selectively. Because this etching utilizes chemical reactions, it does not leave mechanical damages on a processed surface. So far, our group reported the application of this etching mode for local patterning and surface flattening of Ge and SiC surfaces [3, 4]. In this paper, we present two recent topics on this mode.One is the development of “chemical knife” to separate neighboring terraces on a Si surface. We aim at forming ultrathin Si ribbons from a silicon-on-insulator (SOI) layer possessing a vicinal surface by total wet chemical processing. To test this concept, we used a p-type Si(111) sample of which surface is misoriented in the <11-2> direction at an angle of 0.2°. After wet cleaning, it was immersed in water with an ultralow level of dissolved O2 molecules less than 2 ppb, which is referred to as the first LOW (Low dissolved-Oxygen Water) treatment. The first LOW treatment formed a Si(111) surface composed of flat terraces and biatomic steps. Then it was immersed in LOW containing Ag+ ions at a concentration of 5 ppm, which is referred to as the second LOW treatment. We have found that Ag atoms were selectively reduced at the edges of atomic steps on Si(111) to form Ag nanowires, as reported by another group [5]. Finally, the Si sample with Ag nanowires was immersed into a mixture of HF and H2O2. We found that the self-assembled Ag nanowires after the second LOW treatment were replaced by almost continuous nano trenches [6]. This is probably because the Ag nanowires acted as a catalyst to enhance chemical etching of the Si surface underneath. By applying this sequence for a thin SOI layer, we expect to form Si ribbons of which width and thickness are both controlled in a self-assembled manner.The other topic is graphene-based catalysts to enhance etching of a Ge surface just in water. A problem with conventional MaCE is the use of noble metals as catalysts. In most applications, residual metals on the semiconductor surface have to be removed after MaCE. For example, aqua regia is effective for dissolving Pt. However, such a strong oxidative solution causes severe damage to the surfaces of some semiconductor materials such as Ge. To solve this issue, graphene can be used as a substitute for noble metals. Another group has reported graphene-assisted chemical etching of Si with chemical-vapor-deposition-grown graphene as a catalyst [7]. Recently, we reduced a commercial graphene oxide (GO) solution by several synthesis methods to obtain a black suspension including reduced GO (rGO) sheets. Then we found that enhanced etching occurred on a Ge surface covered by the chemically modified rGO sheets in O2-dissolved water [8, 9]. This is probably because the rGO sheets catalyze Ge oxidation underneath the sheets. We propose that this reaction is triggered by the adsorption of O2 molecules in water at local defects in the sheets. As investigated in our surface science studies by scanning probe techniques [10] and first-principles simulations [11], both a finite-sized and chemically modified graphene exhibit electronic structures different from those of a simple and large graphene sheet. This indicates that the control of local defects and their density in an rGO sheet is a key in realizing rGO-assisted chemical etching with a higher performance. Finally, we show a result combining this metal-free etching mode with a lithography process to fabricate a trench pattern on Ge.[1] Z.P. Huang et al., Adv. Mater. 23, 285 (2011).[2] X. Li et al., Curr. Opin. Solid State Mater. Sci. 16, 71 (2012).[3] K. Arima et al., J. Phys.: Condens. Matter 23, 394202 (2011).[4] T. Kawase, K. Arima et al., Nanoscale Res. Lett. 8, 151 (2013).[5] N. Tokuda et al., J. Phys. Chem. B 109, 12655 (2005).[6] Z. Ma, K. Arima et al., Langmuir 38, 3748 (2022).[7] J. Kim et al., ACS Appl. Mater. Interfaces, 7, 24242 (2015).[8] T. Hirano, K. Arima et al., Carbon 127, 681 (2018).[9] R. Mikurino, K. Arima et al., J. Phys. Chem. C 124, 6121 (2020).[10] J. Li, K. Arima et al., Phys. Rev. B 103, 245433 (2021).[11] J. Li, K. Arima et al., Phys. Rev. Res. 6, 013252 (2024).

Electrostatically Tunable PN Junction in 1L-MoTe2 Formed By Gold-Mediated Exfoliation

Atomically thin layered materials have attracted great research interests owing to exciton formation at room temperature based on extraordinarily large binding energy. In particular, a semiconducting molybdenum ditelluride (MoTe2) emits photons in the near-infrared region around 1.1 eV, which is the photon energy applicable to optical telecommunication. So far, various optoelectronic devices such as circularly polarized light emitting diodes and lasers are developed by utilizing Mo-based transition metal dichalcogenides. Recently, it has been reported that gold-mediated exfoliation technique enables to form large-area MoTe2 monolayer. In this study, we focus on electrostatic carrier density modulation in the large-area 1L-MoTe2 formed by gold-mediated exfoliation technique and demonstrate that the fabricated large-area 1L-MoTe2 has a high potential for developing optoelectronic devices such as light emitting diodes.Schematic diagram of the device structure is shown in Fig. 1(a). First, MoTe2 multilayers were mechanically exfoliated by scotch tape, and gold was deposited onto the MoTe2 multilayers by thermal evaporation. Then, the gold film together with the topmost layer of the MoTe2 multilayers was peeled off by using a thermal release tape owing to the stronger interaction of the topmost layer with the evaporated gold compared to the van der Waals interactions in the MoTe2 bulk crystals. The 1L-MoTe2/gold structures on the thermal release tape were transferred to a 290-nm-thick SiO2/Si substrate, and selective wet etching of the surface gold film was performed with a KI/I2 mixed solution. Graphite and hBN flakes were prepared on a polydimethylsiloxane (PDMS), and these flakes were successively stacked on the 1L-MoTe2 using the standard dry transfer process for utilization as electrodes to measure the electrical properties and as a cap layer, respectively. Finally, we deposited Ni/Au top gate electrodes on the hBN/1L-MoTe2 by a lift-off process, which are separated by 8 μm.Figure 1(b) shows the current-voltage (I D–V BG) curves obtained by applying top gate voltages of V TG1 = V TG2 = 0 V. An increase in drain current I D is seen by increasing back-gate voltage V g for both positive and negative polarities in the 1L-MoTe2 channel, showing the ambipolar behavior. Figure 1(c) plots the value of drain current I D as a function of top gate voltages V TG1 and V TG2 at fixed voltages of V BG = 20 V and V D = 2 V. Considering that the positive voltage of 20 V is applied to the Si back gate electrode, the carrier type of the 1L-MoTe2 area between top gate electrodes becomes n-type. Furthermore, we can tune the local carrier densities in the 1L-MoTe2 areas below the top gate electrodes by the gate bias tuning, and thus the four corners of the figure correspond to P/N/N+, N+/N/N+, N+/N/P, and P/N/P configurations. For P/N/N+ and N+/N/P configurations, the I D-V D curves show rectification behavior with the on/off ratio around 103. Additionally, we found the typical current amplification by modulating the Si back gate voltage for the P/N/P configuration. These results demonstrate the versatility of the 1L-MoTe2 device to functionality as a PN junction and an electrostatically controlled transistor. Figure 1

Fabrication of uniform, periodic arrays of exotic AlN nanoholes by combining dry etching and hot selective wet etching, accessing geometries unrealisable from wet etching of planar AlN

Aluminium nitride (AlN) is a wide bandgap semiconductor with far reaching realised and potential applications in electronics and optoelectronic technology. For example, gallium nitride (GaN) quantum dots (QDs) housed within an AlN matrix are attractive due to the large bandgap offsets. However, making suitable AlN sites to house GaN QDs is challenging due to the difficulty in fashioning 3D AlN structures. This results from AlN's strong bonds that are difficult to chemically etch.Whilst dry etching of AlN nanostructures has been explored, wet etching at the nanoscale has been limited by the common exposed facet of AlN being etch-resistant. Hence, wet etching of AlN to create uniform arrays of periodic nanohole nanostructures has, thus far, not been heavily explored.In this paper, an initial dry etching of a 2D AlN planar template is used to expose alternative wet-etchable facets so that periodic arrays of nanohole structures are revealed by wet-etching. Both a study of different initial dry etched structures, including tapered nanoholes, and wet etching time were performed. A model to describe the dynamics of wet etching on the different dry etched nanohole structures is proposed. Periodic arrays of uniform nanohole features are realised that hold promise for applications such as the housing of site-controlled quantum dots.

(Invited) Selective Wet Etching of Semiconductor Materials by Novel Catalyst-assisted Modes

Since reports in the mid-1990s on metal-induced pitting on a Si surface in microelectronics, much attention has been paid to the positive use of corrosion of a semiconductor surface loaded with a metallic catalyst in solutions, known as metal-assisted chemical etching. This paper describes two novel modes of catalyst-assisted etching. The first involves the formation of nano trenches along the atomic step edges of a Si(111) surface with the help of self-assembled metallic nanowires, enabling the separation of neighboring terraces. The second discusses the science and application of nanocarbon-assisted etching, free from noble metals, of a Ge surface in water.

Microstructural Passivation of Patterned Al2O3 Back Contacts on CdS/CdTe Solar Cells

AbstractPatterned aluminum oxide (Al2O3) back contact on cadmium telluride (CdTe) solar cells can effectively mitigate the loss of the majority carriers while retaining the passivation benefits for minority carriers. This study investigates the impact of the point‐contact geometry on cell performance, where the spacing of the microholes is systematically varied at a constant microhole diameter (≈16 µm). Microhole arrays are created on an evaporated Al2O3 layer (≈30 nm) on CdTe using laser‐beam lithography and selective wet etching processes. Comparative analysis indicates a significant decrease in fill factor (FF) and short‐circuit current (ISC) when the contact fraction falls below 30%, likely due to the Al2O3 barrier impeding majority carriers. Above this fraction, FF and ISC are comparable to those of baseline CdTe cells without Al2O3. Open‐circuit voltage (VOC) shows a gradual decrease as Al2O3 coverage is reduced but exhibits a slight increase (&lt;15 mV) when the contact fraction exceeds 30%. Cathodoluminescence (CL) characterization reveals that significantly improved radiative recombination occurs within the CdTe grain bulk with Al2O3, whereas this effect on grain boundaries is minimal. The findings imply complex local carrier dynamics in the patterned back‐contact region, closely tied to the microstructural properties of CdTe‐based solar cells.

Deposition of CdSe Nanocrystals in Highly Porous SiO2 Matrices-In Situ Growth vs. Infiltration Methods.

Embedding quantum dots into porous matrices is a very beneficial approach for generating hybrid nanostructures with unique properties. In this contribution we explore strategies to dope nanoporous SiO2 thin films made by atomic layer deposition and selective wet chemical etching with precise control over pore size with CdSe quantum dots. Two distinct strategies were employed for quantum dot deposition: in situ growth of CdSe nanocrystals within the porous matrix via successive ionic layer adsorption reaction, and infiltration of pre-synthesized quantum dots. To address the impact of pore size, layers with 10 nm and 30 nm maximum pore diameter were used as the matrix. Our results show that though small pores are potentially accessible for the in situ approach, this strategy lacks controllability over the nanocrystal quality and size distribution. To dope layers with high-quality quantum dots with well-defined size distribution and optical properties, infiltration of preformed quantum dots is much more promising. It was observed that due to higher pore volume, 30 nm porous silica shows higher loading after treatment than the 10 nm porous silica matrix. This can be related to a better accessibility of the pores with higher pore size. The amount of infiltrated quantum dots can be influenced via drop-casting of additional solvents on a pre-drop-casted porous matrix as well as via varying the soaking time of a porous matrix in a quantum dot solution. Luminescent quantum dots deposited via this strategy keep their luminescent properties, and the resulting thin films with immobilized quantum dots are suited for integration into optoelectronic devices.

Wide-range angle sensing based on mixed variable line spacing gratings

Variable line spacing (VLS) gratings are core components in spatial spectrum and synchrotron radiation facilities due to their merits of self-focusing, aberration correction, and flat focal field. However, optimal design and fabrication of VLS gratings are still required for matching various applications. Scratch-induced selective wet etching has been proven as a robust way for fabricating various nanostructures because of its simplicity, flexibility, and controllability. In this paper, we proposed convenient and maskless methods to fabricate VLS grating based on scratch-induced selective wet etching. During the etching, key factors, including normal load for the scratching, etching time, and types of etchants, were investigated systematically toward optimizing the process. The shapes including sidewall angle and the bottom curvature of the grating elements can be controlled by adjusting the normal load, etching time and/or etching etchants. It is found that the VLS gratings present a wide-range sensing for angle detection based on the reflection spectrum. Furthermore, combining transferring process, the VLS master gratings could be replicated on polydimethylsiloxane (PDMS) surface, which showed great optical performance. This work opened new light to some extent for the application of angle sensing and structural color showing.

Coral-shaped AlSi anode materials for Li-ion batteries enabled by THF-based electrolyte

This research aims to implement a strategy of using a controlled acidic etching on AlSi alloy particles to partially remove Al and preserve a porous Si framework as anode materials. The etched AlSi materials with different Al/Si weight ratios have been investigated in lithium-ion batteries. Microstructural analysis shows the evolution of the AlSi material during selective wet etching, highlighting the preservation of coral-shaped Si nanostructures with an Al-rich core. Lower Al/Si ratios result in increased surface area and pore volume, which is favorable for improving lithium-ion diffusion and accommodating volume expansion during cycling. Evaluation of electrochemical performance in different electrolytes proves the importance of electrolyte selection for AlSi anodes. The tetrahydrofuran-based (THF-based) electrolyte stabilizes electrochemical reactions, resulting in superior specific capacity, cycle life, and Coulombic efficiency compared to the carbonate-based electrolyte with fluoroethylene carbonate additive. Rate performance analysis shows excellent high-rate capability with stable capacity retention at 3C, particularly in Al53Si47 and Al10Si90 materials. Electrochemical impedance spectroscopy measurements emphasize the critical role of porous structure and electrolytes in sustaining low resistance and enhancing cycle life performance. Selective aluminum etching and the THF-based electrolyte effectively mitigate the breakdown and subsequent reformation of the solid electrolyte interphase, resulting in superior efficiency and extended lifespan.

Unveiling polycrystalline silicon channel dissolution mechanism in wet etching process of 3D NAND fabrication

3D NAND is one of the most promising storage devices due to its high storage density and low energy consumption. Selective wet etching of Si3N4 by hot-concentrated phosphoric acid (PA) solution is a key process for 3D NAND fabrication. However, the channel material, polycrystalline silicon (poly-Si), is unexpectedly dissolved due to its inevitable exposure to the PA etching solution, which causes device failure and thus limits the stacking density of 3D NAND. Herein, to avoid the detrimental dissolution of poly-Si, we unveil the mechanism of poly-Si dissolution in PA solution from kinetic and thermodynamic perspectives. We find that the etch process shows a two-stage reaction, in which H2O plays a key role in lowering the activation barrier for poly-Si etching. Further thermodynamic analysis demonstrates that poly-Si prefers to be oxidized by H2O to suboxide rather than to SiO2. Combined with surface chemistry characterization, we propose the dissolution mechanism as a two-stage process involving the dissolution of suboxide interface and bulk poly-Si, where the nucleophilic substitution of Si–H with Si–OH on bulk poly-Si surface determines the overall etch rate. This study advances the 3D NAND development by establishing a theoretical foundation for identifying and implementing efficacious strategies to impede detrimental dissolution.

Demonstration of HCl-Based Selective Wet Etching for N-Polar GaN with 42:1 Selectivity to Al0.24Ga0.76N

A wet-etching technique based on a mixture of hydrochloric (HCl) and nitric (HNO3) acids is introduced, demonstrating exceptional 42:1 selectivity for etching N-polar GaN over Al0.24Ga0.76N. In the absence of an AlGaN etch stop layer, the etchant primarily targets N-polar unintentionally doped (UID) GaN, indicating its potential as a suitable replacement for selective dry etches in the fabrication of GaN high-electron-mobility transistors (HEMTs). The efficacy and selectivity of this etchant were confirmed through its application to a gate recess module of a deep-recess HEMT, where, despite a 228% over-etch, the 2.6 nm AlGaN etch stop layer remained intact. We also evaluated the proposed method for the selective etching of the GaN cap in the n+ regrowth process, achieving a contact resistance matching that of a BCl3/SF6 ICP process. These findings underscore the applicability and versatility of the etchant in both the electronic and photonic domains and are particularly applicable to the development of N-polar deep-recess HEMTs.

Single-Crystal Silicon Nanotubes, Hollow Nanocones, and Branched Nanotube Networks.

We report a general approach for the synthesis of single-crystal silicon nanotubes, involving epitaxial deposition of silicon shells on germanium nanowire templates followed by removal of the germanium template by selective wet etching. By exploiting advances in the synthesis of germanium nanowires, we were able to rationally tune the nanotube internal diameters (5-80 nm), wall thicknesses (3-12 nm), and taper angles (0-9°) and additionally demonstrated branched silicon nanotube networks. Field effect transistors fabricated from p-type nanotubes exhibited a strong gate effect, and fluid transport experiments demonstrated that small molecules could be electrophoretically driven through the nanotubes. These results demonstrate the suitability of silicon nanotubes for the design of nanoelectrofluidic devices.

High-temperature annealing of ( ) β-Ga2O3 substrates for reducing structural defects after diamond sawing

A commercial epi-ready ( ) β-Ga2O3 wafer was investigated upon diamond sawing into pieces measuring 2.5 × 3 mm2. The defect structure and crystallinity in the cut samples has been studied by X-ray diffraction and a selective wet etching technique. The density of defects was estimated from the average value of etch pits calculated, including near-edge regions, and was obtained close to 109 cm−2. Blocks with lattice orientation deviated by angles of 1−3 arcmin, as well as non-stoichiometric fractions with a relative strain about (1.0−1.5) × 10−4 in the [ ] direction, were found. Crystal perfection was shown to decrease significantly towards the cutting lines of the samples. To reduce the number of structural defects and increase the crystal perfection of the samples via increasing defect motion mobility, the thermal annealing was employed. Polygonization and formation of a mosaic structure coupled with dislocation wall appearance upon 3 h of annealing at 1100 °C was observed. The fractions characterized by non-stoichiometry phases and the block deviation disappeared. The annealing for 11 h improved the homogeneity and perfection in the crystals. The average density of the etch pits dropped down significantly to 8 × 106 cm−2.

Degradation of Ta2O5 / SiO2 dielectric cavity mirrors in ultra-high vacuum.

In order for optical cavities to enable strong light-matter interactions for quantum metrology, networking, and scalability in quantum computing systems, their mirrors must have minimal losses. However, high-finesse dielectric cavity mirrors can degrade in ultra-high vacuum (UHV), increasing the challenges of upgrading to cavity-coupled quantum systems. We observe the optical degradation of high-finesse dielectric optical cavity mirrors after high-temperature UHV bake in the form of a substantial increase in surface roughness. We provide an explanation of the degradation through atomic force microscopy (AFM), X-ray fluorescence (XRF), selective wet etching, and optical measurements. We find the degradation is explained by oxygen reduction in Ta2O5 followed by growth of tantalum sub-oxide defects with height to width aspect ratios near ten. We discuss the dependence of mirror loss on surface roughness and finally give recommendations to avoid degradation to allow for quick adoption of cavity-coupled systems.

Preventing oxide precipitation in selective wet etching of Si3N4 for 3D-NAND structure fabrication: The role of bubbles

Selective wet etching of Si3N4 is a critical process in the fabrication of 3D-NAND structures; however, it faces a oxide precipitation problem that significantly deteriorates the remaining structure morphology. A recent study by Kim et al.(Kim et al., 2022 [1]) showed that generating CO2 bubbles during the wet etching process efficiently solves the precipitation problem in the fabrication of a 128 multi-layer 3D-NAND structure. In this study, we numerically investigated the multiscale diffusive transport of oxides in the etching process via three different simplified simulations at different scales to reveal the underlying mechanism. We found that mass transport within the multilayer structures alone cannot contribute to the oxide precipitation behavior. Macroscopic transport from the wafer-etchant interface to the bulk must be considered since it contributes to a high oxide concentration at the wafer-etchant surface, which further increases the concentration within the trenches, leading to the precipitation problem. Through the conjecture oxide transport simulation, we found that the large bubbles generated from the reaction agitate the surrounding liquid and dramatically reduce the oxide concentration at the wafer-etchant surface by one order of magnitude, thereby solving the precipitation problem. Our findings clearly explain the experimental results reported by Kim et al. and will further benefit the development of process-intensification technologies in wet etching.

Roles of overlapped scratching in grating fabrications assisted by selective wet etching

Roles of overlapped scratching in grating fabrications assisted by selective wet etching