Selective Thermal Oxidation Research Articles

Etching-free pixel definition in InGaN green micro-LEDs

The traditional plasma etching process for defining micro-LED pixels could lead to significant sidewall damage. Defects near sidewall regions act as non-radiative recombination centers and paths for current leakage, significantly deteriorating device performance. In this study, we demonstrated a novel selective thermal oxidation (STO) method that allowed pixel definition without undergoing plasma damage and subsequent dielectric passivation. Thermal annealing in ambient air oxidized and reshaped the LED structure, such as p-layers and InGaN/GaN multiple quantum wells. Simultaneously, the pixel areas beneath the pre-deposited SiO2 layer were selectively and effectively protected. It was demonstrated that prolonged thermal annealing time enhanced the insulating properties of the oxide, significantly reducing LED leakage current. Furthermore, applying a thicker SiO2 protective layer minimized device resistance and boosted device efficiency effectively. Utilizing the STO method, InGaN green micro-LED arrays with 50-, 30-, and 10-µm pixel sizes were manufactured and characterized. The results indicated that after 4 h of air annealing and with a 3.5-μm SiO2 protective layer, the 10-µm pixel array exhibited leakage currents density 1.2 × 10−6 A/cm2 at −10 V voltage and a peak on-wafer external quantum efficiency of ~6.48%. This work suggests that the STO method could become an effective approach for future micro-LED manufacturing to mitigate adverse LED efficiency size effects due to the plasma etching and improve device efficiency. Micro-LEDs fabricated through the STO method can be applied to micro-displays, visible light communication, and optical interconnect-based memories. Almost planar pixel geometry will provide more possibilities for the monolithic integration of driving circuits with micro-LEDs. Moreover, the STO method is not limited to micro-LED fabrication and can be extended to design other III-nitride devices, such as photodetectors, laser diodes, high-electron-mobility transistors, and Schottky barrier diodes.

Integration of Ultrathin Hafnium Oxide with a Clean van der Waals Interface for Two-Dimensional Sandwich Heterostructure Electronics.

Integrating high-κ dielectrics with a small equivalent oxide thickness (EOT) with two-dimensional (2D) semiconductors for low-power consumption van der Waals (vdW) heterostructure electronics remains challenging in meeting both interface quality and dielectric property requirements. Here, we demonstrate the integration of ultrathin amorphous HfOx sandwiched within vdW heterostructures by the selective thermal oxidation of HfSe2 precursors. The self-cleaning process ensures a high-quality interface with a low interface state density of 1011-1012 cm-2 eV-1. The synthesized HfOx displays excellent dielectric properties with an EOT of ∼1.5 nm, i.e., a high κ of ∼16, an ultralow leakage current of 10-6 A/cm2, and an impressively high breakdown field of 9.5 MV/cm. This facilitates low-power consumption vdW heterostructure MoS2 transistors, demonstrating steep switching with a low subthreshold swing of 61 mV/decade. This one-step integration of high-κ dielectrics into vdW sandwich heterostructures holds immense potential for developing low-power consumption 2D electronics while meeting comprehensive dielectric requirements.

Tailoring of embedded dielectric alumina film in AlGaAs epilayer by selective thermal oxidation

Vertical optical confinement is a critical requirement for a wide range of III-V photonic devices where Al2O3 material is the typical oxide used due to its low refractive index. This oxide layer can be formed from the oxidation of AlAs in an epitaxial GaAs/AlAs/GaAs or AlGaAs/AlAs/GaAs stack, with the advantage that the top layer remains single-crystalline. The thick film oxidation of AlAs is required for photonic applications. In this article, we report the oxidation processes developed to fully convert AlAs to AlOx films by analyzing both thin (100 nm) and thick (500 nm) AlAs films on GaAs (001) and 2° miscut GaAs (111)A substrate. Systematic microscopic characterization is performed to demonstrate the absence of any delamination at the oxide interfaces and the evolution of the diffusive oxidation process microscopically characterized is compared with an optical (µ-Raman) characterization. We demonstrate the selectivity of the AlAs oxidation process with respect to the active Al0.18Ga0.82As layer and the GaAs substrate. Finally, the proposed method is adopted to create a high refractive index contrast between the active optical material and the environment in the specific case of a III-V photonic crystal device, highlighting the potential of this approach for non-linear photonic applications.

19-element vertical cavity surface emitting laser arrays with inter-vertical cavity surface emitting laser ridge connectors

We achieve record concurrent combinations of bandwidth (18 GHz), optical output power (150 mW), and wall plug efficiency (30%) with a unique arrangement of 19-element, electrically parallel 980 nm vertical cavity surface emitting laser (VCSEL) arrays. We use a new two-dimensional, quasi honeycomb geometry with inter-VCSEL ridge connectors—made nonconducting by selective thermal oxidation—to improve heat dissipation and facilitate a single top surface anode contact. Via on-wafer probing we perform static and dynamic measurements over the wide temperature range of 23 °C to 85 °C and extract, report, and discuss key array figures-of-merit.

Scalable Synthesis of Hollow β-SiC/Si Anodes via Selective Thermal Oxidation for Lithium-Ion Batteries.

Silicon for anodes in lithium-ion batteries has received much attention owing to its superior specific capacity. There has been a rapid increase of research related to void engineering to address the silicon failure mechanism stemming from the massive volume change during (dis)charging in the past decade. Nevertheless, conventional synthetic methods require complex synthetic procedures and toxic reagents to form a void space, so they have an obvious limitation to reach practical application. Here, we introduce SiCx consisting of nanocrystallite Si embedded in the inactive matrix of β-SiC to fabricate various types of void structures using thermal etching with a scalable one-pot CVD method. The structural features of SiCx make the carbonaceous template possible to be etched selectively without Si oxidation at high temperature with an air atmosphere. Furthermore, bottom-up gas phase synthesis of SiCx ensures atomically identical structural features (e.g., homogeneously distributed Si and β-SiC) regardless of different types of sacrificial templates. For these reasons, various types of SiCx hollow structures having shells, tubes, and sheets can be synthesized by simply employing different morphologies of the carbon template. As a result, the morphological effect of different hollow structures can be deeply investigated as well as the free volume effect originating from void engineering from both a electrochemical and computational point of view. In terms of selective thermal oxidation, the SiCx hollow shell achieves a much higher initial Coulombic efficiency (>89%) than that of the Si hollow shell (65%) because of its nonoxidative property originating from structural characteristics of SiCx during thermal etching. Moreover, the findings based on the clearly observed different electrochemical features between half-cell and full-cell configuration give insight into further Si anode research.

Oxygen-based digital etching of AlGaN/GaN structures with AlN as etch-stop layers

O2 plasma-based digital etching of Al0.25Ga0.75N with a 0.8 nm AlN spacer on GaN was investigated using an inductively coupled plasma etcher. Silicon oxide layer was used as the hard mask. At 40 W RF bias power and 40 sccm oxygen flow, the etch depth of Al0.25Ga0.75N was 5.7 nm per cycle. The 0.8 nm AlN spacer layer acted as an etch-stop layer in three cycles. The surface roughness improved from 0.66 to 0.33 nm after the three and seven digital etch cycles. Compared to the dry etch only approach, this technique smoothed the surface instead of causing surface roughening. Compared to the selective thermal oxidation with a wet etch approach, this method is less demanding on the epitaxial growth and saves the oxidation process. It was shown to be effective in precisely controlling the AlGaN etch depth required for recessed-AlGaN HEMTs.

Anisotropy in the wet thermal oxidation of AlGaAs: influence of process parameters

The crystallographic anisotropy of the lateral selective thermal oxidation of AlGaAs alloys is experimentally studied. The anisotropic behavior of this oxidation process, used primarily for building a lateral confinement in vertical surface emitting lasers (VCSEL), is quantified by varying different process parameters and the geometrical shapes of laterally oxidized mesa structures. This experimental study aims to have a better control of the oxide aperture shape used in oxide-confined photonics devices.

Hydrogen interaction characteristic of nanoscale oxide films grown on iron–nickel based stainless steel by selective thermal oxidation

Hydrogen isotopes, the reaction ingredients in the nuclear fusion plant, can easily permeate through the stainless steel (SS) substrate, leading to the so-called hydrogen degradation. Generally, a widely accepted way to reduce the hydrogen permeation is to prepare a barrier coating on the substrate. Nevertheless, the coated layer has the inherent problem of incompatibility with the heterogeneous base materials. In this work, in-situ selective oxidation was used to explore the optimal oxides with the improved hydrogen resistance. Two types of layers thermally formed at 450 °C and 750 °C, respectively, were selected to investigate their hydrogen interaction characteristics. Comprehensive analyses, including Raman spectra, XPS, EIS and AES, indicate that the oxide formed at 450 °C is a better candidate of hydrogen permeation barriers, probably due to the formation of protective layers of chromia and FeCr2O4, while the oxides obtained at 750 °C, though exhibiting a much more stable phase, can rarely reduce hydrogen diffusion through the shortcuts of defects. This finding provides a potential new way to prepare a hydrogen permeation barrier.

Comparative Analysis of Growth Rate Enhancement and Ge Redistribution during Silicon-Germanium Oxidation by Rapid Thermal Oxidation

The demand for higher speed and lower power consumption ICs has motivated research for higher mobility channel materials (1). Compressively strained SiGe is known to feature higher hole mobility than Si and is largely compatible with the Si CMOS manufacturing platform. Besides, the FDSOI transistor architecture allows power consumption reduction (2), thus making SiGe-On-Insulator (SGOI) channels promising. SGOI layers can be fabricated by the so-called condensation technique, which is based on concurrent Si selective thermal oxidation of SiGe and SiGe composition homogenization by Si and Ge interdiffusion (see Figure 1) (3). Therefore, a sound understanding of kinetics of oxidation and interdiffusion of SiGe is required to develop optimized SGOI structures. SiGe dry oxidation rate has been reported to be higher (4) than or equal (5)(6) to the one of Si. It therefore remains unclear. Few groups investigated Rapid Thermal Oxidation (RTO) (4) while most of them looked at furnace oxidation. Moreover, most studies only considered the initial Ge content to compare oxidation kinetics. Indeed, the Ge concentration below the SiGe-oxide interface is strongly varying with time because of two mechanisms: firstly, the Si-selective oxidation of SiGe tends to pile-up Ge below the oxidizing interface; and secondly, interdiffusion of SiGe favors homogenization of the layer (6). This paper focuses on the oxidation rate of SiGe in regards to the varying Ge concentration in the SiGe layer for various oxidation conditions. Thick (> 20 nm) SiGe layers with either 10% or 30% Ge concentrations were epitaxially grown on bulk Si wafers. Oxidation was performed by RTO in 1 atmosphere of pure O2, with different oxidation temperatures and durations. Oxide thickness and SiGe composition versus depth were measured by Spectroscopic Ellipsometry and X-Ray Reflectivity, and by Secondary Ion Mass Spectroscopy respectively. Figure 2 shows the Ge concentration profile below the oxide. A rapid creation of a pile-up layer is observed at all temperatures. Then, three regimes of evolution of the pile-up layer are distinguished: the Ge concentration at the oxidizing interface (a) increases, (b) is constant, and (c) decreases. The regime of evolution of the pile-up layer is determined by a competition between the oxidation speed and the interdiffusion speed. As schematically illustrated Figure 3, the interdiffusion speed overcomes the oxidation one at higher temperatures because the activation energy of interdiffusion in SiGe ([4,5] eV (7)) is well above the one of SiGe oxidation ([2,2.6] eV (4)). Phrased in a different way, the temperature dependence of interdiffusion is higher than the oxidation one. Figure 4 shows the oxide thickness versus the oxidation duration for dry RTO at 900°C, 1000°C and 1100°C. A higher oxidation rate is observed for SiGe compared to Si for all temperatures. Then, to highlight the effect of the Ge concentration at the oxidizing interface, we fitted the curves to extract oxidation rates for each oxidation conditions. We define the Growth Rate Enhancement (GRE) as the ratio of the oxidation rate of SiGe to the one of Si at a given oxide thickness and for identical oxidation conditions. It is indeed important to highlight that comparing oxidation rates at the same oxide thickness is mandatory: if we want to examine the effect of Ge on the oxidation rate, we have to take into consideration the fact that the oxidation rate also decreases with the oxide thickness. Such an approach allows us to freeze the system and to find more easily correlations. We report on Figure 5 four GRE values extracted from our data versus the Ge concentration at the oxidizing interface. We thus observe that the higher the Ge concentration at the oxidizing interface is, the higher the GRE tends to be. We thus showed that Ge redistribution by interdiffusion during SiGe oxidation can follow different regimes. We also evidenced that for dry RTO conditions, the higher the Ge concentration at the oxidizing interface is, the higher the GRE is. Understanding the interdependence of these two mechanisms is essential to get an accurate picture of the condensation process. Therefore, data for dry RTO will be completed and an in-depth discussion will be led. A similar study will also be conducted for a wet oxidation process called In-Situ Steam Generation (ISSG). (1) Pillarisetty, R., Nature 479.7373 (2011): 324-328. (2) Weber, O., et al., VLSIT IEEE, 2014. (3) Tezuka, T., et al., JJAP 40.4S (2001): 2866. (4) Spadafora, M., et al. MSSP 8.1 (2005): 219-224. (5) LeGoues, et al., APL 54.7 (1989): 644-646. (6) Long, E., et al., PSS (a) 209.10 (2012): 1934-1939. (7) Kube, R., et al., JAP 107.7 (2010): 073520. Figure 1

Vertically Coupled Microdisk Resonators Using AlGaAs/AlOx Technology

In this letter, we report the first experimental demonstration of microdisk resonators that are vertically coupled to their buried access waveguides on III-V semiconductor epitaxial structures using an original fabrication process. The here-proposed and validated three-dimensional integration scheme exploits selective lateral thermal oxidation of aluminium-rich AlGaAs layers. Compared with the previously reported processing techniques, this new scheme is simpler as it does not require any planarization or substrate transfer steps. As a proof-of-principle demonstration of this approach, 250-μm diameter microdisk devices exhibiting quality factor reaching ~8500 have been successfully fabricated.

Method for improving the electrical insulating properties of wet thermal oxide of AlAsSb on GaSb substrates

In this report, we describe the selective wet thermal oxidation of AlAsSb layers lattice-matched on GaSb substrate for lateral oxide-confinement in mid-infrared lasers. A two-step process of wet thermal oxidation followed by thermal annealing at a higher temperature was used. Raman spectroscopy revealed the formation of antimony oxides and the volatilization of these oxidation byproducts after post-oxidation annealing. Using this method, we obtained higher electrical resistivity of the annealed oxide, which was suitable for confinement applications.

In situ purity enhancement/surface modification of single-walled carbon nanotubes synthesized by induction thermal plasma

A simple, cost-effective and energy-efficient approach was developed for in situ purity enhancement and surface modification of single-walled carbon nanotubes (SWCNTs) produced using an induction thermal plasma process. In this process, SWCNT-containing materials are thermally treated with oxygen flow inside a filtration chamber, while they are assembled into the sheets during the synthesis process. Owing to selective thermal oxidation, the amount of amorphous carbon was significantly reduced in the final product resulting in higher purity SWCNT-containing materials. Parametric study indicated that the amorphous carbon content was noticeably diminished in the product at an oxygen volume concentration of 10% in the synthesis system. Raman analysis indicated a decrease in the population of the SWCNTs with diameters smaller than 1.3 nm after in situ exposure to 10 vol.% of oxygen. In addition to the successful reduction of amorphous carbon content, the oxygen-functionalized SWCNTs were also observed in the final product using this process.

High quality factor etchless silicon photonic ring resonators

We demonstrate high quality factor etchless silicon photonic ring resonators fabricated by selective thermal oxidation of silicon without the silicon layer being exposed to any plasma etching throughout the fabrication process. We achieve a high intrinsic quality factor of 510,000 in 50 µm-radius ring resonators, corresponding to a ring loss of 0.8 dB/cm. The device has a total chip insertion loss of 2.5 dB, achieved by designing etchless silicon inverse nanotapers at both the input and output of the chip.

Novel E-Mode GaN-on-Si MOSHEMT Using a Selective Thermal Oxidation

A novel normally-off AIN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMT) on 100-mm Si substrates for high-power applications is demonstrated for the first time by means of a selective thermal oxidation of AIN. The formation of a high-quality insulating AION layer resulting from the dry thermal oxidation of AIN at 900 °C in oxygen has been identified by transmission electron microscopy and X-ray photoelectron spectroscopy. The AIN thermal oxidation appears to be highly selective toward the SiN cap layer allowing the local depletion of the 2-D electron gas (self-aligned to the gate) and thus the achievement of normally-off operation. Threshold voltage (VT) of +0.8 V and drain leakage current at VGS = 0 V well below 1 μA/mm are obtained reproducibly over the wafer. The comparison of the fabricated MOSHEMTs with the control sample (identical but nonoxidized) reveals a drastic shift of VT toward positive values and three to four orders of magnitude drain leakage current reduction.

Single-crystal diamond probes for atomic-force microscopy

The results of investigations aimed at the development and testing of diamond probes for scanning atomic-force microscopy are presented. Plasmochemical deposition of diamond polycrystalline films and selective thermal oxidation were used to manufacture diamond probes. The obtained single-crystal diamond pyramidal tips of micron size had a radius of curvature of 2–20 nm at the top. The diamond tips were attached to a cantilever with an epoxy adhesive and then tested as probes in scanning atomic-force microscopy. Tests have shown that the manufactured diamond probes have appreciable advantages over conventional probes.

Design and fabrication of a nanofluidic channel by selective thermal oxidation and etching back of silicon dioxide made on a silicon substrate

Based on the law that the oxidation rate of Si decreases with the oxidation time, a method to fabricate a nanochannel is presented. In this method, the depth of the channel is precisely controlled by the oxidation time. Nanochannels are fabricated with depths of several tens of nanometers, width of 20 µm and lengths of several millimeters. SEM images show that the channel is fabricated well. It is shown that the flow rate increases linearly with the inlet pressure for water, NaCl solution and oil. Besides, the flow rate increases with the temperature. The capillary phenomenon is also observed in the nanochannel.

A novel technique for the fabrication of nanostructures on silicon carbide usingamorphization and oxidation

A novel technique for fabricating silicon dioxide(SiO2) and silicon carbide (SiC) nanostructures on SiC substrates is reported in this paper.The technique involves amorphization of crystalline SiC at the nanoscale using afocused ion beam followed by selective thermal oxidation that results in oxidenanostructures due to the enhanced oxidation rate of amorphous SiC. Selectiveetching of the oxide results in crystalline SiC nanostructures. Nanostructures(SiO2 and SiC) withminimum feature sizes of ∼55 nm have been fabricated. Oxide nano-channels with channel widths of less than 20 nm aredemonstrated. The physical mechanisms that control the evolution of the structures andlimit the resolution have been addressed.

Corrosion Resistance of Aluminum Nitride as Semiconductor Equipment Parts Studied by Micro-Raman Spectroscopy

A micro-Raman spectroscopic investigation has been performed to observe structural disorder in each grain of aluminum nitride ceramics as semiconductor equipment parts. A selective thermal oxidation treatment normalizes a different rate of a corrosion reaction depending on the crystal face and consequently improves the corrosion resistance. Upon thermal oxidation treatment, line widths of Raman bands increased more in grains including mainly crystals with (100) preferred orientation than in those of (002), indicating that (100) faces oxidize preferentially rather than (002) faces. According to Raman shift from the oxidized sample, oxidation induces residual compressive stress for grains including a large number of (100) prefer-oriented crystals. On fluorination of the oxidized sample, no increase of line widths was observed in both kinds of grains, suggesting that prior anisotropic thermal oxidation treatment of (100) faces, which are more sensitive to corrosion than (002) faces, inhibits the progress of corrosion.

Corrosion Resistance of Aluminum Nitride as Semiconductor Equipment Parts Studied by Micro-Raman Spectroscopy

A micro-Raman spectroscopic investigation has been performed to observe structural disorder in each grain of aluminum nitride ceramics as semiconductor equipment parts. A selective thermal oxidation treatment normalizes a different rate of a corrosion reaction depending on the crystal face and consequently improves the corrosion resistance. Upon thermal oxidation treatment, line widths of Raman bands increased more in grains including mainly crystals with (100) preferred orientation than in those of (002), indicating that (100) faces oxidize preferentially rather than (002) faces. According to Raman shift from the oxidized sample, oxidation induces residual compressive stress for grains including a large number of (100) prefer-oriented crystals. On fluorination of the oxidized sample, no increase of line widths was observed in both kinds of grains, suggesting that prior anisotropic thermal oxidation treatment of (100) faces, which are more sensitive to corrosion than (002) faces, inhibits the progress of corrosion.

Fabrication of a depletion mode GaAs MOSFET using Al 2O 3 as a gate insulator through the selective wet oxidation of AlAs

A 1 μm thick undoped GaAs buffer layer, a 1500 Å thick n-type GaAs layer, an undoped 500 Å thick AlAs layer and a 50 Å thick GaAs cap layer were consecutively grown by molecular beam epitaxy (MBE) on a [100] oriented semi-insulating GaAs substrate. The AlAs layer was oxidized in a N 2 bubbled H 2O vapor ambient at 400°C for 3 h and fully converted to Al 2O 3 for use as a gate insulator. The I– V characteristics, having a maximum drain current of 10.6 mA, a current cut-off voltage of −4.5 V and a maximum transconductance value of 11.25 mS/mm, indicate that the selective wet thermal oxidation of AlAs/GaAs was successful in producing a depletion mode GaAs MOSFET.