Selective Etching Process Research Articles

Improvements in the performance of the n+ cap-layer GaN in the formation of transistor structures based on AlGaN / GaN

The use of heavily doped protective layers of gallium nitride in AlGaN/GaN heterostructures makes it possible to improve the characteristics of transistors. In this paper, using structures with a protective cap layer and the process of selective etching, structures of HEMT transistors are fabricated. Using the n+-GaN layer, remove the contact resistance from 1 Ω·mm to 0.74 Ω·mm. The transistors show a maximum drain current of 380mA/mm and a steepness of 140mS/mm with an output power of 5W/mm.

Selective Wet Etching in Fabricating SiGe and Ge Nanowires for Gate-all-Around MOSFETs

A selective wet etching process for fabricating SiGe and Ge nanowires for gate all around transistors is introduced in this paper. Two formulated proprietary chemical mixtures with highly selective etching properties (Si vs. SiGe and SiGe vs. Ge) can effectively dissolve the sacrificial layers with minimal damage to the interstitial nanowire materials. The Auger Electron Spectroscopy (AES) surface characterization indicates that no chemical contamination is left after the wet etching process.

(Invited) Epitaxy of (SiGe/Si) Superlattices for the Fabrication of Horizontal Gate-All-Around Nanosheet Transistors

Stacked horizontal Gate All Around Nanosheet transistors were recently proposed as a replacement of FinFET for the sub-7nm device nodes. In order to stack Nanosheet channels, a specific SiGe/Si superlattice epitaxy is employed, with SiGe being used as a sacrificial layer that will define the suspension thickness (Tsus) between the channels. In this paper, we will consider the optimization of SiGe/Si multilayer epitaxy for Nanosheet channel definition (Fig. 1). Stacks with different Ge compositions are physically characterized and studied. With strain characterization and x-ray diffraction measurements on (100) substrates, we will show that it is possible to form pseudomorphic defect-free SiGe/Si multilayers over a wide range of Ge concentrations in the sacrificial SiGe (Fig. 2 and 3). The uniformity obtained on blanket 300mm substrates will be presented (Fig. 4), with a discussion on the SiGe/Si interface abruptness. In the context of CMOS device integration, it is necessary to employ a low temperature STI process to mitigate the Ge inter-diffusion in the silicon channel and to avoid the possible generation of defects from plastic relaxation of SiGe. The SiGe and Ge-Si intermixed regions are removed with appropriate selective etch process in two Nanosheet specific modules: inner spacer formation in the extension regions (Fig. 5) and post channel release in the gate regions (Fig. 6), leaving only 5nm intrinsic silicon Nanosheets. We will report the etch rate and selectivity of our in-house vapor-phase channel release process performed at low temperature. This process enables us to remove SiGe versus Si with a great selectivity and a limited amount of silicon loss during channel release, before gate stack deposition around the stacked Nanosheets. From a device perspective, we will show that the optimization of the silicon thickness in the SiGe/Si superlattice plays an important role in the Nanosheet device performance and electrostatics (Fig. 7). Finally, with a good SiGe/Si multilayer uniformity control, a reduced thermal budget and after optimization of our in-house SiGe selective etch process, we will show the capability to form 5nm silicon Nanosheet channels with small within wafer variation, low device variability and good process control, compatible with the fabrication of very large scale integrated circuits for future CMOS device nodes. Acknowledgements: This work was performed by the Research Alliance Teams at various IBM Research Facilities. Figure 1

(Invited) Continued Device Miniaturization Enabled By New Materials Innovations and Advanced Patterning Schemes

The microelectronics industry continues to experience high demand for new materials innovation driven by the need for solutions in the advanced patterning space. As device features and critical dimensions continue to shrink, the complexity of chip fabrication increases at an exponential rate. With this increase in complexity, many issues and challenges arise. For instance, with more steps and smaller dimensions, Edge Placement Error (EPE) becomes a key limiting factor towards enabling future nodes. EPE is the error between the intended and actual placements of desired features in a device. Smaller device features afford tighter tolerance specifications and smaller error budgets. Advanced devices require multiple patterning steps, which increase the potential for errors and misalignments. EPE can have detrimental effects on device performance due to contact shorts and open circuits, often leading to poor device yields. One way to limit the effects of EPEs is to use self-alignment patterning schemes. Selective deposition and selective etch processes are both key enablers for the development of self-aligned processes in semiconductor fabrication. Figure 1(a) shows a standard contact patterning flow without self-alignment. Selective deposition can relax the lithography and overlay requirements, as shown in Figure 1(b), and greatly decrease EPE by enabling self-alignment patterning schemes. Furthermore, as devices continue to shrink, conventional etch processes suffer from poor etch control and line edge roughness and thus can also contribute to EPE for future nodes. Atomic layer Etch (ALE) is an emerging etch technique that uses two or more precursors in a sequential fashion where the surface modification during precursor exposure is self-limiting leading to highly controllable etches that are very smooth and conformal. In addition, the filling of high aspect ratio features is also a key enabler to complicated multi-patterning flows (such as reverse tone patterning). Although there has been remarkable progress on these fronts, further developments are needed to ensure the scalability of microelectronics devices. This presentation will focus on insights and recent research results in the quest for enabling new patterning schemes through the development of new selective ALD processes, thermal ALE processes, and methods for the gap fill of high aspect ratio features. Figure 1

A comparative study of selective dry and wet etching of germanium–tin (Ge1−xSnx) on germanium

A comparative study of selective dry and wet etching methods for germanium–tin (Ge1−xSnx) alloys (3.5% < x < 7.7%) and germanium (Ge) is carried out. Both etching methods are optimized from the perspectives of selectivity and morphology, and then compared. A special behavior of the selective dry etching process is discovered and explained, whereby the selectivity has a dramatic increase to as high as 336 when the Sn concentration is above 6%. Different morphologies of suspended microstructures fabricated by different etching methods are investigated. Comparative study shows that the selective dry etching is a better choice for high Sn concentration GeSn (above 7%) against Ge to have better morphology, selectivity and verticality. While for low Sn concentration GeSn (below 6%), wet etching is a better way to fabricate a suspended GeSn microstructure on Ge. This work provides a comparative understanding of both methods of selective etching for GeSn. This comparative understanding is expected to be applied in the processing of next generation electronic and photonic devices.

Nitrogen reactive ion etch processes for the selective removal of poly-(4-vinylpyridine) in block copolymer films

Self-assembling block copolymer (BCP) patterns are one of the main contenders for the fabrication of nanopattern templates in next generation lithography technology. Transforming these templates to hard mark materials is key for pattern transfer and in some cases, involves selectively removing one block from the nanopattern. For poly(styrene)-block-poly(4-vinylpyridine) (PS-b-P4VP), a high χ BCP system which could be potentially incorporated into semiconductor nanofabrication, this selective removal is predominantly done by a wet etch/activation process. Conversely, this process has numerous disadvantages including lack of control and high generation of waste leading to high cost. For these reasons, our motivation was to move away from the wet etch process and optimise a dry etch which would overcome the limitations associated with the activation process. The work presented herein shows the development of a selective plasma etch process for the removal of P4VP cores from PS-b-P4VP nanopatterned film. Results have shown that a nitrogen reactive ion etch plasma has a selectivity for P4VP of 2.2:1 and suggest that the position of the nitrogen in the aromatic ring of P4VP plays a key role in this selectivity. In situ plasma etching and x-ray photoelectron spectrometry measurements were made without breaking vacuum, confirming that the nitrogen plasma has selectivity for removal of P4VP over PS.

Improved thermal properties by controlling selective distribution of AlN and MWCNT in immiscible polycarbonate (PC)/Polyamide 66 (PA66) composites

A stable co-continuous morphology was achieved in immiscible polycarbonate (PC)/polyamide 66 (PA66) blend by controlling the selective distribution of multi-walled carbon nanotubes (MWCNT) and aluminum nitride (AlN) nanoparticles. SEM and TEM tests proved that hybrid fillers were both located in PA66 phase. Selective etching process was applied to confirm the gradual variation of morphologies. It indicated that the compatibilities between PC and PA66 were gradually enhanced since the phase size reduced significantly and the interface of two phases blurred after the fillers were incorporated. DMA confirmed that the glass transition temperature of PC and PA66 appeared a trend to merge, besides, the tensile properties were enhanced. TGA indicated that the in-situ generated PC-b-PA66 copolymer played an important role in the compatibilization effect. Besides, the raised interconnectivities were proved by theoretical models and the maximum thermal conductivity of 1.3 W/mK at hybrid fillers loading of 24.78 vol% was obtained.

Nanostructured polycarbonate for robust transparency and anti-fogging by control of self-masking metallic clusters

High-aspect-ratio nanostructures formed on a transparent polymer can be easily damaged after several cycles of anti-fogging testing, resulting in a reduction in optical transmittance. To ensure the robust wetting and optical properties of the transparent polycarbonate, we controlled the nanostructure geometries by adding the inert argon gas to oxygen gas during plasma-based selective ion etching process, resulting in both better transparency and longer-lasting anti-fogging properties. We confirmed that the size of the metallic clusters as a self-etching mask is strongly related to the aspect ratio of the final nanostructures. Since metallic clusters with relatively large diameters were formed with the addition of argon gas to oxygen gas, the robustness of the polycarbonate wettability and transparency instilled by the robust nanostructures was improved, as indicated by cyclic anti-fogging testing.

Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAlAs/InGaAs InP-based HEMTs

A two-step gate-recess process combining high selective wet-etching and non-selective digital wet-etching techniques has been proposed for InAlAs/InGaAs InP-based high electron mobility transistors (HEMTs). High etching-selectivity ratio of InGaAs to InAlAs material larger than 100 is achieved by using mixture solution of succinic acid and hydrogen peroxide (H2O2). Selective wet-etching is validated in the gate-recess process of InAlAs/InGaAs InP-based HEMTs, which proceeds and automatically stops at the InAlAs barrier layer. The non-selective digital wet-etching process is developed using a separately controlled oxidation/de-oxidation technique, and during each digital etching cycle 1.2 nm InAlAs material is removed. The two-step gate-recess etching technique has been successfully incorporated into device fabrication. Digital wet-etching is repeated for two cycles with about 3 nm InAlAs barrier layer being etched off. InP-based HEMTs have demonstrated superior extrinsic transconductance and RF characteristics to devices fabricated during only the selective gate-recess etching process because of the smaller gate to channel distance.

A simple route for preparing Au/mesoporous silica yolk/shell particles for Au-catalyzed reactions

We present a simple route to prepare mesoporous hollow silica particles containing an Au core, i.e., yolk/shell particles, by sol-gel and selective etching processes. Using tetraethoxysilane as a silica precursor, zinc acetate as a base catalyst, and cetyltrimethylammonium chloride as a soft template in the presence of Au nanoparticles, double-layered mesoporous shells were produced in one step. Elemental analysis showed that the inner shell consists of zinc silicate and the outer shell is pure silica. Au/mesoporous silica yolk/shell nanoparticles were obtained by selective etching of the zinc oxide phase with citrate buffer. The particle structure and composition were studied by transmission electron microscopy with energy disperse spectroscopy, UV-vis spectroscopy, X-ray diffraction, and nitrogen sorption experiments. Formation of double shells on the Au core in a single step was explained by a difference in the formation rates of the silica and zinc silicate phases. Au/mesoporous yolk/shell particles showed a high catalytic activity for reduction of 4-nitrophenol.

Integration of Electrodeposited Ni-Fe in MEMS with Low-Temperature Deposition and Etch Processes.

This article presents a set of low-temperature deposition and etching processes for the integration of electrochemically deposited Ni-Fe alloys in complex magnetic microelectromechanical systems, as Ni-Fe is known to suffer from detrimental stress development when subjected to excessive thermal loads. A selective etch process is reported which enables the copper seed layer used for electrodeposition to be removed while preserving the integrity of Ni-Fe. In addition, a low temperature deposition and surface micromachining process is presented in which silicon dioxide and silicon nitride are used, respectively, as sacrificial material and structural dielectric. The sacrificial layer can be patterned and removed by wet buffered oxide etch or vapour HF etching. The reported methods limit the thermal budget and minimise the stress development in Ni-Fe. This combination of techniques represents an advance towards the reliable integration of Ni-Fe components in complex surface micromachined magnetic MEMS.

Fabrication of dye-sensitized solar cells using a both-ends-opened TiO 2 nanotube/nanoparticle hetero-nanostructure

Abstract We fabricated a hetero-structure photoanode with both-ends-opened TiO2 nanotubes and TiO2 nanoparticles for dye-sensitized solar cells (DSSCs). Two-step anodization and selective etching process were used to obtain the both-ends-opened TiO2 nanotubes. A heat treatment was employed to obtain anatase crystal-structured nanotubes. The effect of the both-ends-opened TiO2 nanotubes on the photoelectric conversion efficiency (PCE) of the DSSCs was evaluated by positioning the TiO2 nanotubes on TiO2 nanoparticle layers and by sandwiching them between the TiO2 nanoparticles. It is suggested that both-ends-opened TiO2 nanotubes serve as incident light scattering layers that lead to superior light harvesting efficiency of DSSCs. This increases the electron lifetime and results in the recycling of more light by dye molecules, thus increasing the photocurrent density. Consequently, a high PCE of 7.74% was obtained when the TiO2 nanotubes were placed on the TiO2 nanoparticles and a PCE of 8.56% was obtained when the TiO2 nanotubes were placed between the TiO2 nanoparticles.

Dual-Core Fe2O3@Carbon Structure Derived from Hydrothermal Carbonization of Chitosan as a Highly Efficient Material for Selective Adsorption

A dual-core Fe2O3@carbon structure was prepared by a hydrothermal treatment of iron salt and chitosan (CS) solution. The structure exhibits microsphere-like (∼850 nm in size) morphology with dual cores at two ends. The existence of CS plays an important role in the formation of the dual-core–shell structure. The unique structure was investigated to be a CS adsorption, and subsequent carbonization induced a selective etching process. Further, the special structure was proven to be a highly efficient material for selective adsorption. The dual-core structure facilitates the exposure of the Fe2O3 surface, and the carbonaceous shell gives plenty of functional groups for selective adsorption. More importantly, the selectivity was highly dependent on pH values. It was found that the adsorbent showed higher adsorption selectivity toward Cr(VI) at lower pH values, while the selectivity transferred toward Cu(II) at higher pH values by adsorption of Cu(II) and Cr(VI) in single-component solutions. In binary-component solution, the dual-core Fe2O3@C structure revealed adsorption selectivity for Cr(VI), with the highest separator factor [αCu(II)Cr(VI)] = 1162, due to the strong electrostatic adsorption-coupled reduction interaction induced by the special structure of the adsorbent. This work not only gives deep insights into the understanding of the formation of the dual-core structure but also supplies a novel adsorbent with selective adsorption properties for water treatment.

Hollowing out MOFs: hierarchical micro- and mesoporous MOFs with tailorable porosity via selective acid etching.

We report a new strategy for the synthesis of robust hierarchical micro- and mesoporous MOFs from water stable MOFs via a selective acid etching process. The process is controlled by the size-selective diffusion of acid molecules through the MOF windows. This method enables the fine-tuning of the porosity of hierarchical MOFs, allowing for the generation of well-defined mesopores with high mesopore volume. Because of the size-selective diffusion of acid molecules, the inherent crystallinity and external morphology of the resulting MOFs are well-maintained after acid treatment. This novel strategy may provide an alternative route towards the synthesis of diverse hierarchical MOFs.

Zero-dead-volume interfaces for two-dimensional electrophoretic separations.

We present the study on the sample transfer characteristics of two different microfluidic interfaces for 2D-CE . These interfaces were manufactured using two different microfabrication technologies: one was obtained via the classical photolithography-wet etching-anodic-bonding process; and the other was obtained via the selective laser-induced etching process. The comparison of the two interfaces, and an intact capillary as a reference, was made via the CE separation of amino acids (arginine and lysine) under different bulk flow conditions, with and without applying bias potential to the secondary channels. The influence on peak shapes, migration times, and repeatabiliy were evaluated.

Highly Selective Wet Silicon Etch Chemistry and Process for Advanced Semiconductor Packaging

Abstract A wet silicon etch chemistry and a process using the chemistry as a simple and cost-effective alternative to the polish/plasma etch silicon thinning process are presented in this paper. The new etch chemistry improves the Si etch rate over traditional etchants such as tetramethylammonium hydroxide (TMAH). The chemistry has very high silicon etch selectivity (ratio of Si etch rate to another film etch rate) over SiO2 and over copper films, with etch selectivity greater than 8000:1 and 2500:1 respectively. Chemical compatibility with typical packaging materials such as polybenzoxazole (PBO) and polyimide (PI) are also discussed. Additionally, real production TSV wafers have been successfully processed on an advanced single wafer etch tool using the chemistry. High uniformity and smooth surface finishing have been achieved.

Process development and edge-placement yield modeling of alternating-material self-aligned multiple patterning

We propose and discuss a modular technology to reduce the edge-placement-error effect by combining selective etching and alternating-material (dual-material) self-aligned multiple patterning (altSAMP) processes. A geometrical cut-process yield model considering the joint effect of overlay errors, cut-hole, and line CD variations is developed to analyze its patterning performance. In addition to the contributions from the above three process variations, the impacts of key control parameters (such as cut-hole overhang and etching selectivity) on the patterning yield are examined. It is shown that the optimized altSAMP patterning process significantly improves the patterning yield compared with conventional SAMP processes, especially when the half pitch of device patterns is driven down to 7 nm and below. Moreover, the corresponding layout decomposition and synthesis strategy are also discussed. The experimental results of altSAMP process development and material screening are reported.

300 mm SiGe-On-Insulator Substrates with High Ge Content (70%) Fabricated Using the Smart Cut™ Technology

Bulk silicon device technologies are reaching fundamental scaling limitations. The 28 nm and 22 nm technology nodes have seen the introduction of Ultra-Thin Body and Buried Oxide Fully Depleted SOI (UTBB-FDSOI) [1] and FinFETs [2], respectively. Fully Depleted transistor technologies are mandatory to suppress short channel effects. Today, all major research and development alliances carry the message that the silicon and its Fully Depleted transistor technologies have the potential to address roadmap requirements down to the 10 nm node. High mobility materials are expected to replace silicon as the channel material: attention has recently been focused on III-V (such as GaAs or InGaAs) and germanium (Ge). Ge has a privileged status: indeed, it belongs to column IV of Mendeleiev Table and it is a good candidate for high mobility p-channel and n-channel devices. Hole mobility (respectively electron mobility) in bulk Ge is indeed roughly 4 times (2 times) that in bulk Si. Nevertheless, changing from Si to Ge influences more than just the on-state current. The smaller bandgap value of Ge (0.66 eV versus 1.12 eV for Si) increases the junction leakage, and may therefore lead to a significant increase in the transistor off-state current [3-4]. SiGe alloy material with a high Ge ratio is a good compromise. Recently high-Ge-content (HGC) SiGeOI finFET have been demonstrated with record mobility values and good cut-off behavior [5] indicating the potential of such a channel material. In this paper, we will present our work on 300 mm SiGe-on-insulator (SiGe-OI) substrates with high Ge concentrations (70%). The process flow is illustrated in Fig.1. The standard SOI Smart CutTM process has been adapted for SiGe-OI substrates. The first focus is on the donor substrate and the SiGe epilayers. The donor surface quality should be carefully controlled and optimized before the bonding step. Fig. 2 shows the X-ray reflectivity measurements on the top layers of the Si0.3Ge0.7stack at the end of the epitaxial process steps. The significant interference fringes indicate the good quality of the different surfaces and interfaces which is confirmed by the roughness measurement (Atomic Force Microscopy image in Fig. 2 - right) with a Root Mean Square (RMS) roughness value as low as 0.18 nm on top of the donor substrates. The bonding process and the adapted Hydrogen-induced layer transfer inside the HGC SiGe layer will be presented. The second focus is on the finishing process steps to obtain the desired HGC SiGe-OI substrate. To ensure a good thickness control, the combination of multi-layer donor materials and selective chemical etching process has replaced the polishing removal process. As shown in Fig. 3, it enables to reach a SiGe-OI layer of 56 nm with a uniformity of +/- 3.5 nm at a 300 mm substrate scale. Final RMS surface roughness as low as 0.3 nm is obtained on finished HGC SiGe-OI substrate. Acknowledgment: The authors are grateful for the support given by the European Commission (ECSEL-WAYTOGO FAST 662175) [1] J. Hartmann, FDSOI workshop, 2012 [2] C. Auth, VLSI-T, 2012 [3] C. Claeys and E. Simoen, Eds., Germanium-based technologies – From materials to devices. Elsevier, 2007. [4] G. Eneman, ESSDERC 2007. [5] Hashemi, VLSI 2015. Figure 1

Preparation of multifunctional Al-Mg alloy surface with hierarchical micro/nanostructures by selective chemical etching processes

A superamphiphobic aluminum magnesium alloy surface with enhanced anticorrosion behavior has been prepared in this work via a simple and low-cost method. By successively polishing, etching and boiling treatments, the multifunctional hierarchical binary structures composed of the labyrinth-like concave-convex microstructures and twisty nanoflakes have been prepared. Results indicate that a superhydrophobic contact angle of 160.5° and superoleophobic contact angle larger than 150° as well as low adhesive property to liquids are achieved after such structures being modified with fluoroalkyl-silane. Furthermore, the anticorrosion behaviors in seawater of as-prepared samples are characterized by electrochemical tests including the impedance spectroscopies, equivalent circuits fittings and polarization curves. It is found that the hierarchical micro/nanostructures accompanying with the modified coating are proved to possess the maximal coating coverage rate of 90.0% larger than microstructures of 85.9%, nanostructures of 83.8% and bare polished surface of 67.1% suggesting the optimal anticorrosion. Finally, a great potential application in concentrators for surface-enhanced Raman scattering (SERS) analysis of toxic and pollutive ions on the superamphiphobic surface is also confirmed. This work has wider significance in extending further applications of alloys in engineering and environmental detecting fields.

Atomic Layer Deposition of Bismuth Vanadates for Solar Energy Materials.

The fabrication of porous nanocomposites is key to the advancement of energy conversion and storage devices that interface with electrolytes. Bismuth vanadate, BiVO4 , is a promising oxide for solar water splitting where the controlled fabrication of BiVO4 layers within porous, conducting scaffolds has remained a challenge. Here, the atomic layer deposition of bismuth vanadates is reported from BiPh3 , vanadium(V) oxytriisopropoxide, and water. The resulting films have tunable stoichiometry and may be crystallized to form the photoactive scheelite structure of BiVO4 . A selective etching process was used with vanadium-rich depositions to enable the synthesis of phase-pure BiVO4 after spinodal decomposition. BiVO4 thin films were measured for photoelectrochemical performance under AM 1.5 illumination. The average photocurrents were 1.17 mA cm(-2) at 1.23 V versus the reversible hydrogen electrode using a hole-scavenging sulfite electrolyte. The capability to deposit conformal bismuth vanadates will enable a new generation of nanocomposite architectures for solar water splitting.