Selective Epitaxial Growth Of Silicon Research Articles

Controlling the beam angle spread of carbon implantation for improvement of bin map defect in V-NAND flash memory

As the shrinkage of devices accelerates and the vertical layers increase, beam angle spread of carbon ion implantation (C IIP) for the silicon selective epitaxial growth (Si-SEG) areas in V-NAND is one of the most critical parameters related with bin map defects. The roles of C IIP in Si-SEGs are that it can suppress channeling effect of boron IIP and diffusion limitation of boron dopants during subsequent annealing processes. In this study, beam angle spread was reduced by 36% and the center-to-edge beam angle skew of wafer was reduced to less than 1° by optimizing the specification of tracking magnet and the beam angle mean. After applying the improved process conditions and effective interlocks, the bin defective rate was controlled less than 0.5% successfully.

In situ implementation of silicon epitaxial layer on amorphous SiO2 using reduced-pressure chemical vapor deposition

With the increasing power demand of system-on-chip structures, an ultrathin body is increasingly important owing to its low power leakage; silicon-on-insulator (SOI) technology is used to fabricate such ultrathin platforms. However, the contemporary SOI process and the wafer itself are complex and expensive. In this study, we developed an easy SOI fabrication process that can be implemented on any desired local area of a bulk silicon wafer using the commercially implemented reduced-pressure chemical vapor deposition technique. A local SOI was fabricated through the selective epitaxial growth of silicon, which can also be grown laterally on top of amorphous SiO2 patterned with a 1 μm-wide silicon seed zone and an etch stopper with dimensions of 20 × 100 μm. The local SOI, processed to a thickness of 100 nm or less by chemical mechanical polishing, exhibited a highly crystalline state, as confirmed by cross-sectional imaging and diffraction pattern analysis, surface roughness analysis, and wide-range epitaxy analysis. The local SOI exhibited a surface roughness of 0.237 nm and maintained a perfect (100) crystal plane, identical to that of the silicon wafer, under optimized process conditions. We successfully fabricated reconfigurable transistors on the present local SOI, which implies that contemporary silicon electronics can take advantage of SOI devices on its own platform.

Boron-doped selective silicon epitaxy: high efficiency and process simplification in interdigitated back contact cells

The present research and development activities in crystalline silicon photovoltaics include the exploration of doping technologies alternative to the mainstream diffusion process. The goal is to identify those technologies with potential to increase the solar cell efficiency and reduce the cost per watt peak. In that respect, this work presents the selective epitaxial growth of silicon as a candidate for boron doping; showing the results of the evaluation of boron-doped silicon epitaxial emitters on slurry and diamond-coated wire-sliced Czochralski material, their integration in interdigitated back contact solar cells, and the development of a novel process sequence to create the interdigitated rear junction of these devices using selective epitaxial growth. Boron-doped silicon epitaxy is demonstrated to perform in the high efficiency range (>22%), and the use of selective epitaxial growth is proposed as a route for the simplification of the interdigitated back contact solar cell flow. Copyright © 2013 John Wiley & Sons, Ltd.

The Enhancement of Etch Rate of Silicon by Heavy Doping of Phosphorus and Arsenic Atoms during Cyclic Selective Epitaxial Growth of Silicon

In this study, the enhancement of the silicon etch rate with the heavy doping of phosphorus and arsenic was studied during cyclic selective epitaxial growth process using batch-type equipment. The reaction between molecular chlorine and heavily doped silicon was stimulated during the initial stage of cyclic SEG process at low temperature lower than 700° to induce voids at the interface. Heavy doping of n-type dopants into active regions also brought about the decrease in the growth rate of SEG process. It was possible to attain a stable process window by the elaborate control of total amount ratio of SiH4/Cl2. The window provided the robust interface between SEG silicon and active regions as well as the selectivity to an oxide layer. Vertical diodes which were realized within the window revealed eligible on- and off-current characteristics for cell switches applicable to next generation cross-point memories.

The Enhancement of Etch Rate of Silicon by Heavy Doping of Phosphorus and Arsenic Atoms During Cyclic Selective Epitaxial Growth of Silicon

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Modeling of {311} facets using a lattice kinetic Monte Carlo three-dimensional model for selective epitaxial growth of silicon

Using lattice kinetic Monte Carlo, we provide a quantitative physically based atomistic model for the selective grown of Si-based materials, and explain {311} facet formation while remaining computationally efficient. Descriptions of the local atomistic configurations critical for the developing of {100}, {110}, {111}, and {311} facets are given. The model also introduces (a) three different microscopic growth rates for local {100} planes, needed to properly simulate the formation of perfect {100} terraces in miscut substrates and (b) a break-up energy to account for bonding during {311} facet formation. The model has been verified against experimental results.

Selective Epitaxial Growth of Silicon for Vertical Diode Application

Selectivity control in silicon selective epitaxial growth (SEG) for deep contact patterns, which is one of the key processes for silicon-based stacked devices and cell switches for next generation memories, was studied. Absolute values of selectivity loss during silicon SEG using the most popular H2/dichlorosilane (DCS)/HCl gas system were evaluated using a commercialized inspection tool in 200 mm wafers with real contact patterns. It was revealed that HCl/(DCS+HCl) ratio and the contact structure played a crucial role in suppressing selectivity loss. The number of selectivity losses in an entire wafer was less than 100 when the HCl/(DCS+HCl) ratio was larger than 0.41. The vertical pn diode prepared using the silicon SEG process with elaborate selectivity control showed more remarkable electrical abilities to accommodate current flow than polycrystalline silicon (poly-Si), including the ideality factor and swing, and reverse leakage current.

Selective Epitaxial Growth of Silicon Layer Using Batch-Type Equipment for Vertical Diode Application to Next Generation Memories

Vertical diodes for cross-point phase change memory were realized by selective epitaxial growth (SEG) technique using cyclic chemical vapor deposition method. H2/SiH4/Cl2 cyclic CVD system was introduced in batch-type vertical furnace equipement, replacing conventional single-wafer H2/dichlorosilane/HCl CVD system. It provided excellent capacity of 40 wafers per batch. Selectivity loss which is one of the most crucial features in SEG process for diode application was controlled with both the amount of SiH4 and Cl2 and the period of gas supply, and practical value of selectivity loss was confirmed to be less than 100 in 200-mm wafers. Structural and electrical properties of pn diodes were investigated, and cyclic SEG silicon diode showed more eligible electrical ability to current flow than that of poly-si in terms of forward current and ideality factor as well as lower reverse leakage current.

Si and SiGe faceting during selective epitaxy

Facet apparition during selective epitaxial growth of silicon and silicon–germanium alloys is reported in terms of morphology and kinetics. Epitaxial growth was performed on (0 0 1) Si wafers by chemical vapour deposition using the H 2/HCl/SiH 2Cl 2 chemistry for silicon and GeH 4 addition for silicon–germanium alloy. The (0 0 1) Si and SiGe growth rate was found to be limited by chlorine desorption at low temperature. The creation and development of (3 1 1) facets has been clearly explained by the epitaxial growth kinetics considerations. The impact of the deposition conditions, of the pattern structure and also of the dielectric nature on faceting are discussed here and analysed, thanks to cross section scanning electron microscopy (XSEM) and cross section transmission electron microscopy (XTEM) observations.

Selective epitaxial silicon growth in high aspect ratio contact on 70 nm node flash memory

Selective epitaxial growth (SEG) silicon as sacrificial layer is proposed to circumvent junction leakage ( I jun) of bit line contact due to silicon substrate loss by high aspect ratio contact etching and spontaneous salicide formation. The result indicates that the appropriate SEG silicon in contact area significantly reduces I jun about three orders compared with no SEG silicon. In addition, the SEG method provides acceptable Kelvin contact resistance. Furthermore, during salicide formation, the consumed ratio of titanium to silicon is 0.7. It is confirmed that the feasible approach not only prevents from I jun deterioration but also adjusts contact resistance as well.

Characteristics of in-situ phosphorus-doped silicon selective epitaxial growth at atmospheric pressure

The characteristics of in-situ P-doped Si selective epitaxial growth (SEG) under atmospheric pressure (AP) was investigated and compared with in-situ As-doped SEG under AP. Dopant concentrations and growth rates of films grown at AP are higher than those at low pressure, this for both dopants. This was interpreted as effects of surface segregation of the dopant atoms and the strong etching effect of HCl during the SEG under AP. By optimizing the growth rate and temperature, we achieved a high dopant concentration of 7.3×10 19 atoms/cm 3 and a high growth rate for the P-doped SEG.

Investigation of In-situ Boron-Doped Si Selective Epitaxial Growth by Comparison with Arsenic Doping

In-situ boron-doped silicon selective epitaxial growth (SEG) was investigated by comparison with in-situ As-doped SEG. The dopant concentration and growth rate of the film grown under low pressure are high for B-doped SEG, while they are high under atmospheric pressure (AP) for As-doped SEG. This difference is interpreted to be due to the strong effects of HCl etching under AP and surface segregation of As. By optimizing the growth rate and temperature, we have successfully grown epitaxial Si layers with high B concentrations of 2.3 ×1020 atoms/cm3.

Correlation of the growth rate for selective epitaxial growth of silicon and oxide thickness and oxide coverage in a reduced pressure chemical vapor deposition pancake reactor

The selective epitaxial growth (SEG) rate of silicon for wafers with various oxide coverages (OCs) (the ratio of oxide area to silicon area on a silicon wafer) and oxide thicknesses, ranging from 0% to 90% and 0to500nm, respectively, in a rf heated cold-wall reduced-pressure chemical vapor deposition (RPCVD) pancake reactor, using the SiH2Cl2–HCl–H2 gas system, was investigated at a chamber pressure of 40Torr and a temperature of 970°C. The highest growth rate is about 175nm∕min, occurred at the oxide coverage of 90% and oxide thickness of 200nm; the lowest growth rate is about 112nm∕min, occurred at the oxide coverage of 30% and oxide thickness of 500nm. The growth rate of a control sample (a bare silicon wafer) is 110nm∕min. According to these data, a semiempirical expression for the SEG rate of undoped wafers in an RPCVD pancake reactor system is developed. The growth rate is exponentially dependent on the oxide coverage and a function of oxide thickness. This expression is suitable for the in situ p-t...

High-density plane deposition kinetics and facet propagation in silicon-selective epitaxial growth

This paper reports morphological results and kinetics of the main high-density planes obtained after silicon growth on two different etched figures exhibiting the {3 1 1} and/or {1 1 1} planes. These etched profiles were generated by HCl chemical vapour etching on SiO2-patterned wafers with the (0 0 1) orientation. Deposition was performed after SiO2 removal on a full-sheet wafer with a chlorinated chemistry. Scanning electron microscope observations after silicon growth at temperatures between 700 °C and 850 °C permitted us to show that the appearance of the different facets is strongly dependent on the etch profile and on the chamber temperature. Besides that, these results permitted us to point out the difficulty in doing an acceptable silicon epitaxy on the {1 1 1} plane at low temperature (<750 °C). Moreover, we could extract the growth rates of the different high-density planes and we obtained values of activation energies associated with different populations: the values for the {1 0 0} and {1 1 1} planes are different when the {3 1 1} and {9 1 1} planes exhibit very close values.

Robustness of a Selective Epitaxial-Growth Process of Silicon and Its Application to the Fabrication of a High-Quality Hybrid SOI Wafer

Robustness of a selective epitaxial growth of silicon is demonstrated. The process window of selectivity was estimated quantitatively using the Taguchi method and signal-to-noise ratio analysis for the first time. Both the number of the silicon nuclei on the mask layer and the growth rate of silicon on a silicon substrate were investigated as the output parameters of the Taguchi method. One of the most effective process parameters for the suppression of silicon nucleation on the mask layer without retarding the growth rate of silicon is revealed to be the flow rate of SiH/sub 2/Cl/sub 2/. By calculating the number of the silicon nuclei, which could not be detected by an available measurement method, the process window of the selectivity could be determined with which a wafer with selective epitaxial silicon layer having LSI-quality could be fabricated. A high-quality silicon-on-insulator (SOI) wafer that has both an SOI region and bulk-silicon region can be obtained, and a high-quality embedded device could be realized on the SOI wafer.

Optimization of Selective Epitaxial Growth of Silicon in LPCVD

Selective epitaxial growth (SEG) of silicon has attracted considerable attention for its good electrical properties and advantages in building microstructures in high-density devices. However, SEG problems, such as an unclear process window, selectivity loss, and nonuniformity have often made application difficult. In our study, we derived processing diagrams for SEG from thermodynamics on gas-phase reactions so that we could predict the SEG process zone for low pressure chemical vapor deposition. In addition, with the help of both the concept of the effective supersaturation ratio and three kinds of E-beam patterns, we evaluated and controlled selectivity loss and nonuniformity in SEG, which is affected by the loading effect. To optimize the SEG process, we propose two practical methods: One deals with cleaning the wafer, and the other involves inserting dummy active patterns into the wide insulator to prevent the silicon from nucleating.

Fully-depleted SOI devices with TaSiN gate, HfO2 gate dielectric, and elevated source/drain extensions

We report for the first time the performance of ultrathin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS transistors using HfO/sub 2/ gate dielectric and TaSiN gate material. The transistors feature 100-150 /spl Aring/ silicon film thickness and selective epitaxial silicon growth in the source/drain extension regions. TaSiN-gate shows good threshold voltage control using an undoped channel, which reduces threshold voltage variation with silicon film thickness and discrete, random dopant placement. Device processing for CMOS fabrication is drastically simplified by the use of the same gate material for both n- and p-MOSFETs. Electrical characterization results illustrate the combined impact of using high-k dielectric and metal gate on the performance of ultrathin film FD SOI devices.

Ammonia nitrided isolation oxide for selective epitaxial growth technology to eliminate edge transistor effects of SOI and bulk N-channel MOSFETs

A simple and effective method to eliminate edge transistor effects in SOI and bulk N-channel MOSFETs, fabricated using selective epitaxial growth of silicon, is demonstrated. Employing an ammonia nitridation of the isolation oxide, before the epitaxial growth, the boron out-diffusion into the surrounding oxide is effectively suppressed. Parasitic edge transistors in both SOI and bulk N-MOSFETs are eliminated.

Low-pressure chemical vapour deposition growth of epitaxial silicon selective to silicon nitride

The selective epitaxial growth of silicon through windows in a masking material has a wide range of applications for silicon based heterostructures. For many device structures, silicon deposition selective to silicon nitride is required. A novel low-pressure chemical vapour deposition growth process has been developed for epitaxial silicon growth which is selective to silicon nitride. The influence of pressure on the epitaxial quality was investigated. Substrate wafers were heated using a resistive graphite element at 850 °C. The gas chemistry consisted of a combination of SiH 4 and SiH 2Cl 2 in a carrier gas stream of H 2 in the ratio 5:1:20, respectively. Selective growth has been demonstrated at pressures from 50 mTorr to 2 Torr on 4 in. wafers, which were patterned with a series of silicon nitride bars.

The spacer/replacer concept: a viable route for sub-100 nm ultrathin-film fully-depleted SOI CMOS

We introduce the Spacer/Replacer concept, a new concept to improve the device performance of ultrathin-film fully-depleted (FD) SOI CMOS transistors. High-performance FD SOI CMOS transistors are demonstrated with a silicon film thickness of 30 nm and physical gate-lengths down to 0.1 μm. The approach uses selective epitaxial growth of silicon to form raised source/drains while avoiding the simultaneous formation of a T-shaped poly-Si gate. In addition, the introduced concept eases the integration issues related to the ultrathin silicon film.