Security ICs Research Articles

Practical Silicon-backside-protection Method for Abnormally Detection

Nowadays, security ICs such as cryptographic modules, TPMs (Trust Platform Modules), connected car ICs, and smart card protection methods have been enhanced due to the introduction of a variety of new attack methods. Additionally, their protection mechanisms are continuously being developed and evaluated. For these reasons, attacking or hacking security chips is now more difficult than it ever has been. Nevertheless, IC failure analysis tools are being greatly improved, with many developers using them. Additionally, in using these tools, many cases involve analyzing the integrated circuit. By exploiting this analysis, attackers can perform invasive attacks [1] or hack the IC from the backside more easily than ever before. However, due to the structure of an IC, making a circuit on the back side of the silicon is more difficult than doing so on the front side. In order to resolve this issue, this paper proposes a practical silicon-backside-protection method that can protect the IC from backside attacks while minimizing its size and increasing its coverage. The proposed method uses capacitance located between the metal-layer which is unused for routing, and uses it for a passive shield (dummy shield) area.

Comparison of Requirements of Regulators of the Russian Federation and the United States of America to Automatic Control Systems of Technological Processes of Critical Objects

There are requirements for AMS TP CO based on federal laws, the presidential decree, the FSTEC decree and documents, other information security conceptions, state standards in the Russian Federation and requirements for ICS based on other security strategies, the FISMA Act, NIST, IEEE, GAO documents and others in the Unitet States of America. The main FSTEC document for information security AMS TP CO is the decree of March 14, 2014 no. 31. The main FIPS document for information security ICS is Special Publication 800-82 Rev 2. The FIPS document Special Publication 800-82 Rev 2 is more detailed than the FSTEC document in realization control levels, components, objects of ICS protection. The Special Publication includes base operations in ICS main components and enterprises network, ICS system review, USA critical object feature description. Special Publication 800-82 Rev 2 shows more quality performance than the FSTEC document. It has more pages, system descriptions, recommendation for the life cycle security system of ICS, a lot of network contents.

Dynamic differential self-timed logic families for robust and low-power security ICs

This paper describes two new dynamic differential self-timed logic families that can be used either to implement low-power security components or low-power high-speed self-timed circuits. Electrical simulations in 0.13 μm partially depleted (PD) SOI CMOS under a V dd of 1.2 V have shown that the substitution box (S-box), a module of the Khazad cipher algorithm, implemented with the improved feedback low swing current mode logic (IFLSCML) features a power consumption standard deviation almost five times smaller than that of the self-timed DDCVSL one, while consuming 37% less. On the other hand, the 8b CLA implemented with dynamic differential swing limited logic (DDSLL) features a power delay product about 19% lower than that of its counterpart implemented with self-timed DDCVSL.

AES-Based Security Coprocessor IC in 0.18-<tex>$muhbox m$</tex>CMOS With Resistance to Differential Power Analysis Side-Channel Attacks

Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$muhbox m$</tex> CMOS consisting of an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint-matching engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.

A flexible ferroelectric liquid‐crystal display with improved mechanical stability for smart‐card applications

Abstract—A bistable ferroelectric liquid‐crystal display (FLCD) for application in a smart card has been developed together with Infineon Technologies Business Unit Security and Chip Card ICs. The manufacturing process of the display will be explained. To further improve the functionality and reliability of the display, its layout has been modified. Barrier layers to reduce water permeation have been introduced. Defects in the FLC have been observed around the spacers. A change in the process order can help to avoid them. To reduce the sensitivity of the smectic layers of the FLC to shear forces, a special display layout with enlarged spacers has been developed together with an appropriate vacuum‐free filling process.