Sector Error Rate Research Articles

Reliability Evaluation of Erasure-coded Storage Systems with Latent Errors

Large-scale storage systems employ erasure-coding redundancy schemes to protect against device failures. The adverse effect of latent sector errors on the Mean Time to Data Loss (MTTDL) and the Expected Annual Fraction of Data Loss (EAFDL) reliability metrics is evaluated. A theoretical model capturing the effect of latent errors and device failures is developed, and closed-form expressions for the metrics of interest are derived. The MTTDL and EAFDL of erasure-coded systems are obtained analytically for (i) the entire range of bit error rates; (ii) the symmetric, clustered, and declustered data placement schemes; and (iii) arbitrary device failure and rebuild time distributions under network rebuild bandwidth constraints. The range of error rates that deteriorate system reliability is derived analytically. For realistic values of sector error rates, the results obtained demonstrate that MTTDL degrades, whereas, for moderate erasure codes, EAFDL remains practically unaffected. It is demonstrated that, in the range of typical sector error rates and for very powerful erasure codes, EAFDL degrades as well. It is also shown that the declustered data placement scheme offers superior reliability.

Effect of reduction of slider pitch-mode vibration on magnetic-recording performance at low-clearance head–disk interface

Aiming at improvements of both stability of slider flying and magnetic-recording performance under a low-clearance condition, a “narrow-grooved slider” was constructed and demonstrated at drive level. The proposed slider has narrow grooves on its center pad of an air-bearing surface for attaining a high-damping effect on pitch-mode resonant vibration of the air bearing. The relationship between the high-damping effect and the pitch-mode resonant vibration was studied, and the magnetic-recording performance at the lube/slider interaction regime was improved. In this study, first, flying-height modulation (FHM) of the slider was analyzed in the frequency domain by using a fast Fourier transform. Compared with the narrow-grooved slider, a non-grooved slider showed a larger increase in high-frequency modulation of gap flying height when the clearance was reduced to near “zero” at which the slider is starting to interact with lube. Furthermore, by means of drive-level experiments, sector error rate (SER) as a function of flying clearance was investigated. Under a low gap flying height condition, HDDs with the non-grooved slider showed slight SER degradation during slider/lube interaction. However, the narrow-grooved slider did not show any SER degradation at the same gap flying height; the damping effect of the narrow-grooved slider suppressed high-frequency FHM, thereby preventing SER degradation in the slider/lube interaction region.

Concatenated Low-Density Parity-Check and BCH Coding System for Magnetic Recording Read Channel With 4 kB Sector Format

In this paper, we examine the potential of applying concatenated low-density parity-check (LDPC) and Bose-Chaudhuri-Hocquenghem (BCH) coding for magnetic recording read channel with a 4 kB sector format. One key observation for such concatenated coding systems is that the overall error correction capability can be improved by exploiting the iteration-by-iteration bit error number oscillation behavior in case of inner LDPC code decoding failures. Moreover, assisted by field programmable gate array (FPGA)-based simulation platforms, empirical error-correcting performance analysis can reach a very low sector error rate (e.g., 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup> and below), which is almost infeasible for LDPC-only coding systems. Finally, concatenated coding can further reduce the silicon cost. By implementing a high-speed FPGA-based perpendicular recording read channel simulator, we investigate a 4 kB rate-15/16 concatenated coding system with a 512-byte rate-19/20 inner LDPC code and an outer 4 kB BCH code. We apply a decoding strategy that can fully utilize the bit error number oscillation behavior of inner LDPC code decoding, and show that its sector error rate drops down to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-11</sup> . For the purpose of comparison, we use the FPGA-based simulator to empirically observe the performance of 4 kB rate-15/16 LDPC and Reed-Solomon (RS) codes down to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-7</sup> -10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-8</sup> . Finally, we estimate the silicon cost of this concatenated coding system at 65 nm node, and compare it with that of the RS-only and LDPC-only coding systems.

Iterative decoding algorithm using attenuated information in PMR with bit-patterned medium

In this paper, a low-density parity check (LDPC) coding and iterative decoding system is studied in perpendicular magnetic recording (PMR) with a bit-patterned medium. We propose the efficient iterative decoding algorithm attenuating reliability information, and evaluate the sector error rate (SER) performance of the LDPC coding and iterative decoding system by R/W computer simulations. It is clarified that the proposed systems provide better SER performances than that of the conventional system at an areal density of 1 Tbit/in 2 and can also prevent the error floor which appears in the performance of conventional system.

Quasi-Cyclic LDPC Codes for the Magnetic Recording Channel: Code Design and VLSI Implementation

By implementing a field-programmable gate array (FPGA)-based simulator, we investigate the performance of randomly constructed high-rate quasi-cyclic (QC) low-density parity-check (LDPC) codes for the magnetic recording channel at very low block sector error rates. On the basis of extensive simulations, we conjecture guidelines for designing randomly constructed high-rate regular QC-LDPC codes with low error floor for the magnetic recording channel. Experimental results show that our high-rate regular QC-LDPC codes do not suffer from error floor, at least at block error rates of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> , and can realize significant coding gains over Reed-Solomon codes that are used in current practice. Furthermore, we develop a QC-LDPC decoder hardware architecture that is well suited to achieving high decoding throughput. Finally, to evaluate the implementation feasibility of LDPC codes for the magnetic recording channel, using 0.13 mum standard cell and memory libraries, we designed a read channel signal processing datapath consisting of a parallel max-log-MAP detector and a QC-LDPC decoder, which can achieve a throughput up to 1.8 Gb/s

Turbo Equalization With Single-Parity Check Codes and Unequal Error Protection Codes

The performance of turbo equalization with interleaved single-parity check codes on partial-response channels is evaluated. Single-parity check codes are weak codes, but are shown to have modest performance gain. The proposed system achieves gains of 3.5, 3.4, 2.7, and 2.4 dB with code rates of 19/20,24/25,49/50, and 63/64, respectively, at a BER of 10-5. The complexity of the proposed decoder is significantly lower than that of turbo equalization using standard low-density parity-check codes. These single-parity check codes are modified to be unequal error protection codes, designed to decrease the probability that Viterbi error events span Reed-Solomon symbol boundaries, resulting in a decrease of the sector error rate. Once such code gains an additional 0.1 dB over a single-parity check code of the same code rate of 24/25

Tensor-product Parity codes: combination with constrained codes and application to perpendicular recording

A parity code and a distance enhancing constrained code are often concatenated with a Reed-Solomon code to form a coding system for magnetic recording. The tensor-product parity coding scheme helps to improve efficiency of the parity code while retaining the same level of performance. In this paper, we present two methods for combining a tensor-product parity code with a distance-enhancing constrained code. The first method incorporates a constrained code with unconstrained positions. The second method uses a new technique, which we call word-set partitioning, to achieve a higher code rate relative to the first method. We simulate the performance of several coding systems based upon the two combination methods on a perpendicular recording channel, and we compare their symbol error rates and sector error rates with those of a system that uses only a Reed-Solomon code.

Imposing a k constraint in recording systems employing post-Viterbi error correction

A strategy for imposing a k constraint without any rate penalty is proposed for recording systems that already employ a post-Viterbi error-correction processor. Although the method is general, we focus on the application to perpendicular magnetic recording. This scheme is based on deliberate insertion of a short pattern, which contains one or more transitions and can be detected by an inner error-detection code, in the prolonged absence of magnetic transitions in the data bit pattern. The post-Viterbi processor attempts an error event correction by examining the likelihoods of a list of error events including the one due to the inserted pattern that forces the k constraint. The signal-to-noise ratio loss compared to the ideal system with k=/spl infin/ but perfect timing recovery is negligible at either a fixed bit-error rate or a fixed sector-error rate.

Nested Codes for Perpendicular Recording Channels

The performance of nested error-correction codes for perpendicular magnetic recording channels is evaluated in the presence of burst noise using Reed-Solomon codes as well as low-density parity-check codes as component codes. Erasure detection and iterative decoding algorithms for nested codes are considered, and their performance is evaluated using computer simulations. The results illustrate the advantages of the nested schemes over noninterleaved architectures in terms of sector error rate and complexity for both current and future native block sizes.

An accurate head-positioning signal for perpendicular recording using a dc-free servo pattern

We devised a dc-free servo pattern for perpendicular recording to prevent distortion of the readback wave form from the servo area. This servo pattern remarkably improves the servo sector error rate, and shows the same linearity of position error signals as does that from a conventional pattern. An experimental 2.5 in hard disk drive (HDD) with a trapezoidal-shaped single pole type (SPT) head shows good following performance within a wide range of yaw angle.

Noise predictive maximum likelihood detection combined with parity-based post-processing

The performance of magnetic recording systems that include conventional modulation codes combined with multiple parity bits is studied. Various performance measures, including bit error rate at the output of time inverse precoder, byte error probability at the input of the Reed-Solomon (RS) decoder and sector error rate, are used to evaluate the performance of various coding/detection schemes. Suboptimum detection/decoding schemes consisting of a 16-state noise-predictive maximum-likelihood (NPML) detector followed by parity-based noise-predictive post-processing, and maximum-likelihood sequence detection/decoding on the combined channel/parity trellis are considered. For conventional modulation codes, it is shown that although the dual-parity post-processor gains 0.5 dB over the single-parity post-processor in terms of bit- and byte-error-rate performance, the sector-error-rate performance of both schemes is almost the same. Furthermore, the sector-error-rate performance of optimum 64-state combined channel/parity detection for the dual-parity code is shown to be approximately 0.1 dB better than that of optimum 32-state combined channel/parity detection for the single-parity code. These performance gains can be even more substantial if appropriate coding techniques that eliminate certain error events and minimize error burst length or multiparity codes in conjunction with combined parity/channel detection are used.

Reduced-complexity decoding of low density parity check codes for generalized partial response channels

The performance of low-density parity-check (LDPC) codes serially concatenated with generalized partial response channels is investigated. Various soft-input/soft-output detection schemes suitable for use in iterative detection/decoding systems are described. A low-complexity near-optimal detection algorithm that incorporates soft-input reliability information and generates soft-output reliability information is presented. A reduced-complexity algorithm for decoding LDPC codes is described. Simulation results on the performance of high-rate LDPC codes on generalized PR channels at various recording densities are presented. These results indicate that a judicious selection of the inner detector target polynomial and the choice of a good LDPC code are important in optimizing the performance of the overall recording system. Furthermore, the results also show that iterative detection/decoding schemes using LDPC codes can outperform hard-decision decoding of Reed-Solomon codes by over 2 dB at a sector error rate of 10/sup -3/.

A compact on-chip ECC for low cost flash memories

A compact on-chip error correcting circuit (ECC) for low cost flash memories has been developed. The total increase in chip area is 2%, including all cells, sense amplifiers, logic, and wiring associated with the ECC. The proposed on-chip ECC, employing 10 check bits for 512 data bits, has been implemented on an experimental 64M-bit NAND flash memory. The cumulative sector error rate has been improved from 10/sup -4/ to 10/sup -10/. By transferring read data from the sense amplifiers to the ECC twice, 522-Byte temporary buffers, which are required for the conventional ECC and occupy a large part of the ECC area, have been eliminated. As a result, the area for the circuit has been drastically reduced by a factor of 25. The proposed on-chip ECC has been optimized in consideration of balance between the reliability improvement and the cell area overhead. The power increase has been suppressed to less than 1 mA.