Second-order Input Intercept Point Research Articles

A Wideband Noise-Canceling CMOS LNA With Enhanced Linearity by Using Complementary nMOS and pMOS Configurations

A complementary noise-canceling CMOS low-noise amplifier (LNA) with enhanced linearity is proposed. An active shunt feedback input stage offers input matching, while extended input matching bandwidth is acquired by a $\pi$ -type matching network. The intrinsic noise cancellation mechanism maintains acceptable noise figure (NF) with reduced power consumption due to the current reuse principle. Multiple complementary nMOS and pMOS configurations commonly restrain nonlinear components in individual stage of the LNA. Complementary multigated transistor architecture is further employed to nullify the third-order distortion of noise-canceling stage and compensate the second-order nonlinearity of that. High third-order input intercept point (IIP3) is thus obtained, while the second-order input intercept point (IIP2) is guaranteed by differential operation. Implemented in a 0.18- $\mu \text{m}$ CMOS process, the experimental results show that the proposed LNA provides a maximum gain of 17.5 dB and an input 1-dB compression point (IP1 dB) of −3 dBm. An NF of 2.9–3.5 dB and an IIP3 of 10.6–14.3 dBm are obtained from 0.1 to 2 GHz, respectively. The circuit core only draws 9.7 mA from a 2.2 V supply.

Using the Gate–Bulk Interaction and a Fundamental Current Injection to Attenuate IM3 and IM2 Currents in RF Transconductors

Two new linearization techniques to attenuate the second-order intermodulation (IM2) and third-order intermodulation (IM3) currents in transconductance stage of CMOS active mixers are proposed. In the first technique, the third-order Volterra kernel of the transconductance stage output current is cancelled using the interaction between the gate and bulk terminals of the input transistors. For this end, a IM2 voltage, with an adjustable magnitude and phase, is produced and applied to the bulk of these transistors. This produces an interaction term in the IM3 current of the stage and attenuates the total IM3 current. In the second technique, a fundamental component is added to the current of the tail source in the transconductance stage. This component produces an IM2 term in the drain current of the input transistors, caused by g’ m of the input transistors, with an equal magnitude and opposite phase related to the intrinsic IM2 current of the stage, and cancels the total IM2 current. Spectre-RF simulation results show that the proposed techniques simultaneously improve the third-order input intercept point and second-order input intercept point by $\sim 14.1$ and 16.4 dB, respectively, compared with the conventional active mixer, while 1.66-mA extra current is drawn from a single 1.2 V power supply.

A BROADBAND LOW POWER HIGH ISOLATION DOUBLE-BALANCED SUBHARMONIC MIXER FOR 4G APPLICATIONS

This paper presents a fully integrated broadband low power high isolation subharmonic mixer. The proposed mixer achieves a double-balanced architecture by adopting a single-to-difierential frequency-doubling technique, and improves port-to-port isolations. The mixer fabricated by tsmc 0.18m Mixed Signal CMOS process achieves maximum power conversion gain of 7.1dB, input third-order intercept point (IIP3) of i6:9dBm, input second-order intercept point (IIP2) of 33.5dBm, and single side-band noise flgure of i19:6dB over the 2.3{5.8GHz fourth generation of mobile phone communications standards (4G) frequency band. The LO-RF, LO-IF and RF-IF isolations are 82.8dB, 66.5dB and 62.3dB, respectively. The measured power consumption is 2.95mW at a 1.8V power supply.

A High-Linearity WCDMA/GSM Reconfigurable Transceiver in 0.13-$\mu\hbox{m}$ CMOS

This paper presents a dual-mode multiband transceiver with DigRF interface implemented in a 0.13-μm CMOS technology. Based on direct conversion architecture, blocks in the transceiver can be configured to simultaneously support wavelength code-division multiple access (WCDMA) band I and four Global System for Mobile Communications (GSM) bands (PCS/DCS/GSM900/GSM850). In the receiver path, the narrowband radio-frequency front-end is comprised of multiple-gated low-noise amplifiers with capacitive desensitization and current-mode passive mixers with the proposed second-order input intercept point (IIP2) calibration to comply for surface-acoustic-wave-less application. In the transmitter path, a high-linearity mixer and parallel Class-AB PA driver are adopted. Low-noise wideband frequency synthesizers with adaptive frequency calibration are proposed to cover all modes and bands. This reconfigurable transceiver achieves -5.6/-2/-6 dBm in-band third-order intercept point for WCDMA/GSM HB/GSM LB respectively, and >;65 dBm IIP2. At the maximum output power, the transmitter achieves 2.3% rms error vector magnitude for WCDMA I and 1.67° phase error for a GSM system.

Wideband CMOS Amplification Stage for a Direct-Sampling Square Kilometre Array Receiver

The design of a second amplification stage (SAS) for a highly sensitive direct-sampling receiver for the Square Kilometre Array (SKA) radio synthesis telescope is discussed. The SAS is intended to follow a Square Kilometre Array low-noise amplifier (SKA-LNA), which is being designed by others and is not a subject of this study, to obtain the high gain required from the SKA receiver. Due to the SKA ultra-low noise-temperature requirements, the SAS noise must be minimized, even though it is preceded by an SKA-LNA. The first two stages of the SAS consist of an inductorless partially noise-canceling resistive-feedback amplifier and a differential gain stage that achieve both low noise figures (NFs) and convert the single-ended input signal to a differential output. Following this, an additional gain stage is cascaded to increase the SAS gain. Over the midband SKA frequency range of 0.7-1.4 GHz, a 65-nm CMOS SAS achieves an S21 >; 34 dB, voltage gain >;36 dB, and sub-1-dB NFs (~75-K noise temperature), P1dB of >; -52 dBm, input third-order intercept point (IP3) of >;-43 dBm and input second-order intercept point (IP2) of >;-34 dBm, while consuming 96.8 mW of dc power. While the proposed SAS is not required to be input power matched, a method for matching with minimum effect on NF and gain is also presented and experimentally verified. The power match SAS achieves an S21>;26dB, voltage gain >;35 dB, and sub-1.6-dB NFs (~130-K noise temperature), input P1dB of >;-52 dBm, input IP3 of >;-44 dBm, and input IP2 of >;-34 dBm, while consuming 58.9 mW of dc power.

Broad-Band Odd-Number CMOS Prescalers With Quadrature/Symmetrical Outputs

In this brief we present two architectures for digital division by odd numbers suitable for implementation in high-speed prescalers. First, we show a technique that delivers accurate in-phase and quadrature outputs over a wide frequency range from an inherently symmetrical circuit structure, which is particularly suited to the realization of image-rejection transceiver architectures with offset local oscillator frequency. The second technique focuses on generating precise 50% duty cycle outputs, which are intended for direct mixer drive to achieve low output dc offset and second-order input intercept point. Both concepts can be realized in a wide range of logic forms. Demonstrator circuits implemented in high-speed current-mode logic have been fabricated in 0.18-m digital CMOS technology, and both techniques show robust odd-number division. The test chips consume approximately 7 mA each from a 1.8-V supply.

On the Design of Broadband Power-to-Current Low Noise Amplifiers

Aiming for the simultaneous realization of constant gain, accurate input impedance match, and minimum noise figure over a wide frequency range, the circuit topologies and detailed design of two broadband dual-loop negative feedback power-to-current low noise amplifiers (LNAs) are presented in this paper: 1) a resistive indirect-feedback power-to-current LNA, which requires an active part with two output terminal pairs, and 2) a transformer feedback power-to-current LNA, which requires a transformer in its current feedback path having a high turn ratio with high magnetic coupling. For both LNAs the feedback networks and active part implementations are discussed in detail. It is shown that for this purpose a novel stacked transformer can be realized using only two metal layers. The two LNAs are designed to be implemented in a 0.2 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu$</tex></formula> m GaAs p-HEMT technology process to verify the theory presented. Counter measures are applied to deal with the effects of bond wires and the effects of transformer parasitics on the circuit performance are analyzed. Simulation results show that the resistive indirect-feedback power-to-current LNA exhibits a 0.6–0.8 dB noise figure, an input return loss well below <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">${-}15$</tex></formula> dB, a 200 mS voltage-to-current gain (which corresponds to 23 dB power gain for a 50 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\Omega$</tex></formula> load) from 0.3 GHz to 4 GHz, a <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}1$</tex></formula> dBm third-order input intercept point (IIP3) and a 23 dBm second-order input intercept point (IIP2) at 2 GHz. It consumes 73 mA current from a 4 V power supply. The transformer-feedback power-to-current LNA achieves a 0.5–0.8 dB noise figure, an input return loss of less than <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">${-}15$</tex></formula> dB, a 22 dB power gain from 0.8 GHz to 4 GHz, and a 0 dBm IIP3 and 22 dBm IIP2 at 2 GHz while drawing 53 mA current from the 4 V power supply.

Dynamic range enhancements in radio receivers by means of frequency retranslation

In this study, a receiver architecture is presented that may be used for linearisation or for large signal interference suppression. In linearisation mode, an error signal that consists of intermodulation distortion products is obtained and used for predistorting the receiver. Experimental results demonstrate >;16 dB improvement of third-order input intercept point when used in a superheterodyne topology. When used in a direct conversion receiver topology, 7-dB improvement of second-order input intercept point is obtained. In interference suppression mode, an error signal that consists of high-level interferers spectrally close to a small wanted signal is obtained and used for predistorting the receiver. Experimental results demonstrate 14-dB enhancement of spurious-free dynamic range of the receiver.

Multiband 0.25-$\mu{\hbox {m}}$ CMOS Base Station Chips for Indirect and Direct Conversion Receivers

This paper describes a multiband CMOS chip-set for indirect and direct conversion base station receivers. The chip set consists of a low-noise amplifier (LNA), and a down-converter which includes a passive resistive mixer and a local-oscillator balun. The 0.25-mum CMOS receiver chip set, biased at 3 V, meets normal DCS1800, PCS1900, and Universal Mobile Telecommunication System (UMTS) base station specifications in heterodyne and homodyne architectures. In a heterodyne architecture, an third-order input intercept point (IIP3) higher than -5 was achieved with a noise figure (NF) lower than 4.5 dB for the complete receiver chain in the DCS1800, PCS1900, and UMTS bands. In a homodyne architecture, IIP3 and second-order input intercept point (IIP2) values better than 0 and 40 dBm, respectively, were achieved for the complete receiver chain in all three bands, with an NF of less than 6 dB. A dedicated DCS1800 heterodyne receiver based on this chip-set was developed, meeting and exceeding the specifications, with a NF of 5.8 dB and IIP3 of 0.4 dBm. This is believed to be the first CMOS receiver chip set that meets second and third-generation base station specifications in indirect and direct conversion architectures.

A New IIP2 Enhancement Technique for CMOS Down-Converter Mixers

The design of a CMOS mixer for cellular phone and 3G applications is challenging because of tough linearity and noise requirements. A new technique for second-order input intercept point (IIP2) enhancement of CMOS down-converter mixers is introduced in this brief. The technique is based on canceling second-order intermodulation components generated in input pseudodifferential transconductor, by injecting a nonlinear current to the mixer. Since this current is controlled by a high bandwidth feedback loop, the cancellation technique can be used in multistandard mixers for high channel bandwidth applications like UMTS and IEEE802.11 as well as GSM. A CMOS mixer demonstrating the performance for UMTS standard is designed in a 65-nm technology which can work with supplies as low as 1 V. The simulation results show that the differential and common mode IIP2 of the mixer are improved about 22 and 29 dB, respectively, while cancellation circuit consumes less than 3.3 mA. The other mixer parameters such as noise figure are not affected by the proposed technique.

A Low-Power RF Direct-Conversion Receiver/Transmitter for 2.4-GHz-Band IEEE 802.15.4 Standard in 0.18-$\mu{\hbox {m}}$ CMOS Technology

This paper presents a low-power RF receiver/transmitter front-end for 2.4-GHz-band IEEE 802.15.4 standard in 0.18-mum CMOS technology. An RF receiver comprises a single-ended low-noise amplifier, a quadrature passive mixer, and a transimpedance amplifier. A current-mode passive mixer showing a very good 1/f noise performance is adopted to convert an RF signal directly to a baseband signal. Moreover, this type of passive mixer shows high-linearity performance, leading to overall RF receiver linearity improvement. A low-power, high-linearity transmitter front-end is implemented by using a passive mixer and two-stage driver amplifier in which the first stage is a conventional cascode amplifier and the second stage uses a folded cascode one. The receiver front-end achieves 30-dB voltage conversion gain, 7.3-dB noise figure with 1/f noise corner frequency of 70 kHz, -8-dBm input third-order intercept point, and +40-dBm input second-order intercept point. The transmitter front-end shows 12-dB power conversion gain, 0-dBm output power with 10-dBm output third-order intercept point, and -30-dB local-oscillator suppression. The receiver and transmitter front-end dissipate 3.5 and 3 mA from a 1.8-V supply, respectively

A Fully Integrated Direct-Conversion Receiver for CDMA and GPS Applications

This paper describes a fully integrated zero-IF receiver for cellular CDMA and GPS applications. The single-chip zero-IF receiver integrates the entire signal path for CDMA and GPS bands, including a low-noise amplifier (LNA), I/Q down-converters, baseband channel selection filters (CSFs), a voltage-controlled oscillator (VCO), and a local oscillator (LO) distribution circuit for each band. The cellular-band LNA achieves a noise figure (NF) of 1.2 dB, input third-order intercept point (IIP3) of 11 dBm, and gain of 15.5 dB. Cellular I/Q down-converter and baseband circuitries show 9-dB composite NF, 9 dBm IIP3 and 60-dBm input second-order intercept point (IIP2) without IIP2 calibration. The measured LO leakage is less than <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$-$</tex> 110 dBm at LNA input. The phase noise of the cellular VCO is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$-$</tex> 134 dBc/Hz at 900-kHz offset with 1.76-GHz carrier frequency. Total GPS signal path achieves NF of 1.7 dB and gain of 74 dB with 42-mA current. The receiver is fabricated in a 0.35- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$muhboxm$</tex> SiGe BiCMOS process and packaged in a 6 mm <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$times$</tex> 6 mm 40-pin micro-lead-frame. Handset measurements report that the receiver meets or exceeds all of the CDMA-2000 requirements .

A Direct Conversion Receiver With an IP2 Calibrator for CDMA/PCS/GPS/AMPS Applications

A second-order intercept point (IP2) calibration technique is developed using common-mode feedback (CMFB) circuitry in a direct-conversion receiver for wireless CDMA/PCS/GPS/AMPS applications. The IP2 calibrator is capable of providing different CMFB gain to tune its common-mode output impedance for each of the positive and negative mixer outputs. The CDMA mixer applying this method achieved a second-order input intercept point (IIP2) of 64 dBm, a third-order input intercept point (IIP3) of 4 dBm, a noise figure of 6.5 dB and a voltage gain of 42.2 dB. This result shows a 20 dB improvement from an uncalibrated IIP2 of 44 dBm. The receiver RFIC is implemented in a 0.5-mum SiGe BiCMOS process, and it operates from a 2.7 to 3.1 V single power supply

A 5.25-GHz CMOS folded-cascode even-harmonic mixer for low-voltage applications

This paper presents a 5.25-GHz folded-cascode even-harmonic mixer (FEHM) for low-voltage applications. This FEHM employs the folded technique to reduce the headroom voltage, a current reuse circuit in the RF stage to improve its linearity, and the frequency-doubling technique in the local oscillator (LO) stage to produce an LO double-frequency signal. In addition, the proposed technique exhibits the advantage of high conversion gain. In order to demonstrate the benefits and optimize the circuit design, the theoretical studies of conversion gain, linearity, and noise performance are described. For measurement, the proposed FEHM possesses conversion gain of 8.3 dB, third-order input intercept point (IIP/sub 3/) of 0.03 dBm, and second-order input intercept point (IIP/sub 2/) of 31.2 dBm under the supply voltage of 0.9 V and LO power of 5.5 dBm. The power consumption of the proposed mixer is about 4.95 mW at an IF frequency of 500 kHz.

A low-power CMOS direct conversion receiver with 3-dB NF and 30-kHz flicker-noise corner for 915-MHz band IEEE 802.15.4 ZigBee standard

A low-power low flicker-noise receiver front-end for 915-MHz-band IEEE 802.15.4 standard in 0.18-/spl mu/m CMOS technology is implemented. A power-constrained simultaneous noise and input matching low-noise amplifier (LNA) can be achieved by using a conventional inductive degeneration cascode amplifier with an extra gate-source capacitor. In combination with the LNA, a passive mixer showing low 1/f noise performance is adopted to convert the RF signal directly to the baseband signal. The measured results show a conversion gain of 30 dB and a noise figure of 3 dB with 1/f noise corner frequency of 30 kHz. Two-tone test measurements indicate -5-dBm input third-order intercept point and +45-dBm input second-order intercept point. The RF receiver front-end dissipates 2 mA from a 1.8-V supply.

Nonlinear Analysis of Bipolar Harmonic Mixer for Direct Conversion Receivers

An even-harmonic mixer using a bipolar differential pair (bipolar harmonic mixer;BHMIX) is theoretically analyzed from the direct conversion point of view; i.e, conversion gain, third-order input intercept point (IIP3), self-mixing induced dc offset level, and second-order input intercept point (IIP2). Also, noise are analyzed based on nonlinear large-signal model, and numerical results are given. Noises are treated as cyclostationary noises, thus all the folding effects are taken into account. Factors determining IIP3, IIP2, dc offset, and noise are identified and estimation procedures for these characteristics are obtained. For example, design guidelines for the optimal noise performance are given. Measured results support all the analysis results, and they are very useful in the practical BHMIX design.

An Si-SiGe BiCMOS direct-conversion mixer with second-order and third-order nonlinearity cancellation for WCDMA applications

This paper presents a general analysis of the third-order nonlinearity of a differential common-emitter RF amplifier and an improved technique to cancel the third-order nonlinearity. A thorough analysis of the mechanisms leading to the second-order nonlinearity of bipolar double-balanced active mixers is also presented. An SiGe BiCMOS WCDMA direct-conversion mixer is designed based on the third- and the second-order cancellation schemes. The mixer achieves +6-dBm third-order input intercept point, +49-dBm second-order input intercept point, 16-dB gain and 7.2-dB double-sideband noise figure with only 2.2-mA current at 2.1 GHz.

A single-chip multimode receiver for GSM900, DCS1800, PCS1900, and WCDMA

A single-chip, multimode receiver for GSM900, DCS1800, PCS1900, and UTRA/FDD WCDMA is introduced in this paper. The receiver operates at four different radio frequencies with two different baseband bandwidths. The presented chip uses a direct-conversion architecture and consists of a low-noise amplifier (LNA), downconversion mixers with on-chip local-oscillator I/Q generation, channel selection filters, and programmable gain amplifiers. In spite of four receive bands, only four on-chip inductors are used in the single-ended LNA. The repeatable receiver second-order input intercept point (IIP2) of over +42 dBm is achieved with mixer linearization circuitry together with a baseband circuitry having approximately +100-dBV out-of-band IIP2. The noise figure of the SiGe BiCMOS receiver is less than 4.8 dB in all GSM modes, and 3.5 dB in WCDMA. The power consumption from a 2.7-V supply in all GSM modes and in WCDMA mode is 42 and 50 mW, respectively. The silicon area is 9.8 mm/sup 2/ including the bonding pads.

Second-order intermodulation mechanisms in CMOS downconverters

An in-depth analysis of the mechanisms responsible for second-order intermodulation distortion in CMOS active downconverters is proposed in this paper. The achievable second-order input intercept point (IIP2) has a fundamental limit due to nonlinearity and mismatches in the switching stage and improves with technology scaling. Second-order intermodulation products generated by the input transconductor or due to self-mixing usually contribute to determine the IIP2 even though they can, at least in principle, be eliminated. The parasitic capacitance loading the switching-stage common source plays a key role in the intermodulation mechanisms. Moreover, the paper shows that, besides direct conversion and low intermediate frequency (IF), even superheterodyne receivers can suffer from second-order intermodulation if the IF is not carefully chosen. The test vehicle to validate the proposed analysis is a highly linear 0.18-μm direct-conversion CMOS mixer, embedded in a fully integrated receiver, realized for Universal Mobile Telecommunications System applications.

Calibration techniques of active BiCMOS mixers

This paper describes calibration techniques for downconversion mixers used in integrated direct-conversion receivers. A method of achieving a high even-order intermodulation rejection is presented. Using the method presented, the receiver second-order input intercept point (IIP2) can always be improved by more than 20 dB. The minimum achieved receiver IIP2 after calibration is +38 dBm. A technique to enhance the I/Q-amplitude balance between the quadrature channels is also introduced. A single-balanced adjustable mixer is implemented as a part of a prototype direct-conversion receiver. The receiver chip consists of a low-noise amplifier, mixers and calibration circuitry, a divide-by-two circuit, local oscillator (LO) buffers for LO generation, and active baseband filters. The chip is fabricated using a 0.35-/spl mu/m SiGe BiCMOS process and is characterized at 900 MHz.