Abstract

In this brief we present two architectures for digital division by odd numbers suitable for implementation in high-speed prescalers. First, we show a technique that delivers accurate in-phase and quadrature outputs over a wide frequency range from an inherently symmetrical circuit structure, which is particularly suited to the realization of image-rejection transceiver architectures with offset local oscillator frequency. The second technique focuses on generating precise 50% duty cycle outputs, which are intended for direct mixer drive to achieve low output dc offset and second-order input intercept point. Both concepts can be realized in a wide range of logic forms. Demonstrator circuits implemented in high-speed current-mode logic have been fabricated in 0.18-m digital CMOS technology, and both techniques show robust odd-number division. The test chips consume approximately 7 mA each from a 1.8-V supply.

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