Second-order Sigma-delta Modulator Research Articles

A 96 dB DR Second-Order CIFF Delta-Sigma Modulator with Rail-to-Rail Input Voltage Range

A second-order delta-sigma modulator (DSM) is proposed for readout integrated circuits of sensor applications requiring a small area and low-power consumption. The proposed second-order CIFF DSM with the architecture of cascaded-of-integrator feedforward (CIFF) basically consists of two integrators, a 3-bit quantizer, data-weighted averaging (DWA) circuit, and clock generator. The use of the 3-bit quantizer instead of the single-bit quantizer reduces the size of the feedback capacitor in the first integrator. The 3-bit quantizer is designed based on a successive approximation register analog-to-digital converter for small area and low power implementation. Furthermore, the proposed second-order CIFF DSM has a single supply without an additional reference driver while having a wide analog input voltage range with rail to rail. The proposed second-order CIFF DSM, implemented using a 130 nm 1-poly 6-metal CMOS process with a supply of 1.5 V, has an area of 0.096 mm2. It has a sampling frequency of 500 kHz for the implementation of an input bandwidth of 2 kHz and an oversampling ratio of 125. The measured peak signal-to-noise and distortion ratio is approximately 90 dB when the differential analog input signal has a frequency of 353 Hz and an amplitude of 1.2 Vpp. The measured dynamic range is approximately 96.3 dB.

A Reconfigurable 12-to-18-Bit Dynamic Zoom ADC With Pole-Optimized Technique

This paper presents a resolution-reconfigurable discrete-time dynamic zoom analog-to-digital converter (ADC) with a 20-kHz bandwidth. It employs a coarse 6-bit successive approximation register (SAR) ADC that dynamically updates the references for the post-stage single-bit second-order delta-sigma modulator to obtain a higher resolution with lower power. The sampling rate of the proposed ADC can be configured to be 1.6, 3.2, 6.4 and 10-MS/s such that four resolution modes, including 12, 14, 16 and 18-bit, can be provided accordingly. Note that pole locations of the noise transfer function (NTF) vary with different OSR’s, and noise-shaping effect, together with the power efficiency, can be degraded. To solve this issue, the pole-optimization technique is proposed in this paper. In this way can the pole locations be reconfigured according to the specific OSR. Additionally, the bandwidths of the operational amplifiers are also modulated in different oversampling ratio (OSR) scenarios to further improve the energy efficiency. Fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> m CMOS process, the prototype occupies 1.01 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . On condition of an OSR of 250, the proposed ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 102.8 dB, while dissipating 1.3 mW.

Low power delta sigma capacitor conversion circuit

To accurately measure the micro capacitance, a kind of capacitance conversion circuit that uses a second-order Sigma-Delta modulation technique is introduced, and the measuring range of inductive capacitance is extended by a 4-bit DAC capacitor. The loop oscillator is used to provide the modulator with a 16 kHz square wave signal. Because the circuit has a built-in clock generation circuit, no external clock signal is required outside the chip. Chopping technology is used to reduce the impact of 1/f noise on circuit performance. This capacitance conversion circuit is based on the SMIC 0.18um process, simulated and verified with cadence, MATLAB and other tools. The circuit achieves a capacitance range from 0 to 35pF and consumes 25μA from a 1.2V single supply. The conversion time for one measurement is 15ms, during which the resolution is 4fF and good linearity is achieved.

A 121 dB SNDR Zoom ADC Using Dynamic Amplifier and Asynchronous SAR Quantizer

This paper presents a discrete-time zoom analog-to-digital converter (ADC) for low-bandwidth high-precision applications. It uses a coarse-conversion 5-bit asynchronous self-timed SAR ADC combined with a fine-conversion second-order delta-sigma modulator to efficiently obtain a high signal-to-noise distortion ratio (SNDR). An integrator circuit using a high-gain dynamic amplifier is proposed to achieve higher SNDR. The dynamic amplifier uses a switched tail current source to operate periodically, simplifying the common-mode feedback circuit, reducing unnecessary static current, and improving the PVT robustness. Dynamic error correction techniques, such as redundancy, chopping, and dynamic element matching (DEM) are used to achieve low offset and high linearity. And a 2-bit asynchronous SAR quantizer with an embedded feed-forward adder is used in the second-order delta-sigma modulator to reduce the quantization noise caused by redundancy, and further achieve higher energy efficiency. Simulation results show that the ADC achieves a peak SNDR of 121.1 dB in a 390 Hz bandwidth at a 200 kHz sampling clock while consuming only 170 μW from a 2.5 V supply and the core area is 0.55 mm2. This results in a Schreier figure of merit (FoM) of 184.7 dB.

Image sequence decomposition via sigma-delta cellular neural network having coupled cells

In this paper, an image sequence decomposition by the sigma-delta cellular neural network (SD-CNN) with coupled cells and its composition framework is proposed. The SD-CNN, having coupled cells inspired by the second-order sigma-delta modulator, is employed for image sequence decomposition, and it enables effective image decomposition by the effects of complex dynamics. In our method, pixel luminance is described by the number of spikes within a discrete time window that corresponds to the number of SD-CNN iterations. For efficient image decomposition, a high luminance which requires a long time window, should be compensated. To solve this problem, we introduce the cumulated luminance integrator enables compensating a high luminance even with a short time window. Experimental results on various test images in the Kodak dataset and the Waterloo dataset support that all the test images can be mathematically lossless reconstructed from an image sequence decomposed via our method. It is also confirmed that the proposed method improves transmission efficiency for the Kodak dataset by approximately 80%, which is an issue with our previous method.

A Switched-Capacitor, Integrator-Multiplexing, Second-Order Delta-Sigma Modulator Featuring a Single Differential Difference Amplifier for Portable EEG Application

We present a novel switched-capacitor, integrator-multiplexing, second-order delta-sigma modulator (DSM) featuring a single differential difference amplifier (DDA). Power consumption is low and resolution is high when this DSM is used for portable electroencephalographic applications. A single DDA (rather than a conventional operational transconductance amplifier) with appropriate switch and capacitor architectures is used to create the second-order switched-capacitor DSM. The configuration ensures that the resolution is high. The modulator was implemented using a standard 180 nm complementary metal–oxide–silicon process. At a supply voltage of 1.8 V, a signal bandwidth of 250 Hz and a sampling frequency of 200 kHz, simulations demonstrated that the modulator achieved an 82 dB peak signal-to-noise–distortion ratio and an effective number of bits of 14.

A Single-Bit Incremental Second-Order Delta-Sigma Modulator with Coarse-Fine Input Buffer

This paper presents an incremental second-order delta-sigma modulator with a coarse-fine input buffer in 180-nm CMOS. The modulator’s architecture was implemented as a second-order cascade of integrators with a feedback structure. The switched-capacitor integrator was operated in discrete time, with high-gain amplifiers required to achieve improved performance during the integration phase. The amplifier comprised rail-to-rail input and gain-boosted cascode intermediate stages, thus achieving a high gain and wide input voltage range. The circuit adopts a coarse-fine buffer for higher performance. The coarse buffer is operated first to enable fast settling through a high slew rate, followed by the fine buffer to satisfy the low-noise and high-accuracy characteristics. The fine buffer has a smaller current consumption with higher power efficiency. The experiment results show that the proposed input buffer achieved a 13.14 effective number of bits and an 80.87 dB signal-to-noise and distortion ratio. The modulator operates a single bit and sampling clock at 125 kHz. The proposed delta-sigma modulator was operated at 1.8 V. The proposed circuit was designed using a standard 0.18-μm CMOS process with an active area of 1.06 mm2. The total current consumption with the coarse-fine buffer was 1.374 mA.

An Improved Low-EMI Fast-Transient-Response Buck Converter Suitable for Wireless Sensor Networks With New Transient Accelerated Techniques

This paper proposed an improved low-electromagnetic-interference (EMI), high-efficiency fast-transient-response buck converter suitable for wireless sensor networks with new transient accelerated techniques. The proposed second-order delta-sigma modulator used the noise-shaping technique and the oversampling theorem to reduce the electromagnetic interference of the output spectrum. And then added the transient acceleration loop to accelerate the transient response also lowers the undershoot and overshoot voltage when the load current changed. The proposed converter has been implemented with TSMC <inline-formula> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> 1P6M process, and the chip area is <inline-formula> <tex-math notation="LaTeX">$1.19 \times 1.19$ </tex-math></inline-formula> mm² (including PADs). The measured results show that when the output voltage is 2 V and the load current changes from 100 mA to 500 mA and from 500 mA to 100 mA, the transient responses are <inline-formula> <tex-math notation="LaTeX">$4 ~\mu \text{s}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$3 ~\mu \text{s}$ </tex-math></inline-formula>, and transient voltages are 18 mV and 30 mV, respectively. Compared to the traditional continuous-time delta-sigma-modulation converter improved <inline-formula> <tex-math notation="LaTeX">$3 ~\mu \text{s}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$7 ~\mu \text{s}$ </tex-math></inline-formula>. The maximum output voltage ripple is 30 mV. The output-to-noise ratio (ONR) is 72.15 dB with the sampling frequency of 10 MHz. When the load current is 100 mA and the output voltage is 2.5 V, the peak efficiency is 90.8&#x0025;.

A Low-Power Opamp-Less Second-Order Delta-Sigma Modulator for Bioelectrical Signals in 0.18 µm CMOS.

This article reports on a compact and low-power CMOS readout circuit for bioelectrical signals based on a second-order delta-sigma modulator. The converter uses a voltage-controlled, oscillator-based quantizer, achieving second-order noise shaping with a single opamp-less integrator and minimal analog circuitry. A prototype has been implemented using 0.18 μm CMOS technology and includes two different variants of the same modulator topology. The main modulator has been optimized for low-noise, neural-action-potential detection in the 300 Hz–6 kHz band, with an input-referred noise of 5.0 μVrms, and occupies an area of 0.0045 mm2. An alternative configuration features a larger input stage to reduce low-frequency noise, achieving 8.7 μVrms in the 1 Hz–10 kHz band, and occupies an area of 0.006 mm2. The modulator is powered at 1.8 V with an estimated power consumption of 3.5 μW.

Ultrasensitive Magnetic Sensors Enabled by Heterogeneous Integration of Graphene Hall Elements and Silicon Processing Circuits.

Graphene Hall elements (GHEs) have been demonstrated to be promising magnetic field sensors with excellent sensitivity, linearity, temperature stability, and compatibility with complementary-metal-oxide-semiconductor (CMOS)-integrated circuits (ICs). However, the demonstrated GHEs have still not exhibited a comprehensive advantage in performance over commercial integrated Hall sensors which were implemented in integrated Hall element and CMOS processing ICs. In this work, we develop a technology for the three-dimensional (3D) heterogeneous integration of silicon-based CMOS ICs and GHEs, and the fabricated magnetic field sensors outperform commercial high-end integrated Hall sensors. Specifically, the integrated Hall sensors are implemented in a stacked integration on Si based on a chopper programmable-gain amplifier (CPGA), a chopper-stabilized second-order sigma-delta modulator (CSDM), and graphene-based Hall elements on monochips. GHEs with high sensitivity (up to 1000 A/VT) are fabricated with a compatible process on a smoothened silicon nitride passivation layer of silicon-based CMOS ICs, and the two device layers are connected by an interlayer. The heterogeneous integrated Hall ICs exhibit current and voltage magnetic sensitivities up to 64 000 A/VT and 6.12 V/VT, respectively, which are much higher than those in all other reported nanomaterial-based Hall sensors and even in high-end commercial Hall ICs. Furthermore, the 3D heterogeneous integration technology used here can be extended as a universal technology for integrating nanomaterial-based sensors and Si CMOS ICs.

Slewing Mitigation Technique for Switched Capacitor Circuits

Slewing in switched capacitor (SC) circuits reduces the available time for linear settling, and hence increases the nonlinear settling error. This transient demand in current can be supplied by making the bias currents larger in the operational transconductance amplifier (OTA). However, this increases the static power consumption significantly. In this paper a slewing mitigation technique is presented where just the right amount of charge is provided at the switching instant to the SC circuit so that OTA does not need to provide high peak current. This may eliminate slewing altogether, and allows using OTAs with less static current for the same settling accuracy. The operation of the proposed technique is illustrated by incorporating it in a second-order delta-sigma modulator (DSM). The modulator was designed and simulated in a 65nm CMOS process. Post-layout extracted simulations with optimized design show more than 12 dB improvement in signal to noise and distortion ratio (SNDR) for the same static power. Alternatively, compared to a DSM without such technique, the same performance can be achieved with 30% less power.

A low-power second-order sigma-delta modulator for MEMS digital geophones

This paper presents a low-power second-order sigma-delta modulator (SDM) for micro-electromechanical systems (MEMS) digital geophones (DGPs). The proposed SDM optimizes the performance of the first stage integrator and uses an adaptive class-AB current recycling operational transconductance amplifier (OTA) to improve the current efficiency. In addition, gain-enhancing circuits are applied in the OTA to increase the DC gain, and the chopper technique is used in the first stage integrator to reduce the flicker noise. The proposed SDM was implemented in the SMIC 0.18 μm CMOS technology and occupies an area of 0.82 mm2. The simulation results reveal the signal-to-noise ratio (SNR) was 76.46 dB and the effective number of bit (ENOB) was 12.4 bits. Measurements show that the SNR was 57.5 dB and the ENOB was 9.26 bits with a sampling rate of 256 kHz, an oversampling ratio 128, and a signal bandwidth of 1 kHz. The proposed SDM has a supply voltage of 1.8 V and a power consumption of 193.5 μW, which is suitable for the low-power MEMS DGPs applications.

A 6.6-μW Wheatstone-Bridge Temperature Sensor for Biomedical Applications

This letter presents a compact, energy-efficient, and low-power Wheatstone-bridge temperature sensor for biomedical applications. To maximize sensitivity and reduce power dissipation, the sensor employs a high-resistance (600 $\text{k}\Omega $ ) bridge that consists of resistors with positive (silicided-poly) and negative ( $n$ -poly) temperature coefficients. Resistor spread is then mitigated by trimming the $n$ -poly arms with a 12-bit DAC, which consists of a 5-bit series DAC whose LSB is trimmed by a 7-bit PWM generator. The bridge is readout by a second-order delta–sigma modulator, which dynamically balances the bridge by tuning the resistance of the silicided-poly arms via a 1-bit series DAC. As a result, the modulator’s bitstream average is an accurate and near-linear function of temperature, which does not require further correction in the digital domain. Fabricated in a 180-nm CMOS technology, the sensor occupies 0.12 mm2. After a 1-point trim, it achieves +0.2 °C/−0.1 °C ( $3{\sigma }$ ) inaccuracy in a ±10 °C range around body temperature (37.5 °C). It consumes 6.6 ${\mu }\text{W}$ from a 1.6-V supply, and achieves 200- ${\mu }\text{K}$ resolution in a 40-ms conversion time, which corresponds to a state-of-the-art resolution FoM of 11 fJ $\cdot \text{K}^{2}$ . Duty cycling the sensor results in even lower average power: 700 nW at 10 conversions/s.

A Scalable Four-Channel Frequency-Division Multiplexing MIMO Radar Utilizing Single-Sideband Delta–Sigma Modulation

A scalable four-channel multiple-input multiple-output (MIMO) radar that features a modular system architecture and a novel frequency-division multiplexing approach is presented in this article. It includes a single 30-GHz voltage-controlled oscillator (VCO) for the local oscillator signal generation, four cascaded 120-GHz transceivers with a frequency quadrupler, and on-board differential series-fed patch antennas. The utilized uniform antenna configuration results in 16 virtual array elements and enables an angular resolution of 6.2°. The vector modulators in the transmit (TX) paths allow the application of complex bit streams of second-order delta-sigma modulators easily generated on a field-programmable gate array (FPGA) to implement single-sideband (SSB) modulation on the TX signals resulting in orthogonal waveforms for the MIMO operation. Only one phase-locked loop and no digital-to-analog converter is required. The waveform diversity also allows the simultaneous transmission of the TX signals to reduce the measurement time. The application of the SSB modulation on the frequency-modulated continuous-wave MIMO radar requires only half of the intermediate frequency bandwidth compared with the double-sideband modulation. The issue of the phase and amplitude mismatches at the virtual array elements due to the scalable radar architecture is addressed and a calibration solution is introduced in this article. Radar measurements using different numbers of virtual array elements were compared and the digital-beamforming method was applied to the results to create 2-D images.

A Charge-Sharing-Based Two-Phase Charging Scheme for Zero-Crossing-Based Integrator Circuits

As an effort to improve the energy efficiency of switched-capacitor circuits, zero-crossing- based integrators (ZCBI) that consist of zero-crossing detectors and charging circuits have been proposed. To break the trade-off between accuracy and speed, ZCBI typically employs a two-phase charging scheme that relies on an additional threshold for zero-crossing detection. This paper proposes a simpler realization method of the two-phase charging scheme by means of charge sharing. To demonstrate feasibility of the proposed method, we designed and fabricated a second-order delta-sigma modulator in 180-nm complementary metal–oxide–semiconductor (CMOS) technology. The measurement results show that the modulator exhibits a peak signal-to-noise-and-distortion ratio (SNDR) of 46.3 dB over the bandwidth of 156 kHz with the power consumption of 684 µW. We also designed the same modulator in 65-nm CMOS technology and simulation results imply that the proposed circuit is able to achieve a much better energy efficiency in advanced technology.

A second-order continuous-time delta-sigma modulator with double self noise coupling

In this paper, a second-order continuous-time delta-sigma modulator using double self noise coupling technique is proposed. Noise coupling increases the effective order of the noise shaping loops. The presented architecture splits the outputs of the quantizer into a most significant bit segment (MSBs) and a least significant bit segment (LSBs). The LSBs can be viewed as the residue after the MSBs quantization and is fed back to the front of the quantizer and the second integrator respectively, as a result, double self noise coupling is achieved. In addition, the quantizer also provides a convenient means to incorporate the excess-loop-delay compensation. As a result, the digital noise cancellation logic complexity is simplified, the digital and analog filter mismatch is relaxed, meanwhile, it strictly suppresses the noise within the effective signal bandwidth by reducing the main MSBs mismatch. Finally, the resolution is increased, the hardware complexity and the output swing of the integrator are reduced, which greatly relaxes the bandwidth and gain requirement of the Op-Amp design. The higher order noise shaping introduced by the residue of multi-bit quantizer further reduces the quantization noise.

Performance Appraisal of Sigma Delta Modulated Radio over Fiber System

Abstract Radio over fiber (RoF) is a promising solution for the next-generation wireless networks including fifth-generation Cloud/Centralized Radio Access Network (C-RAN). There exists a possibility to use Sigma Delta Modulated RoF (S-DRoF) that combines the advantages of analog RoF and digital RoF by means of sigma delta modulation (SDM) at the transmitter side subsequently replacing the employment of expensive and high-speed digital-to-analog converters. In this paper, we demonstrate the usage of second-order SDM for LTE 20 MHz signal having 64 QAM modulation on a central carrier frequency of 1.14 GHz for the implementation of S-DRoF for 20 km of standard single mode fiber with baud rate from 25 to 100 Mbaud. Furthermore, a comprehensive analysis of the design of SDM is explained followed by the experimental setup. The performance is reported in terms of error vector magnitude, constellations and adjacent channel power ratio. The results show that the proposed architecture performance is in with accordance to the limitations set by the 3GPP (Third Generation Partnership Project) standards and is a reasonable choice either for upgrading installed systems as well as for the new deployments.

A Low-Electromagnetic-Interference Buck Converter With Continuous-Time Delta-Sigma-Modulation and Burst-Mode Techniques

This paper presents a high-efficient low-noise buck converter with continuous-time delta-sigma-modulation and burst-mode techniques. The proposed buck converter uses the techniques of over-sampling, noise shaping, burst mode, and continuous-time second-order delta-sigma modulator to achieve low output noise, low overshoot and undershoot voltage, and improve the recovery time. First, the second-order DSM can lower the switching frequency noise, overshoot, and undershoot of the converter. Second, the noise shaping technique can move the noise to high frequency and filter out the noise within bandwidth. Third, the burst-mode technique can accelerate the transient response. The proposed chip is fabricated with a 0.35 μ m Taiwan Semiconductor Manufacturing Company (TSMC) CMOS process and the chip area is 1.5 × 1.5 mm. The transient recovery time is 6 and 16 μ s, when the load current changes from 600 to 50 mA and from 50 to 600 mA, respectively. The output noise spectrum is –67.5 dbm, when output voltage is 2 V. The maximum efficiency is 91.6%, when the output voltage is 2 V. The supply voltage is 3.3 V. The output voltage range of the proposed converter is 1–2.5 V.

Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator

A second-order sigma delta modulator that uses an operational transconductance amplifier as integrator and latch comparator as quantizer. The proposed technique where a low power high gain OTA is used as integrator and another circuit called dynamic latch comparator with two tail transistors and two controlling switches are used to achieve high speed, low power and high resolution in second order delta sigma modulator. It enhances the power efficiency and compactness of the modulator by implementing these blocks as sub modules. A second order modulator has been designed to justify the effectiveness of the proposed design. Technology 180nm CMOS process is used to implement complete second order continuous time sigma delta modulator. We introduce the sub threshold three stage OTA, which is a way of achieving low distortion operation with input referred noise at 1 KHz is equal to the 2.2647pV/ and with low power consumption of 296.72nW. A high-speed, low-voltage and a low-power Double-Tail dynamic comparator is also proposed. The proposed structure is contrasted with past dynamic comparators. In this paper, the comparator’s delay will be investigated and systematic analysis are inferred. a novel comparator using two tail transistor is proposed, here circuitry of a customized comparator having two tail is changed for low power dissipation and also it operates fast at little supply voltages. By maintaining the outline and by including couple of transistors, during the regeneration strengthening of positive feedback can be maintained, this results in amazingly diminished delay parameter. It is investigated that in proposed design structure of comparator using two tail transistors, power consumption is reduced and delay time is also diminished to a great extent. The proposed comparator is having maximum clock frequency that is possibly expanded up to 1GHz at voltages of 1 V whereas it is dissipating 10.99 µW of power, individually. By using sub threshold three stage OTA and dynamic standard two tail latch comparator, designed second order sigma delta ADC will consume 29.95µW of power.

A High-Resolution 2-GHz Fractional-N PLL With Crystal Oscillator PVT-Insensitive Feedback Control

This letter presents a 2-GHz fractional-N phase-locked loop (PLL) with a high-precision delta–sigma digital-to-analog converter (DAC) to overcome the frequency deviation of a crystal oscillator due to manufacturing process, supply voltage, and temperature (PVT). The delta–sigma DAC with high power efficiency and linearity consists of a second-order delta–sigma modulator, a finite impulse response filter, and a low-pass filter. With the proposed PLL architecture, the frequency resolution can be lower than a few thousands of pulse per minute. The PLL is implemented in a 0.13- $\mu \text{m}$ 1P6M CMOS process. With temperature from −40 °C to 80 °C, the measured results of 15 chips show that the frequency deviation of output frequency in PVT decreases from 1 to 0.002 ppm. The phase noise of PLLs is less than −126 dBc/Hz at 1-MHz offset at a carrier frequency of 1.99 GHz. The rms period jitter is below 1 ps at 1.99 GHz, while consuming a total power of no more than 10 mW.