Schottky Tunneling Source Research Articles

Ge field-effect transistor with asymmetric metal source/drain fabricated on Ge-on-Insulator: Schottky tunneling source mode operation and conventional mode operation

An asymmetric Schottky tunneling source field-effect transistor (STS FET) is a prospective device structure to suppress the short-channel effect. Recently, we succeeded in the fabrication and operation of a Ge-STS n-channel FET with TiN and PtGe asymmetric metal source/drain (S/D) on a bulk Ge substrate. However, the Ge-STS p-channel FET has not been demonstrated yet. In this study, we fabricated an asymmetric metal S/D FET with the same S/D structure on a bulk Ge and a Ge-on-Insulator (GOI) substrate. The GOI was made by using the Smart-CutTM technique. The device fabricated on a bulk Ge did not operate. On the other hand, the fabricated FET on a GOI, which has a taper-shaped TiN/Ge source interface, showed STS p-FET behavior. These results suggest that the carrier injection can be improved by the optimization of the device structure. As an auxiliary effect, conventional metal-oxide-semiconductor (MOS) FET operation was also observed, thanks to GOI introduction. We demonstrated both STS mode and MOSFET mode operation in the same device on GOI.

Comparative Analysis of T-Gate and L-Gate Dielectric Modulated Schottky Tunneling Source Impact Ionization MOS for Label-Free Detection of Toxic Gases

Comparative Analysis of T-Gate and L-Gate Dielectric Modulated Schottky Tunneling Source Impact Ionization MOS for Label-Free Detection of Toxic Gases

Fabrication of asymmetric Ge Schottky tunneling source n-channel field-effect transistor and its characterization of tunneling conduction

An asymmetric Schottky tunneling source field-effect transistor (STS FET) is a prospective device structure to suppress the short channel effect and to reduce the off-state current. An obstacle to implement a STS FET with a high mobility Ge channel was to form a metal/Ge contact with a low electron barrier height (ΦBN). Recently, we succeeded in the fabrication of a TiN/Ge contact with an extremely low ΦBN. In this study, a Ge-STS n-channel FET was fabricated, here PtGe/Ge and TiN/Ge contacts were used as the source and the drain. The device showed well-behaved transistor operation. From the current-voltage measurements in the wide temperature range of 160–300K, the conduction mechanism from the source to the channel is confirmed to be field emission tunneling. This result will be the first step toward achieving a high-performance Ge-STS n-FET.

Label-free biosensor using nanogap embedded dielectric modulated schottky tunneling source impact ionization MOS

In this paper, we have investigated a novel nanogap embedded dielectric modulated schottky tunneling source impact-ionization MOS (DM-STS-IMOS) for highly sensitive, real-time label-free electrical detection of bio-molecules. The current gating mechanism of STS-IMOS is governed by cumulative effect of both impact ionization and source induced tunneling. Both of these mechanisms are synergistically leveraged for pathogenic biomolecule sensors design scheme. Technology computer-aided design (TCAD) simulation study is deployed to provide physical insight into the working mechanism and performance estimation of the proposed sensor. DM-STS-IMOS exhibits enhanced sensitivity and as the operating voltage of DM-STS-IMOS is lower than the conventional IMOS, it has significantly enhanced reliability and higher power efficiency. The length of the nanogap is recognized as a potential parameter to optimize the device sensitivity. It demonstrates dominant dielectric modulation effects, easy recovery mechanism and higher sensitivity even at smaller channel lengths. It can also be exploited in array-based screening and in-vivo bio-species diagnostics.

Analytical modeling of Schottky tunneling source impact ionization MOSFET with reduced breakdown voltage

In this paper, we have investigated a novel Schottky tunneling source impact ionization MOSFET (STS-IMOS) to lower the breakdown voltage of conventional impact ionization MOS (IMOS) and developed an analytical model for the same. In STS-IMOS there is an accumulative effect of both impact ionization and source induced barrier tunneling. The silicide source offers very low parasitic resistance, the outcome of which is an increment in voltage drop across the intrinsic region for the same applied bias. This reduces operating voltage and hence, it exhibits a significant reduction in both breakdown and threshold voltage. STS-IMOS shows high immunity against hot electron damage. As a result of this the device reliability increases magnificently. The analytical model for impact ionization current (Iii) is developed based on the integration of ionization integral (M). Similarly, to get Schottky tunneling current (ITun) expression, Wentzel–Kramers–Brillouin (WKB) approximation is employed. Analytical models for threshold voltage and subthreshold slope is optimized against Schottky barrier height (ϕB) variation. The expression for the drain current is computed as a function of gate-to-drain bias via integral expression. It is validated by comparing it with the technology computer-aided design (TCAD) simulation results as well. In essence, this analytical framework provides the physical background for better understanding of STS-IMOS and its performance estimation.

Circuit-Level Performance Evaluation of Schottky Tunneling Transistor in Mixed-Signal Applications

Schottky tunneling source FET (STSFET) is a promising device alternative for future nanometer-scale technology. This paper presents a circuit-level performance evaluation of using STSFET for mixed-signal circuit applications, as well as a design approach that can guide circuit designers to use STSFET optimally. A switched-capacitor track-and-hold amplifier is chosen as a test vehicle, and circuit-level power-performance tradeoff is examined when STSFET is incorporated into the existing array of device types in 90-nm CMOS process. To quantitatively explore the design tradeoff, this paper employs an automated circuit optimization framework using geometric programming, a special type of convex optimization problem. Numerical analysis shows that for our test bench circuit, introducing STSFET, when compared to using devices in 90-nm CMOS process, leads to 30%-50% power reduction, depending on the performance specifications. The analysis also reveals that the full benefit of using STSFET can only be achieved by judiciously choosing device types in a given circuit structure, and the optimal device type selection for a mixed-signal circuit can often be blended using both conventional devices and application-specific devices.

Systhesis and Devices of Graphene

Graphene is of great interest of being a channel material in MOSFETs because of its ultra high mobility and large carrier densities. In this paper, several synthesis methods of graphene are introduced and Graphene channel FETs (Gra-FETs) are fabricated. Heavily doped n-type or p-type PolySi is adopted as source and drain to form Schottky tunneling junctions with graphene and successfully suppresses the ambipolar conduction which is caused by graphene's intrinsic properties. The total drain current is dominated by either electron or hole tunneling current and thus showing a unipolar relationship with VG. We demonstrated the Gra-FETs with Schottky tunneling source and drain and proved experimentally that these devices would have only one kind of carriers to conduct current and thus the ambipolar conduction is suppressed.

Asymmetric Schottky Tunneling Source SOI MOSFET Design for Mixed-Mode Applications

Schottky barrier MOSFETs have recently attracted attention as a viable alternative to conventional CMOS transistors for sub-65-nm technology nodes. An asymmetric Schottky tunneling source SOI MOSFET (STS-FET) is proposed in this paper. The Schottky tunneling source SOI MOSFET has the source/drain regions replaced with silicide as opposed to highly doped silicon in conventional devices. The main feature of this device is the concept of a gate-controlled Schottky barrier tunneling at the source. The device was optimized with respect to various parameters such as Schottky barrier height and gate oxide thickness. The optimized device shows excellent short channel immunity, compared to conventional SOI MOSFETs. The asymmetric nature of the device has been shown to improve the leakage current as well as the linear characteristics of the device as compared to conventional Schottky FETs. The STS-FET was fabricated, using conventional processes combined with the present NiSi technology and large angle implantation, and successfully demonstrated. The high immunity to short channel effects improves the scalability, and the output resistance of the device also makes it an attractive candidate for mixed-mode applications.

ASYMMETRIC TUNNELING SOURCE MOSFETS: A NOVEL DEVICE SOLUTION FOR SUB-100NM CMOS TECHNOLOGY

The paper presents a simulation study of the physics and performance of novel asymmetric tunneling solutions for the sub-100nm MOSFET technology. Two device structures have been investigated: Schottky Tunneling Source MOSFET and band-to-band P +- N + Tunneling Source MOSFET. The Schottky MOSFET exhibits degraded Ion and subthreshold swing (in spite of improved DIBL). On the other hand, the novel PNPN MOSFET shows high Ion/Ioff and steep subthreshold behavior.