Circuit-Level Performance Evaluation of Schottky Tunneling Transistor in Mixed-Signal Applications

Abstract

Schottky tunneling source FET (STSFET) is a promising device alternative for future nanometer-scale technology. This paper presents a circuit-level performance evaluation of using STSFET for mixed-signal circuit applications, as well as a design approach that can guide circuit designers to use STSFET optimally. A switched-capacitor track-and-hold amplifier is chosen as a test vehicle, and circuit-level power-performance tradeoff is examined when STSFET is incorporated into the existing array of device types in 90-nm CMOS process. To quantitatively explore the design tradeoff, this paper employs an automated circuit optimization framework using geometric programming, a special type of convex optimization problem. Numerical analysis shows that for our test bench circuit, introducing STSFET, when compared to using devices in 90-nm CMOS process, leads to 30%-50% power reduction, depending on the performance specifications. The analysis also reveals that the full benefit of using STSFET can only be achieved by judiciously choosing device types in a given circuit structure, and the optimal device type selection for a mixed-signal circuit can often be blended using both conventional devices and application-specific devices.