Schottky Barrier Metal Oxide Semiconductor Research Articles

Dual operation modes of the Ge Schottky barrier metal–oxide–semiconductor field-effect transistor

A germanium p-channel Schottky barrier metal–oxide–semiconductor field-effect transistor (SB-MOSFET) with germanium–platinum Schottky contacts is demonstrated experimentally. The fabrication process has a low thermal budget of 450° C and requires neither intentional doping nor ion implantation. At a temperature of 4 K, the p-channel SB-MOSFET turns on at a gate voltage of −1.6 V and shows a peak mobility of 500 cm2/V s at a carrier density of 3 × 1012 cm–2. Under high drain–source bias voltages, the device operates in an unconventional mode where the current is limited by the source contact. Injection of carriers from the source contact to the germanium channel is controlled by the gate bias, which modulates the Schottky barrier capacitively. The transconductance in this mode deviates from and is significantly higher than the value expected for a conventional MOSFET with the same geometry, mobility, and capacitance. Based on four-point current–voltage measurements, we present a theoretical band diagram of the device and give a physical picture for the observed high currents and transconductances.

A 10 nm Asymmetric Graphene–Rhenium Disulfide Field‐Effect Transistor for High‐Speed Application

Field‐effect transistor devices with exfoliated 2D materials are potent in various optical and electronics applications including photodetectors, valleytronics, spintronic, circuits, memory, and optical modulators. However, these devices endure limited gate control, low carrier mobility, and high operating voltage. This study introduces a new asymmetric graphene–rhenium disulfide heterojunction Schottky barrier metal–oxide–semiconductor field‐effect transistor engineered with high graphene carrier mobility and high rhenium disulfide Ion–off ratio in a 10 nm channel‐length device. The proposed device has better gate control ability, Ion–off ratio of 106, high carrier mobility (87.44 cm2 V−1 s−1), and low subthreshold swing of 43.12 mV dec−1 in the subthreshold region at 0.05 V applied drain voltage. The significant reduction in subthreshold swing at low voltage opens a suite of high‐switching‐speed low‐powered nanologic applications for the upcoming Internet‐of‐Things era. The material properties of graphene–rhenium disulfide heterojunctions are derived using an ab initio quantum transport simulation tool.

A planar Al-Si Schottky barrier metal–oxide–semiconductor field effect transistor operated at cryogenic temperatures

Schottky Barrier-MOSFET technology offers intriguing possibilities for cryogenic nano-scale devices, such as Si quantum devices and superconducting devices. We present experimental results on a device architecture where the gate electrode is self-aligned with the device channel and overlaps the source and drain electrodes. This facilitates a sub-5 nm gap between the source/drain and channel, and no spacers are required. At cryogenic temperatures, such devices function as p-MOS Tunnel FETs, as determined by the Schottky barrier at the Al-Si interface, and as a further advantage, fabrication processes are compatible with both CMOS and superconducting logic technology.

Measurement of Schottky barrier height tuning using dielectric dipole insertion method at metal–semiconductor interfaces by photoelectron spectroscopy and electrical characterization techniques

Schottky barrier height (ΦSBH) tuning from the insertion of dipole providing materials at the TaN/Si and TaN/GaAs interface are investigated using photoelectron spectroscopy and electrical techniques. In-situ processing and characterization of these contact interfaces is utilized to gain understanding of the formation of the dipole at the AlOx/SiO2 interface. Changes in both the band bending and vacuum work function by the insertion of AlOx/SiO2 at the interface are observed on both Si and GaAs substrates and are correlated with a large reduction in the ΦSBH on Si. Applications of this contact scheme for contact resistivity reduction, extremely shallow junctions, and Schottky barrier metal–oxide–semiconductor field effect devices are also discussed.

UV Responsive Characteristics of n-Channel Schottky Barrier MOSFET with ITO as Source/Drain Contacts

Abstract We fabricated a schottky barrier metal oxide semiconductor field effect transistor(SB-MOSFET) by applying indium-tin-oxide(ITO) tothe source/drain on a highly resistive GaN layer grown on a silicon substrate. The MOSFET, with 10
um gate length and 100
um gatewidth, exhibits a threshold gate voltage of 2.7 V, and has a sub-threshold slope of 240 mV/dec taken from the I DS -V GS characteristics at alow drain voltage of 0.05 V. The maximum drain current is 18 mA/mm and the maximum transconductance is 6 mS/mm at V DS =3 V. Weobserved that the spectral photo-response characterization exhibits that the cutoff wavelength was 365 nm, and the UV/visible rejectionratio was about 130 at V DS = 5 V. The MOSFET-type UV detector using ITO, has a high UV photo-responsivity and so is highlyapplicable to the UV image sensors. Keywords : Highly resistive GaN, Schottky Barrier MOSFET, ITO, UV responsivity 1. INTRODUCTION Gallium nitride(GaN) is one of the most promisingmaterials for both opto-electronic devices, such as highsensitive ultraviolet(UV) detector, visible light emissiondiode(LED) and high temperature / high frequency / highpower electronic devices, such as high electron mobilitytransistor(HEMT)[1-3], metal insulator semiconductorfield effect transistor(MISFET)[4, 5].At least until recently, there has not been much interestin enhancement mode transistors, even though there aremany applications for integrated UV image sensors as wellas high power logic integrated circuit applications.Schottky barrier source/drain(S/D) structure MISFET andsilicon implanted S/D MISFET have been presented in [6]and [7], respectively. The schottky barrier S/D is anattractive solution because it excludes the use of the highcost S/D ion implantation process and very hightemperature activation at over 1500 \C[1]. Indium-tin-oxide(ITO), on the other hand, has been widely applied tomany other opto-electronic devices because of its highlyconductive and visible-transparent properties[8].In this study, we investigated both the electrical and theUV responsive characteristics of a fabricated enhancementmode n-channel SB-MOSFET using ITO schottky barrierS/D on a highly resistive GaN layer grown on a siliconsubstrate in the near UV and visible regions for the variousgate/drain bias conditions. The fabricated devices exhibitvery promising behaviors, such as a very high on/offcurrent ratio, high transconductance, and a goodUV/visible rejection ratio.

Quantum compact model for thin-body double-gate Schottky barrier MOSFETs

Nanoscale Schottky barrier metal oxide semiconductor field-effect transistors (MOSFETs) are explored by using quantum mechanism effects for thin-body devices. The results suggest that for small nonnegative Schottky barrier heights, even for zero barrier height, the tunnelling current also plays a role in the total on-state current. Owing to the thin body of device, quantum confinement raises the electron energy levels in the silicon, and the tradeoff takes place between the quantum confinement energy and Schottky barrier lowering (SBL). It is concluded that the inclusion of the quantum mechanism effect in this model, which considers an infinite rectangular well with a first-order perturbation in the channel, can lead to the good agreement with numerical result for thin silicon film. The error increases with silicon thickness increasing.

Impact of Gate Overlap on Performance of Schottky Barrier Metal–Oxide–Semiconductor Field-Effect Transistors Including Gate Induced Barrier Lowering Effect

In this study, we analyzed the impact of gate overlap on the performance of Schottky barrier metal–oxide–semiconductor field-effect transistors (SB MOSFETs) including the gate induced barrier lowering (GIBL) effect by two-dimensional (2D) full-band self-consistent ensemble Monte Carlo (EMC) simulation. Results show that the GIBL effect and gate overlap affect drive current significantly. The GIBL effect relieves the degradation of current drivability caused by overlap. However, the influence of scattering on the performance of SB MOSFETs is almost negligible since the electrons across the channel are nearly ballistic.

Ambipolar Carrier Injection Characteristics of Erbium-Silicided n-Type Schottky Barrier Metal–Oxide–Semiconductor Field-Effect Transistors

Erbium-silicided 50-nm-gate-length n-type Schottky barrier metal–oxide–semiconductor field-effect transistors (SB-MOSFETs) with a 5 nm gate oxide thickness are manufactured. Their on/off-current ratio is higher than 105 with low leakage current less than 10 nA/um. The abnormal increase of drain current with a negative gate voltage is explained by the hole carrier injection from drain into the channel. In SB-MOSFETs, ambipolar carriers, i.e., electrons and holes, can be injected into the channel depending on gate voltage polarity.

Impact of the channel thickness on the performance of Schottky barrier metal–oxide–semiconductor field-effect transistors

We present quantum simulations of single-gated Schottky barrier metal–oxide–semiconductor field-effect transistors on ultrathin silicon on insulator. The electrostatics of such devices is investigated and the influence of the silicon thickness on the Schottky barriers at the source and drain and, thus, the influence on the current–voltage characteristics are elaborated. We show that decreasing the channel layer thickness leads to a strong reduction of the Schottky barrier thickness and thus to an increased gate control of the drain current. The use of ultrathin channel layers improves the off- as well as the on state of such transistors and results in electrical characteristics comparable with conventional metal–oxide–semiconductor field-effect transistors.

Electron transport measurements of Schottky barrier inhomogeneities

We report nonmonotonicities in the low-temperature current versus gate voltage characteristics of PtSi/Si Schottky Barrier metal–oxide–semiconductor field-effect transistors. Direct tunneling through the Schottky barrier is shown to limit the current and be superimposed with resonant peaks and oscillations. These structures are attributed to resonant tunneling through impurities located close to the interface and nonuniformities of the heterojunction. We thus demonstrate barrier height variations in electron transport through a relatively large metal/semiconductor contact area. The inhomogeneities result in different average Schottky barrier heights between devices, and cause height variations as a function of carrier concentration within a metal/semiconductor interface.

Suppression of leakage current in Schottky barrier metal–oxide–semiconductor field-effect transistors

In this article we investigate the subthreshold behavior of PtSi source/drain Schottky barrier metal–oxide–semiconductor field-effect transistors. We demonstrate very large on/off ratios on bulk silicon devices and show that slight process variations can result in anomalous leakage paths that degrade the subthreshold swing and complicate investigations of device scaling.

Self-Assembly CoSi2-Nanostructures for Fabrication of Schottky Barrier MOSFETs on SOI

AbstractA new self-assembly patterning method for generation of epitaxial CoSi2 nanostructures was used to fabricate 70 nm gate-length Schottky barrier metal oxide semiconductor field effect transistors (SBMOSFETs) on silicon-on-insulator (SOI) substrates. This technique involves only conventional optical lithography and standard silicon processing steps. It is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal processing. The strain field is generated along the edges of a mask consisting of 20 nm SiO2 and 300 nm Si3N4. Single-crystalline CoSi2 layers grown by molecular beam allotaxy (MBA) on thin SOI substrates were patterned using this technique. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. During the RTON-step a 6 nm thin SiO2 is formed on top of the gap which is used as a gate oxide. The SBMOSFETs can be driven as both p-channel and n-channel devices without complementary substrate doping and show good I-V characteristics.