Circuit Scheme Research Articles

Nodal State Comparison-based Dynamic Hold Technique for Low Power OR Gates in Domino Logic

This paper presents a novel circuit technique NSCDH, to construct OR gates with 8 inputs up to 128 inputs and single output, which can be cascaded to further stages. It uses stage isolation technique to provide current free nodal state comparison with the ability to hold circuit at an optimal state, thereby resulting in 44.6% lesser power consumption and 16.1% higher noise immunity at 8 inputs as compared to CDDK (2019) and 24.4% lesser power consumption at 128 inputs as compared to CDDK (2019). Circuit simulation is done using HSpice. Standard BSIM4 90 nm PTM file is used to model NMOS and PMOS transistors. Circuit schematic is made using LT Spice. OR gates built using this technique can be used in many applications as multiplexers, read–write data paths, memories, and adders.

Selective Auto-Reclosing of Mixed Circuits Based on Multi-Zone Differential Protection Principle and Distributed Sensing

Environmental concerns and economic constraints have led to increasing installations of mixed conductor circuits comprising underground cables (UGCs) and overhead transmission lines (OHLs). Faults on the OHL sections of such circuits are usually temporary, while there is a higher probability that faults on UGC sections are permanent. To maintain power system reliability and security, auto-reclose (AR) schemes are typically implemented to minimize outage duration after temporary OHL faults while blocking AR for UGC faults to prevent equipment damage. AR of a hybrid UCG–OHL transmission line, therefore, requires effective identification of the faulty section. However, the different electrical characteristics of UGC and OHL sections present significant challenges to existing protection and fault location methods. This paper presents a selective AR scheme for mixed conductor circuits based on the evaluation of differential currents in multiple defined protection zones, using distributed current transformer (CT) measurements provided by passive optical sensing. Case studies are conducted with a number of different UGC–OHL configurations, and the results demonstrate that the proposed scheme can accurately identify the faulty section, enabling effective selective AR of a comprehensive range of mixed conductor circuit topologies. The proposed scheme is also more cost effective, with reduced hardware requirements compared to conventional solutions. This paper thereby validates the optimal solution for mixed circuit protection as described in CIGRE Working Group B5.23 report 587.

Design of an Oil-Immersed Pulse Modulator for X-Band 50-MW Klystron

This article presents a compact high-voltage pulse modulator used for a 50-MW <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$X$</tex-math> </inline-formula> -band pulsed klystron (11.4 GHz) at Shanghai Advanced Research Institute, Chinese Academy of Sciences (SARI, CAS). The pulse modulator includes a ten-section pulse-forming network (PFN), protection circuits, a thyratron module, and a pulse transformer. To reduce the volume of the pulse modulator and maintain the system stability, an oil-immersed tank is proposed to insulate the main electronic components, which leads to a volume reduction of 65%. The modulator is designed with a peak pulse voltage of 427 kV, a peak pulse current of 304 A, a repetition rate of 50 Hz, and a flat-top pulsewidth of 1.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> s. The circuit schematic is provided, while the design criteria of the main components and mechanical structure are discussed. The experimental results and measurements show the design and hardware to be capable of fulfilling the requirements.

Multiband Magnetless Isolators and Circulators With Reconfigurable Bandpass Filtering Capabilities

This article reports on the RF design and practical validation of new classes of magnetless multiband isolators and circulators with reconfigurable bandpass filtering capabilities. They are based on transversal frequency-selective signal paths shaped by frequency-tunable and spatiotemporally modulated resonators. Each path creates a passband that can be independently controlled in terms of frequency and direction of propagation. Thus, the overall network may exhibit 1-to- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> frequency-reconfigurable non-reciprocal passbands. The operating principles and schematic of the magnetless and reconfigurable filtering isolator concept are first demonstrated through circuit-based simulations of two- and three-path transversal filtering networks (i.e., two- and three-band networks). The independent modulation parameters of the bands are determined through detailed parametric analyses. Next, the concept is extended to the design of magnetless, multiband filtering circulators. The operating and design principles of the circulator are expounded through a circuit schematic and an ideally simulated dual-band example. For practical demonstration purposes, three lumped-element (LE) prototypes, two isolators, and one circulator, shaped by two or three RF signal paths (i.e., two and three passbands), were implemented at very high frequency (VHF) band. They exhibited a maximum in-band isolation (IS) up to 50 dB. Moreover, a frequency tuning of up to 1.22:1 and change of directionality are achieved.

An Interface ASIC Design of MEMS Gyroscope with Analog Closed Loop Driving.

This paper introduces a digital interface application-specific integrated circuit (ASIC) for a micro-electromechanical systems (MEMS) vibratory gyroscope. The driving circuit of the interface ASIC uses an automatic gain circuit (AGC) module instead of a phase-locked loop to realize a self-excited vibration, which gives the gyroscope system good robustness. In order to realize the co-simulation of the mechanically sensitive structure and interface circuit of the gyroscope, the equivalent electrical model analysis and modeling of the mechanically sensitive structure of the gyro are carried out by Verilog-A. According to the design scheme of the MEMS gyroscope interface circuit, a system-level simulation model including mechanically sensitive structure and measurement and control circuit is established by SIMULINK. A digital-to-analog converter (ADC) is designed for the digital processing and temperature compensation of the angular velocity in the MEMS gyroscope digital circuit system. Using the positive and negative diode temperature characteristics, the function of the on-chip temperature sensor is realized, and the temperature compensation and zero bias correction are carried out simultaneously. The MEMS interface ASIC is designed using a standard 0.18 μM CMOS BCD process. The experimental results show that the signal-to-noise ratio (SNR) of sigma-delta (ΣΔ) ADC is 111.56 dB. The nonlinearity of the MEMS gyroscope system is 0.03% over the full-scale range.

Hadamard product-based in-memory computing design for floating point neural network training

Deep neural networks (DNNs) are one of the key fields of machine learning. It requires considerable computational resources for cognitive tasks. As a novel technology to perform computing inside/near memory units, in-memory computing (IMC) significantly improves computing efficiency by reducing the need for repetitive data transfer between the processing and memory units. However, prior IMC designs mainly focus on the acceleration for DNN inference. DNN training with the IMC hardware has rarely been proposed. The challenges lie in the requirement of DNN training for high precision (e.g. floating point (FP)) and various operations of tensors (e.g. inner and outer products). These challenges call for the IMC design with new features. This paper proposes a novel Hadamard product-based IMC design for FP DNN training. Our design consists of multiple compartments, which are the basic units for the matrix element-wise processing. We also develop BFloat16 post-processing circuits and fused adder trees, laying the foundation for IMC FP processing. Based on the proposed circuit scheme, we reformulate the back-propagation training algorithm for the convenience and efficiency of the IMC execution. The proposed design is implemented with commercial 28 nm technology process design kits and benchmarked with widely used neural networks. We model the influence of the circuit structural design parameters and provide an analysis framework for design space exploration. Our simulation validates that MobileNet training with the proposed IMC scheme saves in energy and in time versus the same task with NVIDIA GTX 3060 GPU. The proposed IMC design has a data density of 769.2 Kb mm−2 with the FP processing circuits included, showing a 3.5 × improvement than the prior FP IMC designs.

Miniaturized retractable thin-film sensor for wearable multifunctional respiratory monitoring.

Supplementary material (additional figures and movies, including the production process of respiratory monitoring straps, the mechanical analysis of RSPS, RTF-TENG versus vector TENG sensors, the simulation studies of TE-TENG and FT-TENG, the additional characterization of RTF-TENG, the tensile and robustness tests of RSPS, the characterizations of the MWRMS during different sleeping positions, detailed circuit schematic of the MWRMS, the displacements and phase relations of RSPS, MWRMS for multifunctional respiratory monitoring) is available in the online version of this article at 10.1007/s12274-023-5420-1.

The Co-Design of Broadband Diplexer and Quasi-Reflectionless Lowpass/Highpass TFIPD Filter Chip

A new ultra-miniaturized 5G N78 and N79 diplexer based on GaAs Thin Film Integrated Passive Device (TFIPD) technology is proposed in this brief. By a NiCr thin film resistor, the quasi-reflectionless lowpass/highpass filter can also be achieved on the same circuit structure without any increase of size. Circuit schematic is composed of serial-parallel inductances and capacitances, which generates out-of-band transmission zeros. The proposed design provides <2 dB insertion loss and >15 dB out-of-band rejection. Therefore, the GaAs-based TFIPD technology can support low-loss, high-precision, and miniaturized design desires of 5G radio-frequency (RF) front-end devices. Chip model is demonstrated through EM simulation, wafer fabrication, and measurement.

High-Gain Bidirectional LCLC Resonant Converter With Reconfigurable Capability

A reconfigurable gain circuit is proposed for an <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LCLC</i> resonant converter with bidirectional capability considering wide varying redox flow battery source. A suitable hybrid control scheme for <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LCLC</i> resonant converter with secondary synchronous rectifier is proposed in this work. The proposed reconfigurable circuit enables to configure secondary bridge as an active voltage doubler, full-bridge circuit during forward power transfer mode and reverse power transfer mode, respectively. The reconfigurability helps significantly to design a transformer with lower secondary turns and achieve desired high gain. The reduced transformer secondary turns result in reduced transformer parasitics. The presence of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LCLC</i> resonant tank helps to provide the additional gain; the hybrid control scheme ensures zero-voltage switching turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> for the primary, and secondary synchronous <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfets</small> throughout the operating range. The proposed converter is analysed using fundamental harmonic approximation. The proposed reconfigurable gain circuit and hybrid control scheme is verified experimentally for an 800 V/1 kW hardware prototype fed from 24 to 54 V input.

Design of high-performance triboelectric-piezoelectric hybridized mechanical energy harvester inspired by three-phase asynchronous generator

Hybridized nanogenerators harvesting ambient mechanical energy via multiple energy conversion mechanisms is attractive for the development of next-generation energy sources. However, existing devices are still restricted in device size, structure complexity, power circuit and energy utilization scheme. Herein, inspired by the principle of three-phase asynchronous generator, we designed a triboelectric-piezoelectric hybridized mechanical energy harvester (HMEH) that tightly combines triboelectric and piezoelectric components in all-in-one package. Through the strategy of three-phase full-wave rectifier and integration of triboelectric/piezoelectric components with similar impedance to optimize the power extraction, one HMEH device can deliver remarkable outputs of 810 V and 0.65 mA at excitation frequency of 0.5 Hz, and even up to 1.10 mA at 4.0 Hz. The device also can endure 40,000 contact-separation cycles stability tests with no device failure and little outputs decay, demonstrating its excellent durability and reliability. The power density of this HMEH device approaches a high value of 1.02 mW cm−2 among similar contact-separation mode HNGs reported to date. Scalable performance of ∼4 mA can be obtained through the 2 × 2 HMEH arrays, supplying power for a smart band in sensing of heart rate and transmitting data wirelessly. The continuous charging of supercapacitor and lithium battery through HMEH arrays are demonstrated, providing extended energy utilization schemes for pulse-power and constant-power types electronics. This work can provide new insights in designing high-performance hybridized mechanical energy harvester and facilitate the development of power-generating technologies in further real-life applications, such as smart road infrastructures, wearable electronics and large-scale blue energy.

Practical reusable garbled circuits with parallel updates

The central contribution of the current paper is to establish a practical and effective reusable garbled circuit scheme with parallel updates, where each update is applied to the circuit in parallel. First of all, we present a strengthened notion of inner product functional encryption (IPE) called simulation-based security (SIM-security) for multi-instance and show that a secret-key IPE scheme is multi-instance SIM-secure. Then we put forward a reusable garbled circuit scheme based on the IPE scheme. The idea is a reduction from re-randomizable garbled circuits in which the distribution of the original garbled circuit is computationally indistinguishable from the re-randomized garbled circuit. Finally, we implemented reusable garbled circuits and validate the practicality of our reusable garbled circuit scheme. Experimental results demonstrate that our reusable garbled circuit scheme is suitable for a wide range of real-world scenarios.

Chaos in a nonlinear Lorentz-Lu-Chen system via the fractal fractional operator of Atangana-Baleanu

This paper establishes the presence or absence of chaotic behaviors in the nonlinear modified Lorentz-L\\\"{u}-Chen using the Atangana-Baleanu fractal-fractional operators. Moreover, we investigate the impact of the fractal-fractional operators on the system\'s behavior and provide insights into the underlying dynamics. Fixed point theory proves the Lorentz-L\\\"{u}-Chen existence and uniqueness under this operator. Furthermore, we applied a numerical power series method to solve the proposed models. To illustrate the applicability and efficiency of this suggested method, numerical examples are provided. To verify the results provided in this paper, a circuit schematic has been drawn and simulated.

RESEARCH OF FEED-PUSHER ROBOTS’ STRUCTURAL-AND-TECHNOLOGICAL PARAMETERS

On a modern robotic farm, at feed distributing process, it is necessary a feed pusher robot using. The EU countries are the leader of such structures’ introducing. Today, 15 of feed pusher robots’ manufacturers offer 21 models. Based on their analysis, the feed pushing robots’ classification was developed. The main structural-and-technological indicators are revealed: their mass is in the range from 500 till 750 kg; the working speeds range from 5,9 to 18 m/min.; the movement’s specific power varies from 0,08 till 1,46 W/kg.; the robot’s body performs 3 revolutions per minute; two AKB batteries with a 12 V voltage, connected in according to the 24 V circuit scheme, with 200 A*h as their total capacity or more are used. The most interest and research perspective promise feed pusher robots with an active working body: a screw and a conveyor belt one. These feed pusher robots with an active working body in the screw’s form of DeLaval OptiDuo and Butler Gold have screws’ diameters of 635 and 660 mm; the step of the turns is 282 and 256 mm; the screws’ length is 1053 and 1117 mm; the driving wheels’ diameter is 390 and 430 mm; the loading window’s width is 1053 and 1158 mm respectively. These values are commensurate. The overall’s dimensions differ significantly - length (in 1672 and 1930 mm) and height (in 931,5 and 777 mm). The data obtained as a study result can be used as new feed pusher robots’ designs, as well as in the APK enterprises selection for particular model in their MTP to be included.

Development of a neural network model for the mechanical properties prediction of aluminum alloys during die casting with crystallization under pressure

A specialized software based on a neural network model is developed, which makes it possible to predict the hardness of aluminum alloys, the crystallization of which proceeds under conditions of comprehensive compression at a pressure of 500 MPa and with a change in the percentage of chemical elements. The object of control is the crystallizing metal. Theoretical provisions that allow correctly training a neural network are considered. A schematic circuit of the casting process with crystallization under pressure is developed, the initial data for neural network modeling and the activation function of neurons are selected. A model and an algorithm for searching for a neural network are developed, a listing of the program code, which includes the functions of normalizing values, sampling the neural network, visualization, and graph comparison operations is adduced. Verification of the program operation, which allows predicting the mechanical properties of products from aluminum alloys, is carried out by an experimental method. Is revealed that the developed neural network is able to predict the hardness of parts from aluminum alloys with a minimum error. The training sample, supplemented with new experimental data, went through the process of information treatment on the constructed neural network model. Keywords neural network model, automation, control, specialized software, aluminum alloys, pressure, crystallization, hardness

Rancangan Bangun Sistem Pendeteksi Kebocoran Gas LPG Menggunakan Nodemcu ESP866 Berbasis Internet

Abstract: This study aims to determine the design of an LPG gas leak detection system using Internet-based Nodemcu ESP866. LPG gas cylinders are an essential kitchen fuel for most people. In preparing the research, the authors first collected data by conducting a literature study to find out the schematic circuit, component datasheet, and how the components work. Based on statistical data from the fire department from January 2010 to August 24, 2010, there were 46 fire incidents in the DKI Jakarta area, with an estimated material loss of Rp. and many materials. With the results, we get from our tool. Namely, the Buzzer as an alarm, the LED as an indicator, and the DC Fan can be On when the sensor detects a leak in the gas cylinder. In conclusion, the tool can be integrated with a smartphone using Wifi. In testing the device, the measurement range is 5-30 meters. At a distance of 5 meters, it produces 4.76, and at a distance of 10 meters, the time difference is around 2 seconds slower for smartphones to receive notifications. At a distance of 20 meters, it produces 7.66 seconds; at a distance of 30 meters, the time difference is 2.5 seconds slower for smartphones to receive notifications.&#x0D; &#x0D; Keywords: NodeMCU Esp8266, Internet Of Things, Buzzer, Smartphone

Internet of Things-Based Entrepreneurship Lockers

The development of the internet, which was originally only a medium of communication, is now more varied and sophisticated. An example of the development of the internet is Internet Of Things (IoT) , which in this study will discuss the implementation of IoT. As a form of pandemic recovery for IoT entrepreneurial activities, researchers developed lockers that can help entrepreneurial actors (especially on campus) to get up during the recovery period from the pandemic. The general concept of this locker is that the seller puts his merchandise into the locker and the buyer will pick it up by paying through QRIS. In other words, this locker provides convenience in transactions because it is done cashless. The design begins with making the work steps and logic flow of the locker which then makes the circuit scheme of the hardware. The hardware circuits used have their respective roles and support each other. This research hopes that with the IoT-based entrepreneurial lockers, it is expected not only to help partners / entrepreneurial actors on campus, but also attract new partners and encourage campus residents to dare to be entrepreneurs.

Modeling of the Payload Signal Generator of the UAV Radio Transmitter based on the Phase Distortion Autocompensator

A block diagram of a payload signal generator of a UAV radio transmitter with an autocompensator for phase distortion of a digital computational synthesizer with improved spectral characteristics compared to known solutions is considered. Schematic diagrams and circuit design models of the main paths of the shaper in the Micro-Cap environment with the analysis of the characteristics of the necessary radio elements and microcircuits have been developed. The simulation of the device operation in the frequency domain is carried out. Based on the simulation results, the conditions for selecting the parameters of the shaper to achieve the greatest compensation of phase distortions are formulated.

Reliability Improvement of Voltage Regulator Modules by a Virtual Series Voltage Source

Output voltage deviation is a key performance index of voltage regulator modules (VRMs) with consecutive load transients. Usually, a large-capacity filter capacitor bank is used in VRMs to reduce the voltage deviation and stabilize the output voltage during transients. However, capacitors are one of the most vulnerable links in power electronic converters. For reliability reasons, it is essential to reduce the capacitance requirement while guaranteeing the transient performances of VRMs. Focusing on this, many efforts have been made to optimize the design of VRMs, where the transient auxiliary circuit-based scheme is a popular one. Unfortunately, there exists a large number of additional components in the existing auxiliary circuits. Considering this issue, in this article, we present a virtual series voltage source (VSVS) based auxiliary circuit scheme, which has minimum component counts. By using a controlled coupled inductor as the VSVS, the proposed scheme enables VRMs to have a relatively small transient voltage overshoot and without needing large bulk capacitance. Moreover, considering different control schemes with the same designing aim, the number and the electrothermal stress of critical components (e.g., capacitors) of VRMs are different; it is difficult to compare directly their advantages and disadvantages. Regarding this issue, this article investigates the converter-level reliability of VRMs with different control schemes. Taking a 12–3.3 V VRM as a case study, the reliability benchmarking results illustrate that the proposed scheme can significantly improve the reliability of VRMs.

Low-Noise Potentiostat Readout Circuit with a Chopper Fully Differential Difference Amplifier for Glucose Monitoring

This paper presents a low-noise potentiostat readout circuit with a chopper fully differential difference amplifier (FDDA) for glucose monitoring. Glucose monitoring is necessary for the early diagnosis of diabetes complications and for health management. Ammeter electrochemical sensors are widely used for glucose detection, and in general, a three-electrode structure of a reference electrode (RE), a counter electrode (CE), and a working electrode (WE) is implemented with a potentiostat structure. A low-noise characteristic of the readout circuit is essential for highly accurate glucose monitoring. The chopping technique can reduce low-frequency noises such as 1/f noise and can achieve the required low-noise characteristic. The proposed potentiostat readout circuit is based on a low-noise chopper FDDA with a class-AB output stage. The implementation of the chopper FDDA scheme of the potentiostat readout circuit can decrease the number of amplifiers in the control part of the potentiostat, with reduced power consumption and a wide dynamic output range. The negative feedback loop of the inverting amplifier scheme with the FDDA maintains the voltage between the WE and RE constants. The negative feedback loop tracks the reference voltage of the RE with an input voltage of the WE. The proposed potentiostat readout circuit is designed in the standard 0.18 µm CMOS process, and the simulated current consumption is 48.54 μA with a 1.8 V power supply. The simulated input-referred noise level was 8.53 pArms.

Design of Ternary Logic Circuits using Pseudo N-type CNTFETs

In this paper, a novel method is presented to design ternary logic circuits for nanoelectronics applications. The ternary logic is a best alternative to the binary logic because it offers reduced interconnects, faster operating speed and reduced chip area. The digital logic circuit designs are developed using Pseudo N-type carbon nanotube field effect transistors (CNTFETs). The threshold voltage of CNTFETs is altered by the CNT diameter that is defined by the chirality vector. The ternary inverters such as standard inverter (SI), positive inverter (PI) and negative inverter (NI) and ternary basic gates such as AND, NAND, OR and NOR gates are designed. Furthermore, the half adder circuits developed which assists to develop complex circuit schematics. The proposed ternary schematics are designed and simulated using the HSPICE simulator. Moreover, the performance of the proposed circuits are investigated in terms of delay, power dissipation and power delay product (PDP) and compared with the existing circuits. It is observed that the proposed circuits show average performance improvement up to 47.48% over the existing circuits.