Scheduling Algorithm For Input-queued Switches Research Articles

Highest Rank First: A New Class of Single-Iteration Scheduling Algorithms for Input-Queued Switches

In this paper, we study a new class of single-iteration scheduling algorithms for input-queued switches based on a new arbitration idea called highest rank first (HRF). We first demonstrate the effectiveness of HRF by a simple algorithm named Basic-HRF. In Basic-HRF, virtual output queues (VOQs) at an input port are ranked according to their queue sizes. The rank of a VOQ, coded by $\log (N+1)$ bits, where $N$ is the switch size, is sent to the corresponding output as a request. Unlike all existing iterative algorithms, the winner is selected based on the ranks of the requests/grants. We show that the rank-based arbitration outperforms the widely adopted queue-based arbitration. To improve the performance under heavy load and maximize the match size, Basic-HRF is integrated with an embedded round-robin scheduler. The resulting HRF algorithm is shown to beat almost all existing single-iteration algorithms. But, the complexity of HRF is high due to the use of multi-bit requests. A novel request encoding/decoding mechanism is then designed to reduce the request size to a single bit while keeping the original performance of HRF. A unique feature of the resulting coded HRF (CHRF) algorithm is that the single-bit request indicates an increase or decrease of a VOQ rank, rather than an empty VOQ or not. We show that the CHRF is the most efficient single-bit-single-iteration algorithm.

On Iterative Scheduling for Input-Queued Switches With a Speedup of $2-1/N$

An efficient iterative scheduling algorithm for input-queued switches, called round robin with longest queue first (RR/LQF), is proposed in this paper. RR/LQF consists of three phases: report, grant, and accept. In each phase, only a single-bit message per port is sent for reporting a packet arrival, granting an input for packet sending, or accepting a grant. In both the grant and accept phases, scheduling priority is given to the preferred input–output pairs first and the longest virtual output queuing (VOQ) next. The notion of the preferred input–output pair is to keep a global RR schedule among all the inputs and the outputs. By serving the preferred input–output pairs first, the match size tends to be maximized. By serving the longest VOQ next, the match weight is also boosted. When RR/LQF is executed for a single iteration (i.e., RR/LQF-1), we show by simulations that RR/LQF-1 outperforms all the existing single-bit-single-iteration scheduling algorithms. When RR/LQF is executed up to $N$ iterations (i.e., RR/LQF- $N$ ), we prove that under any admissible traffic pattern, RR/LQF- $N$ is stable with a speedup of $2-1/N$ , where $N$ is the switch size. To the best of our knowledge, this is the first work showing that an iterative scheduling algorithm is stable with a speedup less than 2. We then generalize RR/LQF to become a class of algorithms that have the same speedup bound of $2-1/N$ . Efforts are then made to further reduce the implementation complexity of RR/LQF. To this end, the pipelined RR/LQF and RR/RR, a simpler variant of RR/LQF, are proposed.

Multicast Due Date Round-Robin Scheduling Algorithm for Input-Queued Switches

Multicast Due Date Round-Robin Scheduling Algorithm for Input-Queued Switches

Enhanced first-in-first-out-based round-robin multicast scheduling algorithm for input-queued switches

This study focuses on the multicast scheduling for M×N input-queued switches. An enhanced first-in-first-out -based round-robin multicast scheduling algorithm is proposed with a function of searching deeper into queues to reduce the head-of-line (HOL) blocking problem and thereby the multicast latency. Fan-out information of each input cell composes a traffic matrix and the scheduler executes a round-robin algorithm on each column independently. Scheduling decisions result in a decision matrix for the scheduler to release multicast cells accordingly. A matrix operation called sync is carried out on the decision matrix to reduce the number of transmission for each cell. To reduce the HOL blocking problem, a complement matrix is constructed based on the traffic matrix and the decision matrix, and a process of searching deeper into the queues is carried out to find cells that can be sent to the idle outputs. Simulation results show that the proposed function of searching deeper into the queues can alleviate the HOL blocking and as a result reduce the multicast latency significantly. Under both balanced and unbalanced multicast traffic, the proposed algorithm is able to maintain a stable throughput.

Frame-Based Packet-Mode Scheduling for Input-Queued Switches

Most packet scheduling algorithms for input-queued switches operate on fixed-sized packets known as cells. In reality, communication traffic in many systems such as Internet runs on variable-sized packets. Motivated by potential savings of segmentation and reassembly, there has been increasing interest in scheduling variable-sized packets in a nonpreemptive manner known as packet-mode scheduling. This paper studies frame-based packet-mode scheduling for better scalability. It first shows that the admissible condition is no longer sufficient for packet-mode scheduling. Then, a relation between the frame size and packet sizes is derived that classifies under what conditions the packet-mode scheduling problem is polynomial solvable or is NP-hard. This relation reveals an interesting result that under various packet size distributions, it may be polynomial solvable even if many different packet sizes occur in the packet set, whereas it may be NP-hard with just two packet sizes present. Finally, as a practical solution, this paper studies how a speedup can help packet-mode scheduling. It is shown that the admissible condition becomes sufficient also when a speedup of two is used. A simple algorithm with a speedup of two is presented.

Max-Min Fair Scheduling in Input-Queued Switches

Fairness in traffic management can improve the isolation between traffic streams, offer a more predictable performance, eliminate transient bottlenecks, mitigate the effect of certain kinds of denial-of-service attacks, and serve as a critical component of a quality-of-service strategy to achieve certain guaranteed services such as delay bounds and minimum bandwidths. In this paper, we choose a popular notion of fairness called max-min fairness and provide a rigorous definition in the context of input-queued switches. We show that being fair at the output ports alone or at the input ports alone or even at both input and output ports does not actually achieve an overall max-min fair allocation of bandwidth in a switch. Instead, we propose a new algorithm that can be readily implemented in a distributed fashion at the input and output ports to determine the exact max-min fair rate allocations for the flows through the switch. In addition to proving the correctness of the algorithm, we propose a practical scheduling strategy based on our algorithm. We present simulation results, using both real traffic traces and synthetic traffic, to evaluate the fairness of a variety of popular scheduling algorithms for input-queued switches. The results show that our scheduling strategy achieves better fairness than other known algorithms for input-queued switches and, in addition, achieves throughput performance very close to that of the best schedulers.

An efficient scheduling algorithm for input-queued switches

This letter presents an efficient scheduling algorithm DTRR (Dual-Threshold Round Robin) for input-queued switches. In DTRR, a new matched input and output by round robin in a cell time will be locked by two self-adaptive thresholds whenever the queue length or the wait-time of the head cell in the corresponding Virtual Output Queue (VOQ) exceeds the thresholds. The locked input and output will be matched directly in the succeeding cell time until they are unlocked. By employing queue length and wait-time thresholds which are updated every cell time simultaneously, DTRR achieves a good tradeoff between the performance and hardware complexity. Simulation results indicate that the delay performance of DTRR is competitive compared to other typical scheduling algorithms under various traffic patterns especially under diagonal traffic.

Randomized scheduling algorithms for high-aggregate bandwidth switches

The aggregate bandwidth of a switch is its port count multiplied by its operating line rate. We consider switches with high-aggregate bandwidths; for example, a 30-port switch operating at 40 Gb/s or a 1000-port switch operating at 1 Gb/s. Designing high-performance schedulers for such switches with input queues is a challenging problem for the following reasons: (1) high performance requires finding good matchings; (2) good matchings take time to find; and (3) in high-aggregate bandwidth switches there is either too little time (due to high line rates) or there is too much work to do (due to a high port count). We exploit the following features of the switching problem to devise simple-to-implement, high-performance schedulers for high-aggregate bandwidth switches: (1) the state of the switch (carried in the lengths of its queues) changes slowly with time, implying that heavy matchings will likely stay heavy over a period of time and (2) observing arriving packets will convey useful information about the state of the switch. The above features are exploited using hardware parallelism and randomization to yield three scheduling algorithms - APSARA, LAURA, and SERENA. These algorithms are shown to achieve 100% throughput and simulations show that their delay performance is quite close to that of the maximum weight matching, even when the traffic is correlated. We also consider the stability property of these algorithms under generic admissible traffic using the fluid-model technique. The main contribution of this paper is a suite of simple to implement, high-performance scheduling algorithms for input-queued switches. We exploit a novel operation, called MERGE, which combines the edges of two matchings to produce a heavier match, and study of the properties of this operation via simulations and theory. The stability proof of the randomized algorithms we present involves a derandomization procedure and uses methods which may have wider applicability.

DISA: a robust scheduling algorithm for scalable crosspoint-based switch fabrics

This paper presents and analyzes a high-performance, robust, and scalable scheduling algorithm for input-queued switches called distributed sequential allocation (DISA). In contrast to pointer-based arbitration schemes, the proposed algorithm is based on a synchronized output reservation process, whereby each input selects a designated output while taking into consideration both local transmission requests and the availability of global resources. The distinctiveness of the algorithm lies in its ability to offer high performance when multiple cells are transmitted within each switching interval. Relaxed switching-time requirements allow for the incorporation of commercially available crosspoint switches. The result is a pragmatic and scalable solution for high port-density switching platforms. The efficiency of the scheme and its robustness in the presence of admissible traffic, without the need for speedup, is established through analysis and computer simulations. Performance results are shown for various traffic scenarios including nonuniform destination distribution, correlated arrivals and multiple classes of service.

A quantitative comparison of iterative scheduling algorithms for input-queued switches

In this paper we quantitatively evaluate three iterative algorithms for scheduling cells in a high-bandwidth input-queued ATM switch. In particular, we compare the performance of an algorithm described previously – parallel iterative matching (PIM) – with two new algorithms: iterative round-robin matching with slip ( iSLIP) and iterative least-recently used ( iLRU). We also compare each algorithm against FIFO input-queueing and perfect output-queueing. For the synthetic workloads we consider, including uniform and bursty traffic, iSLIP performs almost identically to the other algorithms. Cases for which PIM and iSLIP perform poorly are presented, indicating that care should be taken when using these algorithms. But, we show that the implementation complexity of iSLIP is an order of magnitude less than for PIM, making it feasible to implement a 32×32 switch scheduler for iSLIP on a single chip.