Abstract
In this paper we quantitatively evaluate three iterative algorithms for scheduling cells in a high-bandwidth input-queued ATM switch. In particular, we compare the performance of an algorithm described previously – parallel iterative matching (PIM) – with two new algorithms: iterative round-robin matching with slip ( iSLIP) and iterative least-recently used ( iLRU). We also compare each algorithm against FIFO input-queueing and perfect output-queueing. For the synthetic workloads we consider, including uniform and bursty traffic, iSLIP performs almost identically to the other algorithms. Cases for which PIM and iSLIP perform poorly are presented, indicating that care should be taken when using these algorithms. But, we show that the implementation complexity of iSLIP is an order of magnitude less than for PIM, making it feasible to implement a 32×32 switch scheduler for iSLIP on a single chip.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
