Scan Shift Research Articles

Design of clock control block for DFT

DFT is a technique that converts the design into testable after manufacturing. As technology is shrinking, the complexity of inserting the DFT is becoming high. When it comes to DFT timing, controlling clocks in test mode is become a challenge nowadays. To achieve the high scan shift speed and to reduce the tester time, a new architecture is proposed in this work. The objective of this work is to propose a new design for clock controlling in DFT timing and working of the proposed block by configuring the different Test Data Registers. The proposed clock provides the clock intercepts for scan and debug modes along with features such as a single clock entry point per tile, clock stop using TDR, capture clock path same as functional mode path, and staggering pulse generation for LOS and LOC. The scannable logic in any tile must receive a clock from the clock control block. The tile level clock can be gated inside this block. A pulse generation logic is used to control the Gater inside the proposed design. The dynamic power consumption of the proposed architecture is compared with different clock architectures. The dynamic Power consumption is calculated as 60 mW which is less compared to already existing on-chip clock controllers in the DFT.

Developments in scan shift power reduction: a survey

While power reduction during testing is necessary for today's low-power devices, it also lowers test costs. Scan-based methods are the most widely used approach for testing integrated circuits (IC). Test vectors are shifted into and out of scan chains bit by bit during shift operation. The time required for shift operation dominates the test time. With the geometries shrinking (7 nm→5 nm→3 nm→1.8 nm), ICs are required to be tested for newer defects, increasing test time. The most effective way to reduce test time for scan operation is to increase the frequency of the shift operation. Reduction in shift power enables scan operation to be performed with increased frequency, reducing test time, and test cost. This paper presents a survey of techniques proposed recently for shift power reduction. Various techniques, including special flip-flop usage, segmentation, reordering, and low-pass filter, are being reviewed. The techniques are organized based on main attributes to underscore their similarities and differences. Pros and cons in terms of complexities involved in their implementation are discussed. We believe this paper will provide a point of reference for further studies in scan shift power reduction and will be helpful to both industry and academia.

Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift

Test sets that target standard fault models may not always be sufficient for detecting all defects. To evaluate test sets for the detection of unmodeled defects, n-detect test sets (which detect all modeled faults at least n times) have previously been proposed. Unfortunately, n-detect test sets are often prohibitively long. In this paper, we investigate the ability of shadow flip-flops connected into a MISR (Multiple Input Signature Register) to detect stuck-at faults fortuitously multiple times during scan shift. We explore which flip-flops should be shadowed to increase the value of n for the least detected stuck-at faults for each circuit studied. We then identify which circuit characteristics are most important for determining the cost of the MISR needed to achieve high values of n. For example, circuits that contain a few flip-flops with upstream fault cones that cover a large percentage of all faults in the circuit can often achieve high n-detect coverage fortuitously with a low-cost MISR. This allows a DFT engineer to predict the viability of this MISR-based approach early in the design cycle.

A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead

In-situ timing error detection and correction (EDAC) structure is widely adopted in timing-error resilient circuits to reduce the conservative timing guardband induced by process, voltage, and temperature (PVT) variations. However, it introduces the latch-based datapath as well as extra detection and propagation logic, therefore challenges the design-for-testability (DFT) implementation. In this article, we propose a novel DFT-compatible EDAC structure with significant signal control simplification and test-pattern complexity reduction, featuring low area and test overhead. This structure leverages a new scannable EDAC cell (SEDC) which can be configured for timing EDAC in normal mode, or for shift operations as a flip-flop in scan mode. Specifically, the proposed detection logic can be controlled succinctly in scan shift operations and then observed via the global error propagation logic with simple control signal configurations during the test. Therefore, the sophisticated test pattern generation and critical path sensitization are removed. Based on the structure, a shift-based test method is presented to cover the EDAC structure with a low test pattern complexity and test time overheads. As compared with previous works, the proposed SEDC saves 30.5% area, 16.6% power, and 20.3% delay. Besides, our test method cooperating with the proposed EDAC structure reduces <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$149\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$23\times $ </tex-math></inline-formula> static and at-speed test patterns, respectively, together with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$232\times $ </tex-math></inline-formula> static test cycles, and up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$25\times $ </tex-math></inline-formula> at-speed test cycles on average, which proves the effectiveness for DFT.

Preponing Fault Detections for Test Compaction Under Transparent Scan

A test compaction procedure under transparent scan can compact a scan-based test set that contains a minimum number of tests. The additional test compaction can be important in applications that require highly compacted test sets. Transparent scan views a scan-based test set as a sequence of scan shift and functional capture cycles and allows the two types of clock cycles to appear in arbitrary sequences. The contribution of this brief is to suggest that one of the reasons for the effectiveness of transparent scan for test compaction is its ability to prepone fault detections by replacing scan shift with functional capture cycles when faults are activated during scan shift cycles. When fault detections are preponed, clock cycles around the original detection clock cycles become unnecessary and can be omitted. This view results in a new test compaction procedure that focuses on steps that contribute to test compaction, thus reducing the computational effort of test compaction compared with general-purpose test compaction procedures.

Scan Chain Stitching based on Logic Topology for Test-Power Reduction under Routing Constraint

Scan architecture is a widely used design modification for testability in ASICs to obtain good test coverage. But during the process of scan testing, power consumption is much higher than in functional mode of operation, as all the flops in the design switch during scan shift operations (shift-in and shift-out). The heat generated from high power dissipation can destroy the chip, cause reliability problems, or induce noise. Sometimes the problem of wrong response due to overheating may arise, causing yield loss. For these reasons, test power reduction is a topic for research. Though there are several scan shift power optimization techniques used in practice, scan chain stitching techniques based on logic topology proposed in the recent years address both shift-in and shift-out powers. Conceptually, the techniques likely cause routing congestion and therefore applying the techniques under a routing constraint could be an optimal solution is the proposal presented in this paper.

A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability

The power consumption of modern highly complex chips during scan test is significantly higher than the power consumed during functional mode. This leads to substantial heat dissipation, excessive IR drop, and unrealistic timing failures of the integrated circuits (ICs) under test. In this brief, a ByPassable Scan Data Retention Flip-Flop (BPS-DRFF) is proposed for low-power IC test. The proposed flip-flop contains two secondary latches. The output of the “function” secondary latch goes to the following combinational circuits, while the other “shadow” secondary latch is used to shift test vectors during scan test. By gating the output of the function secondary latch, the redundant switching activity in the combinational circuits is eliminated during scan shift, thereby reducing the test power consumption significantly. The suppressed switching activity also leads to lower IR drop across the chip, increasing the chip manufacturing yield. Furthermore, the shadow latch is reused for data retention in the sleep mode while performing power gating, thereby alleviating the area cost of the shadow latch. The proposed BPS-DRFF also eases the hold time sign-off in the test mode due to the elongated clock-to-Q contamination delay that is brought in by the shadow latch. The proposed design is applied to an AES-128 crypto core in a UMC 55-nm low power CMOS technology. Experiment results show that 68.5% power is saved during scan test with the proposed BPS-DRFF, compared to the standard scan retention flip-flop.

Development of a blended learning curriculum to improve POCUS education in a pediatric emergency medicine training program

We engaged in curriculum enhancement of POCUS training in our pediatric emergency medicine subspecialty training program using Kern's model of curricular development. We enhanced existing training to include focused asynchronous learning of image interpretation, longitudinal scanning shifts, and quarterly progress report score cards and check-ins for improved communication, transparency and reinforcement of goals. Our approach could inform other training programs looking to improve their POCUS curricula.

Pediatric emergency medicine fellowship point-of-care ultrasound training in 2020.

The primary objective was to survey pediatric emergency medicine (PEM) leaders and fellows regarding point-of-care ultrasound (POCUS) training in PEM fellowship programs, including teaching methods, training requirements, and applications taught. Secondary objectives were to compare fellows' and program leaders' perceptions of fellow POCUS competency and training barriers. This was a cross-sectional survey of U.S. PEM fellows and fellowship program leaders of the 78 fellowship programs using two online group-specific surveys exploring five domains: program demographics; training strategies and requirements; perceived competency; barriers, strengths, and weaknesses of POCUS training; and POCUS satisfaction. Eighty-three percent (65/78) of programs and 53% (298/558) of fellows responded. All participating PEM fellowship programs included POCUS training in their curriculum. Among the 65 programs, 97% of programs and 92% of programs utilized didactics and supervised scanning shifts as educational techniques, respectively. Sixty percent of programs integrated numerical benchmarks and 49% of programs incorporated real-time, hands-on demonstration as training requirements. Of the 19 POCUS applications deemed in the literature as core requirements for fellows, at least 75% of the 298 fellows reported training in 13 of those applications. Although less than half of fellows endorsed competency for identifying intussusception, ultrasound-guided pericardiocentesis, and transvaginal pregnancy evaluation, a higher proportion of leaders reported fellows as competent for these applications (40% vs. 68%, p≤ 0.001; 21% vs. 39%, p=0.003; and 21% vs. 43%, p≤0.001). Forty-six percent of fellows endorsed a lack of PEM POCUS evidence as a training barrier compared to 31% of leaders (p=0.02), and 39% of leaders endorsed a lack of local financial support as a training barrier compared to 23% of fellows (p=0.01). Although most PEM fellowship programs provide POCUS training, there is variation in content and requirements. Training does conform to many of the expert recommended guidelines; however, there are some discrepancies and perceived barriers to POCUS training remain.

X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan

Hybrid test schemes comprising on-chip test compression and logic built-in self-test are expected to play a pivotal role in the design of new integrated circuits and delivering high quality tests. As architectural differences between these two paradigms are gradually blurring, and both schemes efficiently share test logic, they become more vulnerable to unknown (X) states whose sources vary from uninitialized memory elements to unwrapped-for-test analog modules. Typically, X values degrade test results, and thus test response compaction schemes must be duly protected. This article presents maXpress-an X-tolerant tunable compactor deploying a new scan chain selection mechanism capable of completely masking X states, as required by many in-system or one-directional streaming test applications, within redefinable groups of scan chains and designated scan shift cycles. The proposed scheme is also supporting separate observation scan chains that, in contrast to conventional scan, capture faulty effects every shift cycle, while their content is gradually shifted into a compactor shared with the remaining chains. In addition to a new layout-friendly architecture, the article proposes algorithms to automate maXpress control settings based on scan chain selection rules deployed to suppress X states. Experimental results obtained for industrial designs show feasibility and efficiency of the proposed scheme altogether with actual impact of X-masking on a resultant test coverage and test pattern counts.

Defect Image Recognition and Classification for Eddy Current Testing of Titanium Plate Based on Convolutional Neural Network

In the actual production environment, the eddy current imaging inspection of titanium plate defects is prone to scan shift, scale distortion, and noise interference in varying degrees, which leads to the defect false detection and even missed inspection. In view of this problem, a novel image recognition and classification method based on convolutional neural network (CNN) for eddy current detection of titanium plate defects is proposed. By constructing a variety of experimental conditions and collecting defect signals, the characteristics of eddy current testing (ECT) signals for titanium plate defects are analyzed, and then the convolution structure and learning parameters are set. The structural characteristics of local connectivity and shared weights of CNN have better feature learning and characterization capabilities for titanium plate defect images under scan shift, scale distortion, and strong noise interference. The results prove that, compared with other deep learning and classical machine learning methods, the CNN has a higher recognition and classification accuracy for the defect eddy current image of the titanium plate in the complex detection environment.

Time and Area Optimized Testing of Automotive ICs

As cars become increasingly computerized and their safety functions evolve rapidly, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is rising dramatically with high-end models containing hundreds of embedded microcontrollers. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive systems. This article presents a scan-based test scheme optimizing test time and area overhead during manufacturing and in-system test of automotive electronics. The proposed scheme deploys observation test points that capture the faulty effects in every shift cycle into separate observation scan chains. To reduce area overhead, the scheme enables the sharing of flip-flops among control points. It is also shown how test points enhance test coverage (TC) in the presence of cascaded clock gaters. Finally, processing challenges when fault simulating every scan shift cycle to determine TC are addressed. Experimental results obtained for contemporary automotive designs and reported herein show significant improvements in test quality over traditional solutions.

A Novel Graph-Coloring-Based Solution for Low-Power Scan Shift

Shifting of test patterns often causes excessive toggle activity which leads to power supply noise and other electrical issues. This article proposes a novel method to assign staggered shift clocks to adjacent logic blocks to reduce the likelihood of excessive switching and prevent power supply noise. -Vivek Chickermane, Cadence Design Systems.

Invisible-Scan: A Design-for-Testability Approach for Functional Test Sequences

Functional test sequences can detect defects that are not detected by scan-based tests, but overall, achieve a lower gate-level fault coverage than scan-based tests. Design-for-testability (DFT) approaches for functional test sequences cause the sequences to deviate from functional operation conditions in arbitrary ways over the entire design. This paper introduces the concept of invisible-DFT as a DFT approach for functional test sequences, where the effects of activating the DFT logic are confined to selected logic blocks. This paper develops an invisible-scan approach. Considering a single logic block, the procedure described in this paper inserts scan shift cycles into a functional test sequence while maintaining the same primary input and output sequences for the logic block. This makes the activation of the DFT logic invisible to other logic blocks. The procedure allows a limited number of primary output vectors to be corrected for this purpose. Experimental results are presented to demonstrate the increase in fault coverage that can be achieved by invisible-scan.

Toward development of a large field-of-view cancer screening patch (CASP) to detect cervical intraepithelial neoplasia.

Cervical cancers are primarily diagnosed via colposcopy, in which the tissue is visually assessed by a clinician for abnormalities, followed by directed biopsies and histologic analysis of excised tissue. Optical biopsy technologies offer a less invasive method of imaging such that subcellular features can be resolved without removing tissue. These techniques, however, are limited in field-of-view by the distal end of the probe. We present a prototype that incorporates a rigid, machinable waveguide that is in direct contact with a fluorescently-labeled sample paired with a scanning fluorescent microscope. The system is capable of imaging large areas of tissue without the need to re-position the tissue-probe interface. A mosaicing algorithm was developed to quantify scanning shifts and stitch neighboring frames together to increase the field-of-view. Our prototype can yield a maximum axial resolution of <5 µm for individual frames and can produce mosaiced images with a field-of-view greater than 15 mm x 15 mm without sacrificing resolution. We validated the system with a 1951 USAF resolution target, fluorescent in vitro standards, and a patient study where ex vivo conization samples of squamous cervical epithelium were imaged. The results of the patient study indicate that architectural features of subcellular components could be detected and differentiated between normal tissue and precancerous lesions.

Globally Functional Transparent-Scan Sequences

Maintaining functional operation conditions during the application of scan-based tests is important for avoiding overtesting of delay faults. This issue has been considered for the functional capture cycles of scan-based tests, where the faults are typically detected. When scan shift cycles are used for fault detection, functional operation conditions are important during scan shift cycles as well. A transparent-scan sequence allows both types of clock cycles to be considered uniformly, allowing faults to be detected during functional capture as well as scan shift cycles. This article defines the concept of a globally functional transparent-scan sequence that maintains close-to-functional operation conditions during all its clock cycles. The procedure described in this article for computing globally functional transparent-scan sequences starts from a transparent-scan sequence that avoids scan shift cycles in order to maintain functional operation conditions. The procedure introduces scan shift cycles into the sequence in order to detect target faults. This process is guided by a transparent-scan sequence that is translated from a conventional scan-based test set and achieves the same fault coverage. Experimental results for benchmark circuits demonstrate the tradeoff between the proximity to functional operation conditions and the fault coverage achievable by the globally functional transparent-scan sequence.

Extended Transparent-Scan

Transparent-scan is an approach to test compaction where scan shift cycles and functional capture cycles are interleaved in arbitrary ways as needed for detecting target faults. This is achieved by viewing the scan enable input as a regular primary input that can be assigned arbitrary sequences of zero and one values. This paper notes that transparent-scan leaves an unused combination of the scan enable and scan chain input values. This paper suggests that the unused combination can control design-for-testability logic to achieve better test compaction. At the cost of one additional EXCLUSIVE-OR gate for every state variable, and routing of the scan chain input to all the flip-flops, the extended transparent-scan approach described in this paper allows the values of the next-state variables to be complemented before they are latched in the flip-flops during a functional capture cycle. Extended transparent-scan is developed under bounded transparent-scan, where scan-in and scan-out operations of a conventional scan-based test set are maintained in order to limit the computational cost. Experimental results for transition faults in the functional logic of benchmark circuits demonstrate the additional test compaction that can be achieved with extended transparent-scan. Transition faults in the scan logic are considered as well.

Test-Friendly Data-Selectable Self-Gating (DSSG)

Low-power design is a key consideration in modern design. XOR self-gating (data-driven self-gating) is used for power reduction in clock networks, which is one of the main factors of dynamic power consumption. When applying XOR self-gating, dynamic power consumption is reduced, but the number of required test patterns on the testing side is inflated. In critical cases, more than three times the regular number of scan test patterns may be required for industrial designs, such as GPUs. In this brief, we propose a novel self-gating structure. Data-selectable self-gating (DSSG) is designed to use functional data and scan data selectively to eliminate the unnecessary clock toggling of flip-flops. With this structure, the self-gating function can be used in the scan test mode, as well as the function mode. When the self-gating logic is used during scan shift operations, the stuck-at faults in the self-gating logic can be tested with short test sequences; therefore, the rise in test costs can be mitigated. It is possible to test the stuck-at faults in self-gating logic using only four scan test patterns. The experimental results show that the average of the stuck-at test pattern increase ratio has been dropped from more than 90% to less than 8%. The low-power performance of the proposed method in the mission mode is the same as that of the conventional self-gating structures. When the DSSG method is used, the dynamic power of the shift operation which may increase excessively during the scan test can be reduced.

Test Compaction by Test Removal Under Transparent Scan

This brief describes a new approach to test compaction under transparent scan. Transparent scan achieves higher levels of test compaction than possible with the conventional scan-based tests by interleaving scan shift cycles and functional clock cycles in arbitrary ways. Earlier approaches relied on the computation of a single transparent-scan sequence, and the omission of test vectors from it. However, a single transparent-scan sequence can be prohibitively long. In the approach described in this brief, a transparent-scan test set consists of several sequences whose lengths are limited. Test compaction is achieved by combining sequences into longer sequences that detect more faults, and removing from the test set entire sequences that become unnecessary. Experimental results for benchmark circuits demonstrate the ability of the procedure to achieve test compaction without creating prohibitively long transparent-scan sequences.

Functional-power-aware Partial Gating Method for Low Power Scan-shift

This paper presents a new scheme to minimize scan-shift power for test reliability with minimized functional power overhead, which is achieved by selective insertion of signal gating-logic considering the loading condition and switching activity of scan shift signals. The proposed methodology also considers practical design issues such as logic-timing overhead and cell-congestion impact associated with scan-shift power reduction. In experimental results with industrial system-on-chip (SoC) designs, the proposed power-aware gatinglogic- insertion methodology not only achieved reduction of scan-shift power but also improved functional power up to 10% compared with the conventional full-scan gating scheme.