Scan-path Architecture Research Articles

Planar Straight-Line Embedding of Double-Tree Scan Architecture on a Rectangular Grid

Double-tree-scan (DTS) is a new scan-path architecture that is deemed to be suitable for low-power testing of VLSI circuits. A full DTS resembles two complete k-level (k > 0) binary trees whose leaf nodes are merged pair-wise, and thus consists of exactly N$_{k}$ = 3 × 2$^{k}$ − 2 nodes. In this paper, the problem of planar straight-line embedding of a graph on a rectangular grid is investigated and an O(N$_{k}$) time algorithm for drawing it, is described. The embedding requires at most 2N$_{k}$ grid points, with an aspect ratio lying between 1 and f. Next, techniques of embedding a partial DTS is considered when the number of nodes n ≠ 3 × 2$^{k}$ − 2, for some k. Layouts of double-tree scan-paths for some benchmark circuits are also presented to demonstrate the results.

Self-Timed Boundary-Scan Cells for Multi-Chip Module Test

This paper presents a self-timed scan-path architecture, to be used in a conventional synchronous environment, and with basic application in digital testing and interconnections checking in a Smart-Substrate MCM (T.A. Garcia, A.J. Acosta, J.M. Mora, J. Ramos, and J.L. Huertas, “Self-Timed Boundary-Scan Cells for Multi-Chip Module Test,” Proceedings of IEEE VLSI Test Symposium, April 1998, pp. 92–97). With this approach, the potential advantages of self-timed asynchronous systems are explored for their practical use in a classical MCM testing application. Three different self-timed asynchronous boundary scan cells are proposed (Sense, Drive and Drive & Sense cells) that can be connected to form a self-timed scan-path. The main advantage is that no global test clock is needed, avoiding clock skew and synchronization faults in test mode, and hence, a more reliable test process is achieved. These cells have been designed and integrated in active substrates, building several boundary-scan configurations and being fully compatible with the ANSI/IEEE 1149.1 Standard. The experimental results, as well as their comparison with their synchronous counterparts, show the feasibility of the proposed self-timed approach for testing interconnections in a MCM.

Scan-path architecture for pseudorandom testing

The author presents an architecture for implementing scan technology in a state-of-the-art workstation that uses a single resource to control scan and clock functions and perform pseudorandom testing of individual chips and boards. The testing approach, which is based on the use of a linear-feedback shift register, also features the ability to capture test results and compress them into a single signature for comparison with a known 'golden-circuit' signature. The author describes an application for testing the Apollo DN10000 and presents a list of design rules for pseudorandom testing at the board level. He discusses communication with scan and clock resources, timing relationships for scan operations, problems encountered, and design-for-testability issues in some depth.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>