Scan Flip-flops Research Articles

A dependable and resource-frugal ring oscillator physically unclonable function

ABSTRACT Silicon Physical Unclonable Function (PUF) is a crucial component for hardware security, providing unique device identification in networks. PUF provides robust security for cryptographic keys and IC digital fingerprints. However, resource constraints in network devices limit its use in security protocols. To address this challenge, PUF offers a lightweight hardware security solution with two main types: strong PUF (e.g. arbiter PUF) and Ring Oscillator (RO) PUF. The first option produces large CRPs with improved security but incurs hardware overhead, whereas the second option offers lower overhead with smaller CRP size, leading to reduced security. This paper introduces a novel, cost-effective solution to enhance RO PUF security while reducing hardware limitations. Our proposal involves a resource sharing technique with scan flip-flops, multiplexers, and inverter logic. This approach takes advantage of existing scan chains in circuit netlists to reduce PUF area without sacrificing uniqueness. A specific set of test patterns and odd number of inverters transform the memory-based PUF into an RO PUF. Our solution also leverages pass transistor-based implementation to significantly reduce power consumption and area overhead. Simulation results show that our approach effectively reduces area and power consumption while maintaining PUF uniqueness.

Test Compression for Launch-on-Capture Transition Fault Testing

A new low-power test compression scheme, called Dcompress , is proposed for launch-on-capture transition fault testing by using a new seed encoding scheme, a new design for testability architecture, and a new low-power test application procedure. The new seed encoding scheme generates seeds for all tests by selecting a primitive polynomial that encodes all tests of a compact test set. A software-defined linear feedback shift register architecture, called SLFSR , is proposed to make the new method conform to the current flow of design and test. Experimental results on benchmark circuits show that test data volume can be compressed up to 6300X with the well-compacted baseline test set for a design with 11.8M gates and more than 1.1M scan flip-flops.

Design of a Scan Chain for Side Channel Attacks on AES Cryptosystem for Improved Security

Scan chain-based attacks are side-channel attacks focusing on one of the most significant features of hardware test circuitry. A technique called Design for Testability (DfT) involves integrating certain testability components into a hardware design. However, this creates a side channel for cryptanalysis, providing crypto devices vulnerable to scan-based attacks. Advanced Encryption Standard (AES) has been proven as the most powerful and secure symmetric encryption algorithm announced by USA Government and it outperforms all other existing cryptographic algorithms. Furthermore, the on-chip implementation of private key algorithms like AES has faced scan-based side-channel attacks. With the aim of protecting the data for secure communication, a new hybrid pipelined AES algorithm with enhanced security features is implemented. This paper proposes testing an AES core with unpredictable response compaction and bit level-masking throughout the scan chain process. A bit-level scan flipflop focused on masking as a scan protection solution for secure testing. The experimental results show that the best security is provided by the randomized addition of masked scan flipflop through the scan chain and also provides minimal design difficulty and power expansion overhead with some negligible delay measures. Thus, the proposed technique outperforms the state-of-the-art LUT-based S-box and the composite sub-byte transformation model regarding throughput rate 2 times and 15 times respectively. And security measured in the avalanche effect for the sub-pipelined model has been increased up to 95 per cent with reduced computational complexity. Also, the proposed sub-pipelined S-box utilizing a composite field arithmetic scheme achieves 7 per cent area effectiveness and 2.5 times the hardware complexity compared to the LUT-based model.

A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical Stress

Burn-In test equipment usually owns extensive memory capabilities to store pre-computed patterns to be applied to the circuit inputs as well as ad-hoc circuitries to drive and read the DUT pins during the BI phase. The solution proposed in this paper dramatically reduces the memory size requirement and just demands a generic microcontroller unit (MCU) equipped with a couple of embedded processors, some standard common peripheral units, and a few KB memories. Moreover, the proposed Burn-In tester could be integrated into a System Level Test equipment which is typically based on MCUs to communicate functionally with the DUT. This paper provides full details about the architecture of such a low-cost innovative tester, which can supply the DUT with unlimited pseudo-random patterns created autonomously by the MCU firmware from any selected seed. The tester prototype developed to collect experimental results includes a low-cost System-on-Chip based on a multi-core MCU and a set of peripheral cores, encompassing timers and Direct Memory Access modules. The tester prototype is used to stress an automotive chip accounting for about 20 million gates, 700 thousand scan flip-flops, and several scan modes. The combination of pseudo-random pattern generation with the ability to control different scan and Design for Testability (DfT) modes, including LBIST, permits to reach a higher coverage of stress metrics than by the application of a limited set of pre-computed ATPG patterns. The toggle coverage level reached is up to 95.89%. The application speed achieved by the tester with non-optimized connections is up to about 10MHz.

Design of a Start-Up Sequence Controller for a Mammography Machine

Mammography, which is also calledMastography, is the process of using low-energy X-rays to inspect the human breast for screening and diagnostics. The purpose of mammography is to detect breast cancer early, usually by looking for specific lumps or microcalcifications. The X-rays used are usually around 30 kVp. Excessive voltage to such a machine would be harmful to the patient. Proper monitoring of temperature and pressure needs to be ensured. To ensure this, a start-up sequence module is developed. The start-up sequence module reads the digitized voltage, pressure, and temperature reading from the sensor and asserts all the outputs to ensure that the machine is ready. The scan chain is formed of 13 scan flip-flops in this configuration. The synthesis mapped the design to 484 instances of cells in the open-source PDK technology. The design had a total area of 594 μm2, with a cell width of 0.297 μm, and a height of 0.99 μm.

New scan compression approach to reduce the test data volume

The test data volume (TDV) increases with increased target compression in scan compression and adds to the test cost. Increased TDV is the result of a dependency across scan flip-flops (SFFs) that resulted from compression architecture, which is absent in scan mode. The SFFs have uncompressible values logic-0 and logic-1 in many or most of the patterns contribute to the TDV. In the proposed new scan compression (NSC) architecture, SFFs are analysed from Automatic Test Pattern Generation (ATPG) patterns generated in a scan mode. The identification of SFFs to be moved out of the compression architecture is carried out based on the NSC. The method includes a ranking of SFFs based on the specified values present in the test patterns. The SFFs having higher specified values are moved out of the compression architecture and placed in the outside scan chain. The NSC is the combination of scan compression and scan mode. This method decides the percentage (%) of SFFs to be moved out of compression architecture and is less than 0.5% of the total SFFs present in the design to achieve a better result. The NSC reduces dependencies across the SFFs present in the test compression architecture. It reduces the TDV and test application time. The results show a significant reduction in the TDV up to 78.14% for the same test coverage.

Quantum Dot Cellular Automata-Based Scan Flip-Flop and Boundary Scan Register

In the emerging nanotechnology, a finest potential alternative to transistor-based technology is Quantum-dot cellular automata (QCA). It promises higher device density and lower power consumption. The predominant application of QCA is the realization of configurable blocks in the digital systems. This paper presents a new serial scan register and a boundary scan cell, essential components used for chip-level and system-level testing. The proposed majority logic gate-based 1-bit clocked D-flip-flop (DFF) and the rotating multiplexer is used in these techniques. In the first attempt, the clocked DFF is further extended to implement the 2-bit, 4-bit, serial shift register and scan flip-flop. The detailed structural and performance analysis in different aspects proves that the proposed circuits offer elevated performance in contrast to earlier reported works. The various circuit comparison factors that are to be considered in QCA are the circuit complexity, area, delay in terms of the number of clocks, and energy dissipation. Significant improvements have been enhanced in the proposed layouts as compared to traditional approaches. In addition, power dissipation analysis of the stated DFF would be carried out at 2 K Temperature using different tunnelling energy levels (0.5, 1.0, and 1.5 Ek). All the simulations are performed using QCA Designer Ver. 2.0.3 and the power analysis is performed by QCA Pro tool Ver. 1.0.

Swap and Rotate: Lightweight Linear Layers for SPN-based Blockciphers

In CHES 2017, Jean et al. presented a paper on “Bit-Sliding” in which the authors proposed lightweight constructions for SPN based block ciphers like AES, PRESENT and SKINNY. The main idea behind these constructions was to reduce the length of the datapath to 1 bit and to reformulate the linear layer for these ciphers so that they require fewer scan flip-flops (which have built-in multiplexer functionality and so larger in area as compared to a simple flip-flop). In this paper, we develop their idea even further in few separate directions.First, we prove that given an arbitrary linear transformation, it is always possible to construct the linear layer using merely 2 scan flip-flops. This points to an optimistic venue to follow to gain further GE reductions, yet the straightforward application of the techniques in our proof to PRESENT and GIFT leads to inefficient implementations of the linear layer, as reducing ourselves to 2 scan flip-flops setting requires thousands of clock cycles and leads to very high latency.Equipped with the well-established formalism on permutation groups, we explore whether we can reduce the number of clock cycles to a practical level, i.e. few hundreds, by adding few more pairs of scan flip flops. For PRESENT, we show that 4 (resp. 8, 12) scan flip-flops are sufficient to complete the permutation layer in 384 (resp. 256, 128) clock cycles. For GIFT, we show that 4 (resp. 8, 10) scan flip flops correspond to 320 (resp. 192, 128) clock cycles. Finally, in order to provide the best of the two worlds (i.e. circuit area and latency), we push our scan flip-flop choices even further to completely eliminate the latency incurred by the permutation layer, without compromising our stringent GE budget. We show that not only 12 scan flip flops are sufficient to execute PRESENT permutation in 64 clock cycles, but also the same scan flip flops can be used readily in a combined encryption decryption circuit. Our final design of PRESENT and GIFT beat the record of Jean et al. and Banik et al. in both latency and in circuit-size metric. We believe that the techniques presented in our work can also be used at choosing bit-sliding-friendly linear layer permutations for the future SPN-based designs.

Leveraging controllability measures for high transition delay test coverage in DTESFF based partial enhanced scan design

Scan design is extensively exploited to test transition delay faults (TDF). Broadside test commonly referred as launch on capture and skewed load test is also commonly referred as launch-on-shift are two approaches to test TDF’s through scan design. However arbitrary test vector pair application is not supported by scan design because of architectural constraint of scan and this eventually limits the fault coverage for TDFs. Arbitrary test vector application is supported in enhanced scan design which alleviates the problem of poor fault coverage. Enhanced scan design has high area overhead and this problem can be further tackled through interchanging extra flip-flop by hold latch in enhanced scan. However hold signal required in enhanced scan design consists of hold latch is fast in nature. This signal is exactly equivalent of scan enable signal in skewed load test. Enhanced scan cell using one clock cycle slower hold signal is implemented in delay testable enhanced scan flip-flop (DTESFF) design. Partial enhanced scan method based on DTESFF design by using controllability measures for scan flip-flop identification is proposed for high transition delay test coverage in this work. Simulation results demonstrate the test coverage improvement for TDF in ISCAS 89 benchmark circuits.

Open Defect Detection Not Utilizing Boundary Scan Flip-Flops in Assembled Circuit Boards

An electrical interconnect test method is proposed to detect and locate open defects occurring at interconnects between integrated circuits (ICs) and a printed circuit board. The test method does not utilize boundary scan flip-flops. It is based on a quiescent supply current that is made to flow through an interconnect under test by embedding a test circuit into the ICs. The circuit consists of MOS switches for each input pin of the ICs and its switch control circuit. SPICE simulations are used to examine whether open defects at the interconnects can be detected using this method. The simulation results indicate that the following defective interconnects are detected in addition to defective ones modeled as an open-circuit fault at a test speed of 25 MHz: defective interconnects modeled as a resistor of 150 $\Omega $ generating an additional propagation delay of 482 ps and as a capacitor of 4 pF generating an additional propagation delay of 128 ps and no logical changes. Testability of open defects using this test method is also examined experimentally by prototyping an IC in which the test circuit is embedded. The experiments indicate that a resistive interconnect of $150~\Omega $ and a defective one modeled as a capacitor of 2.2 nF can be detected by the test method at a test speed of 0.5 MHz.

A Novel QCA based Compact Scan Flip-flop for Digital Design Testing

Quantum-dot Cellular Automata (QCA) is an emerging technology used for computation at nano scale. It is an excellent alternative for the conventional CMOS technology. QCA provides us with low energy, high speed, faster switching speed and compact structures for logical circuits. Testing is the integral part of the design verification, scan flip-flop is used for device testing. It is used in processors for a built-in self-test. The objective of this paper is to design an optimized structure of a scan flip-flop which occupies less area and dissipates minimum energy compared to the previously designed architectures. The efficiency of the proposed structure is analyzed in terms of cell count, energy dissipation, and area occupied by the logical circuit. Proposed scan flip flop has a cell count of 32 and an energy dissipation of 0.0105 eV which is 20 % more efficient in terms of cell count and 29 % more efficient than the previous designs. The CAD tool, QCA Designer is used for design and simulation. Cells have a dimension of 18 nm in height and 18 nm in breadth and there is a distance of 2 nm between these cells. Bi-stable and coherence vector simulation engines are used in the tool for simulation.

Aggressive Exclusion of Scan Flip-Flops from Compression Architecture for Better Coverage and Reduced TDV: A Hybrid Approach

Scan-based structural testing methods have seen numerous inventions in scan compression techniques to reduce TDV (test data volume) and TAT (test application time). Compression techniques lead to test coverage (TC) loss and test patterns count (TPC) inflation when higher compression ratio is targeted. This happens because of the correlation issues introduced by these techniques. To overcome this issue, we propose a new hybrid scan compression technique, the aggressive exclusion (AE) of scan cells from compression for increasing overall TC and reduce TPC. This is achieved by excluding scan cells which contribute to 12% to 43% of overall care bits from compression architecture, placing them in multiple scan chains with dedicated scan-data-in and scan-data-out ports. The selection of scan cells to be excluded from the compression technique is done based on a detailed analysis of the last 95% of the patterns from a pattern set to reduce correlations. Results show improvements in TC of up to 1.33%, and reductions in TPC of up to 77.13%.

Design of Arm Processor’s Elements Using QCA

Quantum dot Cellular Automata is one of the promising future nano-technology for transistor-less computing which takes advantage of the coulomb force interacting between electrons. The aim of this paper is to consider the logical circuits of ARM processors and further reducing their size in nanometres like 2:1 multiplexer , D Flip Flop, scan Flip Flop, 2:1 multiplexer with enable, encoder, decoder, SR FF, shift register, memory cell and program counter are designed using QCAD tool . Their cell count, area, kink energy are taken in consideration to calculate power and energy dissipation.

A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test

Over the years, serial scan design has become the de-facto design for testability technique. The ease of testing and high test coverage has made it gain widespread industrial acceptance. However, there are penalties associated with the serial scan design. These penalties include performance degradation, test data volume, test application time, and test power dissipation. The performance overhead of scan design is due to the scan multiplexers added to the inputs of every flip-flop. In today’s very high-speed designs with minimum possible combinational depth, the performance degradation caused by the scan multiplexer has become magnified. Hence, to maintain circuit performance, the timing overhead of scan design must be addressed. In this paper, we propose a new scan flip-flop design that eliminates the performance overhead of serial scan. The proposed design removes the scan multiplexer from the functional path. The proposed design can help improve the functional frequency of performance critical designs. Furthermore, the proposed design can be used as a common scan flip-flop in the “mixed scan” test wherein it can be used as a serial scan cell as well as a random access scan (RAS) cell. The mixed scan test architecture has been implemented using the proposed scan flip-flop. The experimental results show a promising reduction in interconnect wire length, test time, and test data volume, compared to the state-of-the-art RAS and multiple serial scan implementations.

Cost-efficient Chip Identification Method using Scan Flip-flop based Physically Unclonable Function

Cost-efficient Chip Identification Method using Scan Flip-flop based Physically Unclonable Function

Compact circuits for combined AES encryption/decryption

The implementation of the AES encryption core by Moradi et al. at Eurocrypt 2011 is one of the smallest in terms of gate area. The circuit takes around 2400 gates and operates on an 8-bit datapath. However, this is an encryption-only core and unable to cater to block cipher modes like CBC and ELmD that require access to both the AES encryption and decryption modules. In this paper, we look to investigate whether the basic circuit of Moradi et al. can be tweaked to provide dual functionality of encryption and decryption (ENC/DEC) while keeping the hardware overhead as low as possible. We report two constructions of the AES circuit. The first is an 8-bit serialized implementation that provides the functionality of both encryption and decryption and occupies around 2605 GE with a latency of 226 cycles. This is a substantial improvement over the next smallest AES ENC/DEC circuit (Grain of Sand) by Feldhofer et al. which takes around 3400 gates but has a latency of over 1000 cycles for both the encryption and decryption cycles. In the second part, we optimize the above architecture to provide the dual encryption/decryption functionality in only 2227 GE and latency of 246/326 cycles for the encryption and decryption operations, respectively. We take advantage of clock gating techniques to achieve Shiftrow and Inverse Shiftrow operations in 3 cycles instead of 1. This helps us replace many of the scan flip-flops in the design with ordinary flip-flops. Furthermore, we take advantage of the fact that the Inverse Mixcolumn matrix in AES is the cube of the Forward Mixcolumn matrix. Thus by executing the Forward Mixcolumn operation three times over the state, one can achieve the functionality of Inverse Mixcolumn. This saves some more gate area as one is no longer required to have a combined implementation of the Forward and Inverse Mixcolumn circuit.

Design and Implementation of Scan Flip-flop for Processor Using QCA Technology

Design and Implementation of Scan Flip-flop for Processor Using QCA Technology

Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium–Gallium–Zinc Oxide FET Integrated With 65-nm Si CMOS

Low-power embedded memory and an ARM Cortex-M0 core that operate at 30 MHz were fabricated in combination with a 60-nm c-axis aligned crystalline indium-gallium-zinc oxide FET and a 65-nm Si CMOS. The embedded memory adopted a structure wherein oxide semiconductor-based 1T1C cells are stacked on Si sense amplifiers. This memory achieved a standby power of 3 nW while retaining data and an active power of 11.7 μW/MHz by making each bitline as short as each sense amplifier. The Cortex-M0 core adopted a flip-flop (FF) in which an oxide semiconductor-based 3T1C cell is stacked on the Si scan FF cell without area overhead, and achieved a standby power of 6 nW while retaining data. This combination of embedded memory and Cortex-M0 core can provide high-performance as well as low-power operation, which is essential for Internet of Things devices.

A Dummy Scan Flip-Flop Insertion Algorithm based on Driving Vertex

Commonly termed as Hardware Trojans, is an emerging issue for global hardware security. The research on Hardware Trojan detection is urgent and significant. Dummy Scan Flip-Flop(DSFF) structure could be used to improve the probability of hardware Trojan activation, which is significant to hardware Trojan detection, especially during the design phase. In this express, an algorithm for inserting the DSFF structure based on driving vertex is proposed. According to the experimental results, under the same transition probability threshold(Pth), compared to the state-of-art, the proposed algorithm can reduce both the inserting complexity and the induced area overhead of the DSFF insertion. The maximum area optimization rate can reach 44.8%. The simulation results on S386 and S38584 benchmark circuits indicate that the proposed algorithm can significantly reduce Trojan authentication time by increasing activation probability of hardware Trojan circuits.

Scan-Chain Intra-Cell Aware Testing

This paper first presents an evaluation of the effectiveness of different test pattern sets in terms of ability to detect possible intra-cell defects affecting the scan flip-flops. The analysis is then used to develop an effective test solution to improve the overall test quality. As a major result, the paper demonstrates that by combining test vectors generated by a commercial ATPG to detect stuck-at and delay faults, plus a fragment of extra test patterns generated to specifically target the escaped defects, we can obtain a higher intra-cell defect coverage (i.e., 6.46 percent on average) and a shorter test time (i.e., 42.20 percent on average) than by straightforwardly using an ATPG which directly targets these defects.