SC1 Solution Research Articles

Challenges and Solutions for Post-CMP Cleaning of Ceria Particles for Advanced Technology Nodes

It has been very difficult to remove smaller ceria particles from oxide surfaces after polishing. As the particle size decreases from 90 to 10 nm, cleaning efficiency of SC1 solution decreases from ~94 % to ~19 %, presumably because smaller ceria particles with a higher surface concentration of Ce3+ are more strongly coupled with silicon dioxide surfaces via strong Ce-O-Si bonding. (1) As was reported earlier, where the cleaning of oxide surfaces of ceria particles from slurries containing no additives, we reported that equimolar solutions containing H2O2 and NH4OH (4.2 mol l−1 each of H2O2 and NH4OH), aided by ultrasonic cleaning, and at high pH could almost completely remove even 10 nm sized ceria particles from silicon dioxide film surfaces. (1)However, a cleaning solution containing H2O2 and NH4OH at equal molar (4.2 mol l−1) was not effective in cleaning oxide and nitride surfaces contaminated with ceria particles in the presence of additives such as proline and citric acid. (2) Recently, we reported a cleaning solution comprising 1 wt% ascorbic acid, 1 wt% ammonium carbonate and 50 ppm Triton X-100 at pH 12, aided by ultransonic energy, to clean ~30 nm ceria particles from both oxide and nitride films with ~ 99% cleaning efficiencies. The binding between the additive-covered ceria particle particles and the oxide/nitride surfaces could be broken by the nucleophilic attack of hydroxyl ions. Ascorbic acid and ammonium carbonate prevent ceria particle redeposition by adsorbing on the surface of the removed particles and blocking the active Ce3+ species. Triton X-100 reduces adhesion between the particle and the film surfaces during cleaning.(1) Seo, J., Gowda, A., & Babu, S. V. (2018). Almost complete removal of ceria particles down to 10 nm size from silicon dioxide surfaces. ECS Journal of Solid State Science and Technology, 7(5), P243.(2) Gowda, A., Seo, J., Ranaweera, C. K., & Babu, S. V. (2020). Cleaning Solutions for Removal of∼ 30 nm Ceria Particles from Proline and Citric Acid Containing Slurries Deposited on Silicon Dioxide and Silicon Nitride Surfaces. ECS Journal of Solid State Science and Technology, 9(4), 044013.

Removal of Nanoceria Abrasive Particles by Using Diluted SC1 and Non-Ionic Surfactant

Nanoceria abrasives have received intensive attention in the process of shallow trench isolation (STI) polishing since it can result in less scratch. However, the nanoceria particles are very difficult to remove after chemical mechanical polishing. In this study, it is found that by adding AEO-20, a nonionic surfactant with appropriate concentration in the SC1 (H2O2: NH4OH: H2O = 1: 1: 5 v/v/v) and SC1 solution with diluted ratio up to 10, the nanoceria abrasive particles on the contaminated SiO2 wafers can be completely removed. Multiple measurement results show that the SC1 can react with Ce3+ and form Ce4+ in the ceria slurry, and the Ce3+ will slightly react with AEO-20 while Ce4+ will not. It is concluded that AEO-20 will adsorb on the nanoceria particles and will not change the repulsive force between ceria and SiO2. The adsorbed surfactant will lift the particles off the SiO2 surface while the slight reaction between AEO-20 and Ce3+ will accelerate the lift-off process.

Etch Characteristics and Morphology of Al2O3/TiO2 Stacks for Silicon Surface Passivation

Chemical processes are very important for the development of high-efficiency crystalline solar cells, mainly for surface texturing to improve light absorption and cleaning processes to reduce surface recombination. Recently, research has been focusing on the impact of chemical polishing on the performance of a passivated emitter and rear cells (PERC), with particular emphasis on the dielectric passivation layers on the front side. This study examined the influence of etching on the passivation of Al2O3/TiO2 stacks, where the films may each be deposited using a range of deposition and post-annealing parameters. Most TiO2 films deposited at 300 °C were resistant to chemical etching, and higher temperature deposition and annealing produced more chemical-resistant films. TiO2 films deposited at 100 °C were etched slightly by SC1 and SC2 solutions at room temperature, whereas they were etched at a relatively high rate in an HF solution, even when capped with a thick TiO2 layer (up to 50 nm in thickness); blistering occurred in 20-nm-thick Al2O3 films. In contrast to the as-deposited films, the annealed films showed a lower level of passivation as 1% HF etching proceeded. The implied open circuit voltage of the samples annealed at 300 °C after HF etching decreased more than those annealed at 400 °C. The dark area in the photoluminescence images was not resistant to the HF solution and showed more etch pits. The etching strategies developed in this study are expected to help setup integration processes and increase the applicability of this stack to solar cells.

Key technologies for dual high-k and dual metal gate integration**Project supported by the National High Technology Research and Development Program of China (Grant No. 2015AA010601).

The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al–O dipole at interface between HfSiAlON and bottom SiOx. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1 (NH4OH:H2O2:H2O = 1 :1 : 5) and DHF-based solution for the selective removing of nMOS TaN and HfSiON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON. After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.

Impact of Standard Cleaning on Electrical and Optical Properties of Phosphorus-Doped Black Silicon

Black silicon (b-Si) has been estimated to considerably grow its market share as a front texture of high-efficiency silicon solar cells. In addition to excellent optical properties, high-efficiency cell process requires extreme cleanliness of the bulk material, and thus cleaning of b-Si surfaces is often a critical process step. While standard clean (SC) 1 solution efficiently removes possible contamination from wafer surfaces, we show here that it may cause challenges in b-Si solar cells. First, the silicon etch rate in SC1 solution is shown to depend on the phosphorous concentration and as high rate as ∼1.4 nm/min is observed on planar emitter surfaces. When extending the study to b-Si, which has much larger surface area in contact with the cleaning solution, even higher volumetric Si consumption occurs. This is observed in significant changes in emitter doping profiles, for instance, a 10 and 30-min cleaning increases the sheet resistance from 47 to 57 Ω/□ and 127 Ω/□, respectively. Furthermore, the SC1 solution alters substantially the nanostructure morphology, which impacts the optics by nearly doubling and more than tripling the surface reflectance after a 30 and 60-min immersion, respectively. Thus, uncontrolled cleaning times may impair both the electrical and optical properties of b-Si solar cells.

Chemically Stable Atomic-Layer-Deposited Al2O3 Films for Processability.

Atomic-layer-deposited alumina (ALD Al2O3) can be utilized for passivation, structural, and functional purposes in electronics. In all cases, the deposited film is usually expected to maintain chemical stability over the lifetime of the device or during processing. However, as-deposited ALD Al2O3 is typically amorphous with poor resistance to chemical attack by aggressive solutions employed in electronics manufacturing. Therefore, such films may not be suitable for further processing as solvent treatments could weaken the protective barrier properties of the film or dissolved material could contaminate the solvent baths, which can cause cross-contamination of a production line used to manufacture different products. On the contrary, heat-treated, crystalline ALD Al2O3 has shown resistance to deterioration in solutions, such as standard clean (SC) 1 and 2. In this study, ALD Al2O3 was deposited from four different precursor combinations and subsequently annealed either at 600, 800, or 1000 °C for 1 h. Crystalline Al2O3 was achieved after the 800 and 1000 °C heat treatments. The crystalline films showed apparent stability in SC-1 and HF solutions. However, ellipsometry and electron microscopy showed that a prolonged exposure (60 min) to SC-1 and HF had induced a decrease in the refractive index and nanocracks in the films annealed at 800 °C. The degradation mechanism of the unstable crystalline film and the microstructure of the film, fully stable in SC-1 and with minor reaction with HF, were studied with transmission electron microscopy. Although both crystallized films had the same alumina transition phase, the film annealed at 800 °C in N2, with a less developed microstructure such as embedded amorphous regions and an uneven interfacial reaction layer, deteriorates at the amorphous regions and at the substrate–film interface. On the contrary, the stable film annealed at 1000 °C in N2 had considerably less embedded amorphous regions and a uniform Al–O–Si interfacial layer.

Clean-Induced Instability of Electrical Characteristics in Poly-Si Junctionless Nanowire Transistor

A heavy doped poly-Si junctionless channel immersed in NH4OH/H2O2/H2O (SC1) solution is always unexpectedly damaged and results in an instable electrical characteristic in a proposed tri-gated nanaowire (NW) thin film transistor (TFT). A new finding indicates that a sharp nanowire profile is observed because some segregated precipitates at the poly-Si grain boundaries are etched and the dependence of the silicon etch rate on the crystal orientation/grain size also impacts the sharp corner formation in SC1 solution. Moreover, it results in damaged nanowire surface and many electron traps in subsequently deposited gate oxide. Therefore, a smaller etching amount in SC1 solution is suggested in the fabrication of a tiny poly-Si junctionless nanowire TFT.

300 mm SiGe-On-Insulator Substrates with High Ge Content (70%) Fabricated Using the Smart Cut™ Technology

We have fabricated 300 mm Si0.3Ge0.7-On-Insulator substrates with the SmartCutTM approach. The donor wafers consisted in polished, 5 µm thick Si0.3Ge0.7 Strain-Relaxed Buffers (SRBs) on top of Si(001) substrates. The following stacks were deposited on top of those SRBs: (low Ge content SiGe / Si0.3Ge0.7) bilayers and (low Ge content SiGe / Si0.3Ge0.7 / low Ge content SiGe / Si0.3Ge0.7) multilayers. The thin, low Ge content SiGe layers were used as etch stops during the fabrication of the SiGeOI wafers and (in the second case) for the re-use of the expensive SRBs. A slight surface resurgence of the surface cross-hatch occurred as the deposited thicknesses became higher. The Ge content in the epitaxial layers was otherwise closely matched to that in the SRBs (70% instead of 68%) and some O peaks present at the Si0.3Ge0.7 / low Ge content SiGe interfaces. After H+ ion implantation, bonding and splitting, a SC1 solution was used to etch the Si0.3Ge0.7 layers and stop on the low Ge content SiGe layers. Meanwhile, TMAH was used in order to etch the low Ge content SiGe layers and stop on the Si0.3Ge0.7 layers. We obtained in the end 57 nm thick, flat Si0.3Ge0.7 layers (7.4 nm range) on top of the buried oxide (root mean square roughness: 0.3 nm only).

Behavior of Nickel Deposition on Silicon Wafers from TMAH and Ammonia based SC1 Cleaning Process

Behavior of nickel adsorption on silicon wafer from SC1 process, based on TMAH, is studied as a function of TMAH concentration, etch rate, residence time in solution. Deposition behavior of nickel on wafer surface is also investigated, from SC1 and dilute hydrochloric acid solution, intentionally contaminated with nickel. Temperature dependence in the behavior of nickel deposition from Ammonia based and TMAH based SC1 solution, is investigated. Finally, characterization of surface-deposited nickel on the wafer surface from the SC1 solution is carried out to provide possible mechanism and nature of deposited nickel.

Prevention of Metal Contamination in Sub 50 Nm SC1 Cleaning Process

In this study, we investigated the relationship between particle removal efficiency (PRE), surface etch rate and removal of metal contaminant with various concentrations of SC1 cleaning solution. To identify the relationship between etch rate and the formation of defect, etch depth was measured for various compositions of SC-1 solution by using atomic force microscopy. Si wafers were contaminated with Cu ions and particles by dipping method. Cu precipitate and particles on Si surface were counted by using atomic force microscopy and a dark field optical microscope respectively to evaluate cleaning efficiency of SC1 solutions. The effect of SC1 compositions on Si etching was also investigated. It is observed that with increase in H2O2 concentration both Cu contamination and PRE decreases. This study suggests that the SCl cleaning solution needs to be optimized in order to achieve lower Cu contamination with a high PRE.

Behavior of Nickel Deposition on Silicon Wafers from TMAH and Ammonia based SC1 Cleaning Process

Adverse affect of surface contamination, including metal, on silicon wafer resulted into continuous evolution of RCA cleaning process.1 Deposition behavior of nickel on silicon wafer from SC1 solution, based on TMAH, is investigated here. A number of process parameters like chemical concentration, process time and temperature on deposition behavior of nickel from SC1 solution are considered. The mechanism of nickel deposition is discussed along with possible formation of some nickel silicide on the surface. Increased level of nickel deposition, as a function of TMAH concentration, from TMAH based SC1 solution is shown in Fig. 1. Time dependency of nickel deposition is carried out by exposing wafer into a nickel-contaminated SC1 solution with incremental period of time. The level of deposited nickel is found to increase with time as shown in Fig. 2. In other words, the non-equilibrium nickel deposition is observed, for the nickel contamination level used here and the period of investigation. Additional nickel deposition study is performed by exposing wafer to TMAH based SC1 and ammonia based SC1 solution as a function of temperatures separately. Higher nickel deposition tendency, from SC1 bath, is observed in TMAH based SC1 solution compared to ammonia-based SC1 solution. Furthermore, the amount of deposited nickel from SC1 solution increases with temperature. The increased level of nickel deposition from TMAH based SC1 solution compared to ammonia- based SC1 solution is likely influenced by the increased stability of the nickel ion in ammonia with the formation of ammonia-nickel complex. 1 Characterization of surface nickel from nickel-contaminated TMAH-based SC1 solution is carried out by dippingsilcon wafers in SC1 that contains 1ppb Nickel for 4.5 min., 9 min and 18 mins. respectively. This is shown in Figure 3. Amount of deposited nickel in chemical oxide was first analyzed with VPD-ICPMS. Subsequently, non-removable surface nickel on the surface was analyzed by ICP/MS following etching with surface with mixture of hydrofluoric and nitric acid. The mechanism of nickel deposition can be considered to proceed by the reduction of Ni+2 ion via electrochemical oxidation of silicon in the alkaline solution.2 In other words the growth of chemical oxide on silicon is due to high redox potential of the SC1 solution containing peroxide. As indicated above the amount of metal oxide is expected to increase with treatment time observed in a similar study with copper.3 Furthermore, the observation of silicon oxide between the deposited nickel and substrate in alkaline solution is observed in an EDX analysis of the interface.4 The oxide layer is proposed to be produced by reaction of oxidized silicon with OH- ion promoted by Ni+2ion. Part of Ni adsorbed on wafer from SC1 (TMAH+H2O2) possibly form nickel silicide, which may be difficult to remove in traditional low pH metal cleaning step. Fig. 1 Amount of Nickel deposited on the wafer following SC1 traetment from SC1 solution with increasing ratio of TMAH to H2O2 concentration. Fig. 2. Nickel adsorption from SC1 solution contaminated with 1 ppb of nickel. Figure 3. Nickel adsorption from TMAH-based SC1 solution and NH3-based SC1 solution as a function of temperature is shown below. Elevated nickel deposition is observed in TMAH-based solution. Figure 4. Removal and non-removal nickel deposited on the wafer surface treated with dilute hydrochloric acid following depostion from from SC1 solution. Increased amount of non-removable nickel is observed with time.

Prevention of Metal Contamination in Sub 50 Nm SC1 Cleaning Process

The RCA cleaning process is a standard wet cleaning process for removal of contaminants from silicon wafer surface. As well known, the SC1 cleaning solution which consists of a mixture of NH4OH (ammonium hydroxide), H2O2 (hydrogen peroxide) and H2O is an efficient particle removal. Cleaning mechanism of SC1 cleaning solution on particles removal from silicon surface is slightly surface etching and lift off the particles from the Si surface by electrostatic repulsive force between particles and surface. SC1 cleaning process may etch a few angstrom (Å) level of silicon surface. However, metal contaminant which has a high redox potential is critical when bare silicon is exposed. Metal deposition on Si surface is induced by the oxidation reduction reaction between metal ion and Si surface. Metal ion can take electrons from Si surface and are reduced to become metal. Si surface beneath the metal particles is oxidized to become SiO2 and is etched away by OH- in SC1 solution. The metal pit is a form of localized etching that leads to the creation of small hole under the metal. Thus, the etching has a crucial effect on the formation of defects and removal of particles. The etch rate of Si increased with NH4OH concentration whereas it decreased with H2O2 concentration. This indicates that metal pitting increased with NH4OH concentration while H2O2 inhibits it. However, particle removal efficiency (PRE) decreased in high H2O2concentration. Particle removal is affected by etch rate and pH of cleaning solution. For high pH value in the SC1 solution, particles take on a strongly negative charge. The particles are repelled from a Si surface. This electrostatic interaction prevents recontamination by particles to Si surface. Therefore, it is important to optimize SC-1 cleaning process in Si surface cleaning process. In this study, we investigated the relationship between PRE, surface etch rate and removal of metal contaminant with various concentrations of SC1 cleaning solution. The thermally oxidized 200 mm p-type Si (100) wafers were used. To identify relationship between etch rate and formation of defect, etch depth was measured for various composition of SC-1 solution by using atomic force microscopy. The Cu ions were used as a source of metal pitting to making Cu precipitate on Si surface. Si wafers were contaminated with Cu ions and particles by dipping method. Cu precipitate and particles on Si surface were counted using atomic force microscopy and a dark field optical microscope to confirm cleaning efficiency of SC1 solution. Etching of Si wafer surface in SC1 solution was evaluated as a function of composition of SC1 solution. It was shown that Cu precipitates decreased with H2O2 concentration in SC1 solution. But PRE also decreased. It was suggested that H2O2 reduced the formation of Cu precipitates and PRE was dependent of NH4OH concentration. This study proposes cleaning process to minimize Cu precipitates with a high PRE in the optimized SC1 solution. Figure 1

Surface Cleaning of SiGe(100) and Passivation of Ge(100) with Aqeuous Ammonium Sulfide

As scaling of microelectronic devices continues, germanium and silicon-germanium are promising materials for integration into silicon-based technology. Germanium and silicon-germanium based field-effect transistors can reduce leakage current and consume less power by means of improved carrier mobility and a narrower band gap, as opposed to traditional electronics. However, silicon-germanium surfaces are more challenging to work with because the topmost surface layer is comprised of germanium oxides that complicate cleaning and passivation processes. Here we seek to obtain a smooth, oxide free SiGe surface and hope to garner an understanding of the best conditions to effectively remove surface oxides. Additionally, we hope to further our understanding of aqueous ammonium sulfide passivation processes on Ge surfaces that will prevent re-oxidation of the surface for applications towards modern field-effect transistors (FETs). The first portion of this work focuses on the removal of oxides from the SiGe surface with 50 and 75% Ge molar ratios using a variety of aqueous processes. These processes include SC-1, HCl, HF, and HCl/HF mixtures. The SiGe surface was characterized using X-ray photoelectron Spectroscopy (XPS) after each chemical treatment. Film thicknesses were measured using spectroscopic ellipsometry. Immersion in HCl showed similar results to as shipped samples and was ineffective in removing surface oxides. Aqueous HF, however, removed both surface oxides and carbon contamination. SC-1 treatments selectively reduced the Ge in the SiGe film and left the surface enriched in Si, which oxidized as confirmed by XPS. If the Ge could be completely removed from the top-most layer, the SiO2 layer that forms could be used to passivate the SiGe surface and avoid problematic Ge oxides. Ellipsometry results showed that SC-1 solutions (NH4OH:H2O2:H2O, 1:1:100 v/v) etched 1 nm of the SiGe film, which was then oxidized. Ge 2p to Si 2p XPS peak ratios confirmed that increasing concentrations of SC-1 depleted the Ge content on the surface from 0.8 to 0.4, confirming the enrichment of the surface in Si. Ge to Si peak area ratios as a function of the SC-1 dilution factor showed a non-linear trend for SiGe 50% surfaces. Passivation of Ge with aqueous (NH4)2S was also studied. Because Ge oxides are unstable and water soluble, it is advantageous to remove them and deposit a sulfur layer to prevent further oxidation when exposed to air. Surface passivation was studied as a function of deposition time, solution concentration and the addition of H2O2. Passivation of the surface was ineffective at times below 20 min. Changing the concentration of (NH4)2S also had no noticeable effect on the surface based on XPS. Furthermore, at high ammonium sulfide concentrations the addition of H2O2 did not affect the passivation process. The addition of H2O2 to dilute (NH4)2S showed poor passivation due to oxidation of the surface by H2O2.

Chemical Passivation of In0.53Ga0.47As(100) Using Ammonium Sulfide and Thiols

III-V compound semiconductors have superior electron and hole mobilities compared to silicon, which makes them alternative materials to fabricate transistors that are faster and use less energy. Since the oxides of III-V’s contain many defects and have undesirable electrical properties, aqueous passivation chemistries are needed to incorporate these materials into existing semiconductor processing lines. This study seeks to determine whether a thin (~2-3 nm) layer of sulfur or a sulfur-containing molecule can chemically passivate clean InGaAs surfaces to prevent oxide regrowth upon ambient exposure. The goal is to devise a liquid phase process to remove carbon contamination from the surface, etch the native oxides, and deposit a thin film to prevent the diffusion of molecular oxygen and water vapor to the clean surface of the semiconductor for at least one hour. In0.53Ga0.47As(100) on InP substrates (RMS=0.18 nm by atomic force microscopy) were cleaned in dilute SC1 solutions and etched for 1 min in 0.3 M HF or 1.0 M HCl followed by immersion in dilute solutions of 1-eicosanethiol (ET, 20 carbon atoms in chain) in ethanol or ammonium sulfide ((NH4)2S) in water. The chemical composition of the passivated surfaces was analyzed by x-ray photoelectron spectroscopy (XPS). The presence of InGaAs oxides was evaluated by comparing the In 3d, Ga 2p, As 2p and O 1s region of the XPS spectra of the substrates after different processes. The analysis of InGaAs etched for 1 min in HF or HCl showed that the surface reoxidized completely after only 4 min of ambient exposure (no surface roughening occured after etching). The main oxides present on the surface after the acid etching were the As3+ and Ga3+ states. When clean substrates were etched in HF or HCl and immersed for 20 min 4 mM ET and 0.02% (NH4)2S solutions, oxides were detectable on the surface after 4 min of atmospheric exposure, but the reoxidation of InGaAs was slowed down (after 60 min of ambient exposure, less oxides were present on the surface in comparison with the substrate that was not passivated, as shown in Figure 1). Additional tests showed similar results for 0.02% (NH4)2S passivation for 1 min and for 60 min, or for 20 min in 20% (NH4)2S, suggesting that the passivation is independent of (NH4)2S concentration or deposition time. From the XPS analysis, the passivation layer is bonding to the InGaAs surface in the form of sulfide (As1+ states observed in the passivated samples only). Only when InGaAs was passivated for 20 h in ET or for 20 min in (NH4)2S under a nitrogen atmosphere in a glove box, no detectable oxygen was observed in the O 1s region after exposing to air for a short time (4 min). Oxide regrowth was observed for longer ambient exposure times. To estimate the thickness of the passivation layer deposited, spectroscopic ellipsometry was used to measure the overlayer (ET, S and InGaAs oxides) on InGaAs after the passivation processes. An overlayer thickness of 0.8 nm was measured on InGaAs after passivating for 20 min in 0.02% (NH4)2S. The thickness of the overlayer on InGaAs after passivating for 20 h in 4 mM ET was 2.6 nm (the calculated molecular length of the ET molecule is 2.7 nm). These results show that the sulfur-based chemistries are bonding to the III-V’s but the resulting layer is not thick enough to prevent oxygen or water vapor from diffusing and reacting at the surface. We are working to understand how to densify the ET layer and control the thickness of layers deposited using (NH4)2S. Figure 1. XPS spectra of In0.53Ga0.47As(100) etched in 0.3 M HF and passivated for 20 min in 0.02% (NH4)2S in a nitrogen atmosphere (glove box). A control experiment where a water rinse was done instead of the passivation, exposed for 4 min to atmosphere, is shown in a). The passivated surface was exposed to atmosphere for b) 4 min, c) 8 min, d) 20 min and e) 60 min Figure 1

TiN Hard Mask Cleans with SC1 Solutions, for 64nm Pitch BEOL Patterning

Titanium Nitride metal hard mask was first introduced for BEOL patterning at 65 nm [1] and 45 nm nodes [2]. Indeed, in this “Trench First Hard Mask” (TFHM) backend architecture, the dual hard mask stack (SiO2 & TiN) allows a minimized exposure of ULK materials to damaging plasma chemistries, both for line/via etch sequence, and lithography reworks operations. This integration scheme was successfully used for a BEOL pitch down to 90 nm for the 28 nm node, however, for the 14 nm technology node, 64 nm BEOL minimum pitch is required for the first metal levels. Because it is unable to resolve features below 80 nm pitch in a single exposure, conventional 193 nm immersion lithography must be associated with dual patterning schemes, so called Lithography-Etch-Lithography-Etch (LELE) patterning [3] for line levels and self-aligned via (SAV) process [4] for via patterning. In both cases, 2 lithography/etch/clean sequences are necessary to obtain one desired pattern, and associated reworks also become more challenging since first pattern is exposed to resist removal processes (plasma + wet clean). The reference wet cleans that were developed for 65 to 28 nm TiN hardmask patterning, utilizes commonly used chemistry for BEOL post-etch cleans, i.e. diluted hydrofluoric acid (dHF) followed by deionized water Nanospray (DIWNS) on 300 mm single wafer tool.

Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O2, 30%), 120°C), SC1 (1:1:5 mixture of NH4OH, H2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film.

(Invited) Atomic Layer Deposition of HfO2 Using HF Etched Thermal and RTP SiO2 as Interfacial Layers

Atomic Layer Deposition (ALD) of HfO2 on Si substrates requires an interfacial oxide layer, which should be full of hydroxyl groups (-OH groups) or hydrophilic. Chemical oxide grown by SC1 solution is widely used as an ideal interfacial layer. It was reported that thermal SiO2 and RTP SiO2 are not good as interfacial layers because they are lack of OH groups. In this research, we found that diluted HF etching of thermal SiO2 and RTP SiO2 could create hydrophilic surfaces, which could be used as interfacial layers for ALD of HfO2. The electrical properties of the HfO2 grown on etched thermal and RTP SiO2 is not significantly degraded comparing to the HfO2 grown on chemical oxide.

Atomic Layer Deposition of High Quality HfO2 Using In-Situ Formed Hydrophilic Oxide as an Interfacial Layer

High-quality HfO2 cannot be grown directly on Si substrate using atomic layer deposition (ALD), and an interfacial oxide layer is needed. Traditionally, interfacial oxide layer is formed either in SC1 solution (2 NH4OH: 4 H2O2: 200 H2O) or by ozonated water spraying. A highly hydrophilic SiO2 interfacial layer was in-situ formed in the ALD chamber using 1 cycle of ozone and water. The HfO2 deposited on this interfacial layer showed great growth linearity. The gate leakage current is comparable to that formed using chemical oxide as the interfacial layer. The capacitance-voltage (C-V) curves have negligible frequency dispersion and hysteresis, which suggest high quality in both the interface and electrical properties. The in-situ formation of hydrophilic interfacial layer have advantages over the traditional interfacial layer. This might be useful for formation of interfacial layer on sophisticated 3-D MOS structures such as FinFETs and nanowire FETs. In addition, the chemical oxidation step can be eliminated from the integrated circuits manufacturing processes, which is economically beneficial to the industry.

Preparation and analysis of amorphous carbon films deposited from (C 6H 12)/Ar/He chemistry for application as the dry etch hard mask in the semiconductor manufacturing process

Amorphous carbon layers (ACL) were deposited on Si (100) wafers by plasma enhanced chemical vapor deposition (PECVD) by using 1-hexene (C 6H 12) as a carbon source for dry etch hard mask of semiconductor devices manufacturing process. The deposition characteristics and film properties were investigated by means of ellipsometry, Raman spectroscopy, X-ray photo electron spectroscopy (XPS) and stress analysis. Hardness, Young's modulus, and surface roughness of ACL deposited at 550 °C were investigated by using nano-indentation and AFM. The deposition rate was decreased from 5050 Å/min to 2160 Å/min, and dry etch rate was decreased from 2090 Å/min to 1770 Å/min, and extinction coefficient was increased from 0.1 to 0.5. Raman analysis revealed a higher shift of the G-peak and a lower shift of the D-peak and the increase of I(D)/I(G) ratio as the deposition temperature was increased from 350 °C to 550 °C. XPS results of ACL deposited at 550 °C revealed a carbon 1s binding energy of 284.4 eV. The compressive film stress was decreased from 2.95 GPa to 1.28 GPa with increasing deposition temperature. The hardness and Young's modulus of ACL deposited at 550 °C were 5.8 GPa and 48.7 GPa respectively. The surface roughness RMS of ACL deposited at 550 °C was 2.24 Å, and that after cleaning in diluted HF solution (H 2O:HF = 200:1), SC1 (NH 4OH:H 2O 2:H 2O = 1:4:20) solution, and sulfuric acid solution (H 2SO 4:H 2O 2 = 6:1) was 2.28 Å, 2.30 Å and 7.34 Å, respectively. The removal amount of ACL deposited at 550 °C in diluted HF solution, SC1 solution and sulfuric acid solution was 6 Å, 36 Å and 110 Å, respectively. These results demonstrated the viability of ACL deposited by PECVD from C 6H 12 at 550 °C for application as the dry etch hard mask in fabrication of semiconductor devices.

Ag Deposition Forms and Uniformity on Porous Silicon by Electrochemical Method

The electrochemical deposition technique was applied to achieve porous silicon (PS) surface passivated with Ag deposition for improving the properties of PS photoluminescence. The relation of Ag depositing forms to current density and the effect of PS hydrophilic surface on deposition uniformity were investigated. The experimental results indicated that there were two critical current densities (maximum and minimum) in which Ag was absent and electroplated on PS surface correspondingly, and the range of current density for deposition of Ag on porous silicon was from 50 μA/cm2 to 400 μA/cm2. The process of changing PS surface from hydrophobic into hydrophilic had positive effect on Ag deposition uniformity. Under the same experimental conditions, PS hydrophobic surface presented uneven Ag deposition. However, hydrophilic surface treated with SC-1 solution was even. Finally, the effect of PS surface passivation with Ag even deposition on photoluminescence intensity and stabilization of PS was studied. It was discovered that Ag passivation inhibited the degradation of PL intensity effectively. In addition, excessive Ag deposition had a quenching effect on room-temperature visible photoluminescence of PS.