Saturated Output Power Research Articles

23.5–27.5 GHz Band Doherty Power Amplifier Integrated Circuit Using 28 nm Bulk CMOS Process Based on Dynamic Power Dividing Network

This paper presents a Doherty power amplifier (DPA) integrated circuit (IC) designed to have enhanced gain, efficiency, and AM-AM characteristics through a dynamic power dividing technique, which can control the power dividing ratio according to the input power. Since this multi-purpose dynamic power dividing network also provides the phase offset and impedance matching at the interstage network needed for appropriate DPA operation, the active IC area could be reduced. To verify the proposed technique and its analysis, the DPA was implemented with a 28 nm bulk CMOS process for the fifth-generation (5G) new radio (NR) millimeter-wave frequency band of 23.5–27.5 GHz. The measured results showed a gain of 20.3–21.9 dB, saturated output power of 14.0–15.2 dBm, power added efficiency (PAE) of 22.8–26.7% at the peak power, and PAE of 14.6–17.6% at the 6 dB output power back-off (OBO).

The degradation mechanism of high power S-band AlGaN/GaN HEMTs under high temperature

Abstract The radio frequency (RF) degradation mechanism under high temperature is proposed in this paper. The saturated output power (P sat), power added efficiency (PAE) and gain of the HEMTs deteriorate significantly under high power dissipation operation conditions, which contribute to an elevation of the junction temperature (T j). The high T j causes a negative shift of the threshold voltage and a reduction of electron mobility, as well as enhancing the trapping effects of the devices. As a result, the P sat and PAE of the high-power HEMTs (P sat = 152 W) decreased by 0.76 dB and 8.3%, respectively, which is more severe compared to low-power HEMTs (P sat = 20 W), where P sat and PAE reduced by 0.16 dB and 3.1% when the operation temperature was increased from 25 °C to 150 °C. By increasing the gate-to-drain distance from 1.625 to 2.175 μm, drain current stability and high temperature reverse bias reliability are improved. The results demonstrate that the trapping effect can be suppressed by decreasing the electric field under the gate; therefore, the RF output characteristics are boosted by 1.2 W, 1 dB and 2.6% for a device with gate width of 11.52 mm.

Design of Broadband Highly Efficient Power Amplifier Based on Low‐Pass Filtering Network With Periodic Structure

ABSTRACTIn this paper, a broadband high‐efficiency power amplifier (PA) is designed by using an easily implementable low‐pass filtering network with periodic structure as the output matching circuit to achieve bandwidth expansion of the PA. The proposed periodic structure is based on right‐handed T‐type basic cells, which can achieve wideband filtering responses. In addition, the load design space of the extended continuous Class‐F mode is combined as the target impedance to achieve an efficiency improvement in bandwidth PAs. For verification, a broadband highly efficient PA across 0.6–3.6 GHz with a relative bandwidth of 143% is designed, fabricated, and measured. The test results have shown a drain efficiency of 60.8%–70.4% and gain of 8.5–11.9 dB with a saturation output power under 3‐dB gain compression of 38.5–41.9 dBm.

Design of Doherty power amplifier with power back-off extension based on harmonic tuning and output combining network optimization

This paper proposes a Doherty power amplifier (DPA) design method based on harmonic tuning and output combining network (OCN) optimization to extend the power back-off (PBO) range. Firstly, based on the optimal harmonic load impedance, a harmonic tuning optimization method is used to design the harmonic tuning network of the amplifiers, effectively improving the efficiency at saturation and PBO. Secondly, the fundamental output matching network and the post-matching network are considered as an OCN. The S-parameters of the OCN are calculated and utilized in the DPA design. To further expand the PBO range, the carrier load impedance at PBO is determined by considering the relationship between PBO range and reflection coefficient. Finally, a multi-objective evolutionary algorithm combined with the theory of solution set is used to optimize the OCN design, simplifying the design process of the output matching network. For verification, a high-efficiency DPA operating at 1.68 GHz with a large PBO range of 9.5 dB is designed and measured. Results indicate that the proposed DPA achieves a saturated output power greater than 44 dBm, with a peak efficiency of up to 75.2%. The efficiencies are 68.5% and 61.0% at 6 and 9.5 dB back-off powers, respectively.

A V-Band Wideband Power Amplifier with High Gain in a 130 nm SiGe BiCMOS Process.

This paper introduces a high-gain wideband power amplifier (PA) designed for V-band applications, operating across 52 to 65 GHz. The proposed PA design employs a combination of techniques, including pole-gain distribution, base-capacitive peaking, and the parallel configuration of multiple small-sized transistors. These strategies enable significant bandwidth extension while maintaining high gain, substantial output power, and a compact footprint. A two-stage PA using the combination technique was developed and fabricated in a 130 nm SiGe BiCMOS process. The PA prototype achieved a peak gain of 27.3 dB at 64 GHz, with a 3 dB bandwidth exceeding 13 GHz and a fractional bandwidth greater than 22.2%. It delivered a maximum saturated output power of 19.7 dBm and an output 1 dB compression point of 18 dBm. Moreover, the PA chip occupied a total silicon area of 0.57 mm2, including all testing pads with a compact core size of 0.198 mm2.

Multi-switch-controlled multi-mode TRFE with a high-linearity ATRSW for 2.4-GHz ISM applications

This paper presents a multi-switch-controlled multi-mode transceiver front end (TRFE) designed for the 2.4-GHz industrial–scientific–medical (ISM) band, with a particular focus on enhancing the linearity of the transmit/receive switch (TRSW) on the antenna side. Considering the distinct power levels in the RX/TX paths, the TRSW is designed to be asymmetric. This design not only elevates IP-0.1dB by over 50 % compared to the conventional symmetric topology, but also absorbing its function into the input matching network (IMN) of the low noise amplifier (LNA), thereby minimally impacting the noise figure (NF) of the RX chain. For the TX path, the high-pass component of the power amplifier (PA) output matching network (OMN) is repurposed, with a singular inductor being redeployed to serve as an inductive ESD safeguard. Moreover, the driving stage employs a passive gain-boosting technique, which elevates the gain by 3 dB compared to the traditional cascode structure. For verification, this TRFE is fabricated in 0.18-μm CMOS with a die size of 1.53 mm2. It achieves a NF of 2.4 dB and a RX gain of 16.7 dB under a 3.3-V supply. A TX gain of 26.2 dB and a saturation output power of 23.3 dBm with a peak power-added efficiency (PAE) of 38.8 % are also demonstrated.

G-band traveling wave tube based on the elliptical pillar defected photonic crystal

In order to reduce the ohmic losses in the slow wave structure (SWS), an elliptical pillar defected photonic crystal waveguide (EPDPCW) is proposed as a SWS for the terahertz traveling wave tube (TWT). Compared with rectangular pillar defected photonic crystal waveguides (RPDPCW), the EPDPCW shows better high-frequency characteristics and lower ohmic losses. According to the particle-in-cell (PIC) results, in the frequency range of 188 GHz to 218 GHz, the saturated output power of EPDPCW is greater than 13.4 W, and the maximum saturated output power is 26.8 W at 196 GHz at a voltage of 9.78 kV and a beam current of 150 mA. Compared to the RPDPCW-TWT, the performance of the EPDPCW-TWT has been significantly improved.

Dual‐band bandpass‐filtering high‐efficiency power amplifier with second harmonic suppression

AbstractThis study proposes a dual‐band bandpass‐filtering high‐efficiency power amplifier based on dual‐function dual‐band impedance control network (DBICN) and a dual‐band bandpass‐filtering impedance transformer (DBBFIT). The dual‐function DBICN is exploited to transform the optimal fundamental complex load impedance to real one, and control the second harmonic load impedances of two bands to the high‐efficiency region in the Smith chart. Besides, two transmission zeros are constructed at dual‐band second harmonics to enhance harmonic suppression. Meanwhile, an easy‐to‐design DBBFIT is proposed by utilizing filter theory to realize real‐to‐real impedance transformation, and all design parameters can be obtained by simple closed‐form analytical equations. For validation, a prototype is designed, fabricated, and measured. The measured results indicate the drain efficiencies are 61.6% and 58.3% at 1.78 and 2.42 GHz with saturation output power of 40.8 and 39.6 dBm, respectively. Moreover, the second harmonic suppressions of the two bands are 40.1 and 47.1 dBc, respectively.

Analysis of source second-harmonic-controlled wideband extended series of continuous modes power amplifiers

In this article, an in-depth analysis is presented for the first time by considering the impact of the input nonlinearity caused by gate-source capacitance (Cgs) on the performance and broadband design of extended series of continuous modes (ESCMs) power amplifiers (PAs). The conclusion of the analysis shows that the drain current waveforms of ESCMs will be altered, resulting in the overlapping region with the voltage waveform and theoretical efficiency becoming a function of the nonlinear factor γ under the influence of input nonlinearity. As a result, compared to the traditional ESCMs PAs, the introduction of nonlinear factor γ has given rise to a wider load design space and source second-harmonic manipulation space, which can achieve bandwidth expansion while reducing the design complexity of input and output matching networks. Subsequently, this conclusion was verified by using a commercially available 10W gallium nitride (GaN) device from Cree to design wideband high-efficiency PAs. The measured results show that in the target frequency band from 0.55 to 3.55 GHz, a drain efficiency of 60.5%–71.5 % and a gain of 9–12 dB can be obtained at a saturated output power of 39–42 dBm.

Dual-mode dual-band symmetrical Doherty power amplifier employing reciprocal gate bias for high-efficiency range enhancement

This article presents an in-depth exploration of the circuit architecture and design approach for broadening the high-efficiency range of dual-mode symmetrical Doherty power amplifiers (DPAs). To enhance performance across a broader spectrum, a modified dual-mode load modulation network (LMN) is introduced, leveraging the reciprocal gate bias configuration to support an expanded high-efficiency range exceeding 6 dB across two distinct operational bands. To corroborate the efficacy of our proposed dual-mode symmetrical DPA architecture, we designed and constructed a prototype power amplifier (PA) utilizing commercially available GaN transistors. The implemented PA demonstrates exceptional performance, achieving two distinct Doherty operation bands, specifically 1.85–2.0 GHz in Mode I and 1.5–1.55 GHz in Mode II. Remarkably, the high-efficiency range is extended to 8 dB in both bands. Furthermore, the drain efficiency achieves levels of 48.5%–51.8% in Mode I and 47.7%–50.4% in Mode II at 8 dB back-off, with a saturated output power exceeding 43 dBm.

Low-Polarization, Broad-Spectrum Semiconductor Optical Amplifiers.

Polarization-insensitive semiconductor optical amplifiers (SOAs) in all-optical networks can improve the signal-light quality and transmission rate. Herein, to reduce the gain sensitivity to polarization, a multi-quantum-well SOA in the 1550 nm band is designed, simulated, and developed. The active region mainly comprises the quaternary compound InGaAlAs, as differences in the potential barriers and wells of the components cause lattice mismatch. Consequently, a strained quantum well is generated, providing the SOA with gain insensitivity to the polarization state of light. In simulations, the SOA with ridge widths of 4 µm, 5 µm, and 6 µm is investigated. A 3 dB gain bandwidth of >140 nm is achieved with a 4 µm ridge width, whereas a 6 µm ridge width provides more output power and gain. The saturated output power is 150 mW (21.76 dB gain) at an input power of 0 dBm but increases to 233 mW (13.67 dB gain) at an input power of 10 dBm. The polarization sensitivity is <3 dBm at -20 dBm. This design, which achieves low polarization sensitivity, a wide gain bandwidth, and high gain, will be applicable in a wide range of fields following further optimization.

A Compact GaN Power Amplifier Module for New Generation Cellular Basestations

This paper presents a compact class-AB Power Amplifier Module (PAM) designed for new generation massive Multiple Input Multiple Output (MiMo) cellular base stations. The module is designed at the center frequency of 3.5GHz targeting Long Term Evolution (LTE) and 5G New Radio (NR) bands. The module is a hybrid design that incorporates a Gallium Nitride (GaN) High Mobility-Electron Transistor (HEMT) die, discrete components-based input, and output matching networks. The entire design is realized on an 8.5 x 5.2 mm, 2-layer Rogers4003C substrate. The module is assembled on a PCB as an open-top for post-characterization tuning. The small signal and large signal measurements are in quite good agreement. The measurement results show that the amplifier is unconditionally stable, the input return loss is 12.2 dB, the output return loss is 7.7 dB, and the small signal gain is 13.4 dB. The saturated output power is 33.3 dBm with a Power Added Efficiency of 20.1%. The small signal gain drops to 11.2 dB at around 22 dBm of input power due to GaN technology’s intrinsic soft compression characteristics.

An ultra-wideband power amplifier designed through a bandwidth expansion strategy

Abstract A bandwidth expansion strategy for ultra-wideband power amplifiers (PAs) is presented in this letter by adopting a parallel impedance matching architecture. This design strategy can effectively reduce the impedance conversion ratio between the load and the target impedance of the PA, thereby providing a feasible solution for broadband impedance matching. Subsequently, a commercially available 10 W gallium nitride device and a two-stage Wilkinson power divider network are combined to achieve the verification of the proposed theory. The results of the measurement show that within the target frequency band of 0.9–3.9 GHz, 58.5–71.2% of the drain efficiency and 9.1–12 dB of gain can be achieved with a saturated output power of 39.1–42 dBm.

A Broadband Three-Way Series Doherty Power Amplifier with Deep Power Back-Off Efficiency Enhancement for 5G Application

This article presents a new broadband three-way series Doherty power amplifier (DPA) topology, which enables a broadband output power back-off (OBO) efficiency enhancement of up to 10 dB or higher. The proposed DPA topology achieves Doherty load modulation and three-way power combining through a transformer, which requires only a low coupling factor, thus facilitating its implementation in double-sided PCBs or monolithic microwave integrated circuit (MMIC) processes. The design equations for the proposed DPA topology are proposed and analyzed in detail. A proof-of-concept PA at the 2.1–2.8 GHz band using commercial GaN transistors was designed and fabricated to validate the proposed concept. Within the operating frequency band, it achieves a saturated output power (Psat) of 44.5–46.5 dBm with a peak drain efficiency (DE) of 60–72%, and 43–52% DE at 10 dB OBO. Moreover, under a 20 MHz long-term evolution (LTE)-modulated signal, the PA demonstrates a 36.8–37.5 dBm average output power (Pavg) and 47–53% average drain efficiency (DEavg). Notably, the adjacent channel leakage ratio (ACLR) is as low as −35–−28.2 dBc without any digital predistortion (DPD).

Asymmetric Doherty power amplifier design considering the effects of peaking power amplifier early conduction

During the design of a Doherty power amplifier (DPA), the phenomenon of peaking PA turning on in advance is commonly observed. This is mainly due to the feedback of the main PA signal to the gate of the peaking PA through the gate-drain feedback capacitor, which results in an increase in its gate voltage. As a result, the overall efficiency of the back-off region is significantly reduced. This paper first describes the phenomenon of peaking PA turning on in advance. The formula for the voltage (referred to as the feedback gate voltage, FGV) imposed on the gate of the peaking PA by the main PA signal is then deduced. On this basis, the FGV is analysed numerically. For verification, an asymmetric DPA with a 9 dB output back-off (OBO) power level is designed and fabricated in this paper using GaN CGH40010F and CGH40025F transistors. According to the measurement results, the saturated drain efficiency of the DPA is 53.5%–63.3% in the 0.75–1.25 GHz band, the efficiency at the 9 dB OBO level is between 45.5%–54%, and the saturated output power is between 45 dBm–45.7 dBm, with a saturation gain of more than 8 dB.

Design of class f reconfigurable power amplifiers

With the rapid development of mobile communication technology, RF amplifier requirements becoming higher, miniaturization, high efficiency and multi-band have gradually become a research hotspot. Based on these hot research directions, this paper designs a dual-band reconfigurable power amplifier. The input of the amplifier adopts a stepped impedance matching network, which has a good matching effect in the 1.6 - 2.8 GHz band. The output is switched by a single-knife double-throw switch to the corresponding band output matching network to achieve the fast switching of different frequency bands. The RF amplifier tube is designed by using Cree’s GaN chip CGH40010F, which has an additional power efficiency of more than 60% in the frequency range of 1.7 - 1.9 GHz and 2.5 - 2.7 GHz bands, a gain of about 12 - 14 dB and a saturated output power of more than 40 dBm. This design has the features of high efficiency, high gain, miniaturization and multi-band, which is applicable to the mobile communication system.

Design of a Compact 2-6 GHz High-Efficiency and High-Gain GaN Power Amplifier.

In this paper, a novel wideband power amplifier (PA) operating in the 2-6 GHz frequency range is presented. The proposed PA design utilizes a combination technique consisting of a distributed equalization technique, multiplexing the power supply network and matching network technique, an LR dissipative structure, and an RC stability network technique to achieve significant bandwidth while maintaining superior gain flatness, high efficiency, high gain, and compact size. For verification, a three-stage PA using the combination technique is designed and implemented in a 0.25 μm GaN high-electron-mobility transistor (HEMT) process. The fabricated prototype demonstrates a saturated output power of 4 W, a power gain of 21 dB, a gain flatness of ±0.6 dB, a power-added efficiency of 39-46%, and a fractional bandwidth of 100% under the operating conditions of drain voltage 28 V (continuous wave) and gate voltage -2.6 V. Moreover, the chip occupies a compact size of only 2.51 mm × 1.97 mm.

A Ka-band 27.6-dBm power amplifier with a compression-state large-signal matching approach in 130-nm CMOS SOI technology

This paper presents a Ka-band power amplifier with a compression-state large-signal matching approach in 130-nm CMOS SOI technology. The amplifier employs a quad-branch topology based on zero-degree power combiners/splitters, with each branch comprising two differential stages, each containing four stacked FETs. With a compression-state large-signal matching approach, this design achieves the saturated output power (Psat) of 27.6 dBm with 14.1 % peak power added efficiency (PAE), output 1-dB compression point (OP1dB) of 20.1 dBm at 35 GHz, according to electromagnetic simulation (EM) results. Additionally, it exhibits a peak gain of 39.2 dB at 33 GHz and a 3-dB bandwidth across 32–38 GHz. Offering a low-cost solution suitable for phased array radars and satellite communications.

Design of Broadband Doherty Power Amplifier Based on Misaligned Current Phase

A broadband Doherty power amplifier (DPA) always experiences an efficiency degradation between two efficiency peaks, especially at two side bands. In this study, the efficiency degradation was demonstrated to be caused caused by the in-phase power combining at the saturation power level. To solve this problem, current misalignment was introduced into the broadband DPA design. The carrier and peaking PA have different current phases when performing the power combination at the saturation power level. In this work, it was also demonstrated that the efficiency in the high-power region of a DPA can be improved by elaborately using misaligned current phases. A detailed analysis and the design procedure of a broadband DPA are presented in this paper. And a 1.5–2.45 GHz broadband DPA was implemented and measured. The fabricated DPA achieves a saturation output power of 42.7–44.9 dBm, a saturation drain efficiency (DE) of 62.7–74.1% and a gain of 10.2–13.9 dB over 1.5–2.45 GHz. Moreover, the fabricated DPA also achieves a 6 dB back-off DE of more than 49.1% in the frequency band of interest.

A 6-/12-dB back-off reconfigurable Doherty-like load modulated balanced amplifier with compact area and wide bandwidth

This article presents a Doherty-like Reconfigurable Load Modulated Power Amplifier (R-LMBA) topology, which enables a broadband 6-/12-dB power back-off (PBO) reconfiguration by rearranging the bias voltages of the sub-amplifiers with compact area. The proposed R-LMBA guarantees proper phase differences among the three sub-PAs across the entire operating frequency band without the need for a bulky phase shifter that is adopted in conventional LMBAs. The design equations for the R-LMBA are proposed and analyzed in detail. A proof-of-concept PA has been designed in 0.1 μm GaAs pHEMT process to verify the proposed concept. In Mode-1, from 30 to 40 GHz, it achieves saturated output power (Psat) of 27.7–29.1 dBm with peak power added efficiency (PAE) of 28.5–34.4%, and 16.8–22.1% PAE at 6-dB PBO with its best 1.29 × efficiency enhancement over a Class-B counterpart. In Mode-2, it exhibits 28 dBm Psat with 30% peak PAE, and a PAE of 25%/13.6% at 6-/12-dB PBO, which is 1.67 × /1.81 × over an ideal Class-B PA. Besides, in Mode-1/-2, the PA demonstrates 21.3/20.3 dBm average output power (Pavg) and 17.9%/22.1% average PAE (PAEavg) with −28.1/-23.8 dB error vector magnitude (EVM) and −29.1/-25.9 dBc adjacent channel leakage ratio (ACLR) under 6-Gb/s 64-QAM modulated signal at 35 GHz.