Degradation Of Saturation Drain Current Research Articles

The Device Instability of p-GaN Gate HEMTs Induced by Self-Heating Effect Investigated by on-State Drain Current Injection (DCI) Technique

In this work, the device stability of p-GaN gate HEMTs under self-heating effect is comprehensively investigated by the ON-state drain current injection (DCI) technique. By delicately modulating the DCI condition, the devices exhibit different chip temperatures ranging from 40 °C to 150 °C, while the devices show quite distinguishing instability behaviors. Particularly, substantial threshold voltage shift and saturation drain current degradation is constantly observed in the device with severe self-heating effect after DCI stress. Significant <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{th}}$ </tex-math></inline-formula> shift of +0.83 V and saturation current reduction up to 18% are observed after the DCI stress, corresponding to a chip temperature of ~150 °C. After the device degradation, the device characteristics show a recoverable dynamic. By investigating the gate leakage current together with the electrothermal device TCAD simulation, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{th}}$ </tex-math></inline-formula> instability induced by the self-heating is revealed to be the electron trapping in the p-GaN gate-stack, while the saturation drain current degradation originates from a composited action of thermally enhanced electron trapping/de-trapping in p-GaN gate-stack as well as the access region at the hot spot close to the source field plate. The results reported in this work suggest that self-heating is a critical issue that may cause unstable operation of p-GaN gate HEMTs. The revealed underlying mechanisms are beneficial for further improving device stability.

Anomalous Channel Length Dependence of Hot-Carrier-Induced Saturation Drain Current Degradation in n-Type MOSFETs**Supported by Hong Kong, Macao and Taiwan Science & Technology Cooperation Program of China under Grant No 2014DFH10190, the Distinguished Young Scientists Foundation of Jiangsu Province under Grant No BK20130021, the National Natural Science Foundation of China under Grant Nos 61204083 and 61306092, and the Qing Lan Project.

The dependencies of hot-carrier-induced degradations on the effective channel length Lch,eff are investigated for n-type metal-oxide-semiconductor field effect transistor (MOSFETs). Our experiments find that, with decreasing Lch,eff, the saturation drain current (Idsat) degradation is unexpectedly alleviated. The further study demonstrates that the anomalous Lch,eff dependence of Idsat degradation is induced by the increasing influence of the substrate current degradation on the Idsat degradation with Lch,eff reducing.

Analysis of AlGaN/GaN high electron mobility transistors failure mechanism under semi-on DC stress

Semi-on DC stress experiments were conducted on AlGaN/GaN high electron mobility transistors (HEMTs) to find the degradation mechanisms during stress. A positive shift in threshold voltage (VT) and an increase in drain series resistance (RD) were observed after semi-on DC stress on the tested HEMTs. It was found that there exists a close correlation between the degree of drain current degradation and the variation in VT and RD. Our analysis shows that the variation in VT is the main factor leading to the degradation of saturation drain current (IDS), while the increase in RD results in the initial degradation of IDS in linear region in the initial several hours stress time and then the degradation of VT plays more important role. Based on brief analysis, the electron trapping effect induced by gate leakage and the hot electron effect are ascribed to the degradation of drain current during semi-on DC stress. We suggest that electrons in the gate current captured by the traps in the AlGaN layer under the gate metal result in the positive shift in VT and the trapping effect in the gate—drain access region induced by the hot electron effect accounts for the increase in RD.

Effect of 5 MeV proton radiation on DC performance and reliability of circular-shaped AlGaN/GaN high electron mobility transistors

The authors report an investigation of the effect of different doses of 5 MeV proton irradiation on circular-shaped AlGaN/GaN high electron mobility transistors. The degradation of saturation drain current (IDSS) was minimal up to an irradiation dose of 2 × 1013 cm−2. By comparison, a dose of 2 × 1014 cm−2 dose produced a 12.5% reduction of IDSS and 9.2% increase of sheet resistance. In addition, the threshold voltage showed larger positive shifts for 2×1014 cm−2 dose compared to 2×1013 cm−2, and both of these doses produced showed larger shifts for smaller gate to drain distances. Increases of 39.8% and 47.1%, respectively, in the breakdown voltage for 6 and 10 μm drain to gate distances (LGD) was observed and was attributed to the creation of a virtual gate at the AlGaN/GaN interface due to the irradiation, which reduced the peak electric field at the drain side of the gate edge.

Impact of proton irradiation on dc performance of AlGaN/GaN high electron mobility transistors

The effects of high energy proton irradiation dose on dc performance as well as critical voltage of the drain-voltage step-stress of AlGaN/GaN high electron mobility transistors (HEMTs) were investigated to evaluate the feasibility of AlGaN/GaN HEMTs for space applications, which need to stand a variety of irradiations. The HEMTs were irradiated with protons at a fixed energy of 5 MeV and doses ranging from 109 to 2 × 1014 cm−2. For the dc characteristics, there was only minimal degradation of saturation drain current (IDSS), transconductance (gm), electron mobility, and sheet carrier concentration at doses below 2 × 1013 cm−2, while the reduction of these parameters were 15%, 9%, 41% and 16.6%, respectively, at a dose of 2 × 1014 cm−2. At this same dose condition, increases of 37% in drain breakdown voltage (VBR) and of 45% in critical voltage (Vcri) were observed. The improvements of drain breakdown voltage and critical voltage were attributed to the modification of the depletion region due to the introduction of a higher density of defects after irradiation at a higher dose.

Effects of Base Oxide Thickness and Silicon Composition on Charge Trapping in HfSiO/SiO2 High-k Gate Stacks

This work investigates the fundamentals of charge trapping and the effects of base oxide thickness and Si composition on charge trapping in HfSiO/SiO2 high-k gate stacks using positive-bias temperature (PBT) stressing scheme. During the PBT stress, threshold voltage shift and saturation drain current degradation induced by charge trapping continue to grow and eventually become saturated, whereas the subthreshold swing and maximum transconductance remain unchanged. The extent of charge trapping increases with the decrease of base oxide thickness and Si composition in the HfSiO film, which can be explained by considering the channel-to-bulk tunneling time constant and the amount of neutral Hf–OH trapping centers in the HfSiO bulk layer. The power law dependence of saturation drain current degradation on the gate bias voltage indicates that charge trapping would become more significant if thin base oxide and low Si composition were employed in the further scaled HfSiO/SiO2 high-k gate stacks.

Anomalous hot carrier degradation of nMOSFET's at elevated temperatures

An anomalous behavior of nMOSFET's hot carrier reliability characteristics has been investigated at an elevated temperature for the first time. Although the degradation of linear drain current is significantly reduced with increasing stress temperature, the degradation of saturation drain current is enhanced for high temperature stress. This behavior can be explained by the reduction of the velocity saturation length at an elevated temperature, which increases the net amount of interface states that can influence the channel current. This anomalous behavior causes a significant impact on the device reliability for future deep submicrometer devices at high operating temperatures.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A PHYSICAL MODEL FOR THE HOT‐CARRIER INDUCED DEGRADATION OF LDD‐PMOS TRANSISTOR AND ITS EXPERIMENTAL VERIFICATION

As the physical dimensions of the devices are reduced to the submicrometer regime, the hot‐carrier reliability has become an important issue in the scaling of the p‐MOSFET as well as the n‐MOSFET. In this paper, we present a unified approach for p‐MOSFET degradation due to the trapping of the hot electrons in the gate oxide layers. A physical analytical model, based on the pseudo two‐dimensional model, is derived for the first time to describe the linear and saturation drain current degradation. The model has been verified by comparing the calculation and the measurement from submicron p‐MOSFET's with different channel lengths and oxide thickness. There are no empirical parameters in the model. Two physical parameters: the capture cross section and the density of states of electron traps, which can be determined independently from the measured degradation characteristics, are valid for both the linear current and the saturation current degradation. The simple expression is very suitable for the predicting of the circuit reliability.