Sampling Rate Conversion Research Articles

Design of energy efficient and reconfigurable sample rate converter using FPGA devices

Design of energy efficient and reconfigurable sample rate converter using FPGA devices

Frequency-domain adaptive MIMO filter with fractional oversampling using stochastic gradient descent for long-haul transmission over coupled 4-core fibers.

We propose a fractionally spaced frequency-domain adaptive multi-input multi-output (MIMO) filter architecture in which the sampling rate of input signals is below 2× oversampling with a non-integer oversampling factor for mode demultiplexing in long-haul transmission over coupled multi-core fibers. The frequency-domain sampling rate conversion to the symbol rate, i.e., 1× sampling, is placed after the fractionally spaced frequency-domain MIMO filter. The filter coefficients are adaptively controlled by stochastic gradient descent and gradient calculation with back propagation through the sampling rate conversion from the output signals on the basis of deep unfolding. We evaluated the proposed filter through a long-haul transmission experiment of 16-channel wavelength-division multiplexed and 4-core space-division multiplexed 32-Gbaud polarization-division-multiplexed quadrature phase shift keying signals over coupled 4-core fibers. The fractional oversampling frequency-domain adaptive 8×8 filter with 9/8× oversampling provided little performance penalty after 6240-km transmission compared to the conventional 2× oversampling frequency-domain adaptive 8×8 filter. The computational complexity in terms of the required number of complex-valued multiplications was reduced by 40.7%.

Real-time considerations for a source-time dominant auralization scheme

A well-designed recording system can capture a moving source without risk of distortions, knowledge of the source or path, or transmission of information back to the source (i.e., a smartphone can reasonably record a plane flying overhead). This necessarily happens in real time. It would be good if signal processing schemes for auralization possessed these properties. Recent work on the NoTAP method of auralization proposed an asynchronous sample rate conversion scheme that keeps track of the (nonuniform) rate of incoming samples to formulate an effective incoming sampling frequency. This value allows the method to predict what frequency regions at the receiver are vulnerable to aliasing or imaging artifacts. Strategies of oversampling and filtering can be used to eliminate these problem regions while preserving as much of the original content as possible given the desired receiver sampling frequency. This approach creates a situation where the receiver processing can run independently of the source/path processing making it attractive for real-time implementation. This presentation discusses the challenges associated with producing a truly real-time scheme. A three-way tradeoff emerges between an interpolation mechanism that generates decorrelated noise, the computational burden, and the nearness to absolute real-time with which one wants the scheme to run.

A Low Complexity and High Modularity Design for Continuously Variable Bandwidth Digital Filters

ABSTRACT Digital filters with variable bandwidth can be used for a variety of applications. Arbitrary change in the bandwidth of a digital Finite Impulse Response (FIR) filter can be acquired using sampling rate converters. In this paper, a sampling rate converter is proposed which is generated from Pascal structure, a fractional delay filter having low hardware complexity and high modularity. The proposed sampling rate converter requires lesser number of multipliers for implementation when compared with the sampling rate converters in the literature. A low pass filter having a single bandwidth sandwiched between two sampling rate converters can contribute multiple bandwidths in such a way that each bandwidth is an arbitrary variation of the original bandwidth. A two stage Frequency response masking approach (FRM) is used for the hardware efficient design of the original low pass filter. A low complexity and high modularity novel design for a continuously varying bandwidth of a digital FIR filter is proposed in this paper using the proposed sampling rate converter. The modularity of the Pascal structure can be used to control both pass band ripple as well as stop band attenuation of the continuously variable bandwidth FIR filter design. Different communication standards in a Software defined radio (SDR) channelizer is realized using the proposed design of continuously variable bandwidth filter.

A Fractional Sample Rate Converter with Parallelized Multiphase Output: Algorithm and FPGA Implementation

A Fractional Sample Rate Converter with Parallelized Multiphase Output: Algorithm and FPGA Implementation

Selecting the optimal sampling rate for the waveform generator with a variable clock

The broad sampling rate range of the Waveform Generator with Variable Clock (WGVC) allows unlimited choices. Selecting the sample rate only based on the Nyquist criterion might cause aliasing, when the mirror frequency is below the cut frequency of WGVC's reconstruction filter. Replaying signals using the maximum sample rate of the WGVC requires arbitrary sample rate conversion (ASRC), which has a high computational cost. Previous work proposed a suboptimal method to retrieve a fraction for converting the initial waveform in a WGVC with fractional sample rate conversion (FSRC), which guarantees anti-aliasing and a low computation cost. In this paper, an algorithm based on continued fractions is proposed to select a conversion fraction within a closed interval for FSRC, which not only ensures that the numerator and denominator are minimized theoretically but also avoids inversion errors caused by floating-point calculations. Experimental results demonstrate that the computational cost of signal conversion and waveform storage requirements are reduced when this algorithm is applied. In addition, the spectral purity of the output signal is better than that of the ASRC algorithm using the proposed algorithm.

A Range and Performance Optimized Version of the Computer-Aided Speckle Interferometry Algorithm for Real-Time Displacement-Strain Field Monitoring

This work presents an optimized implementation of the Computer-Aided Speckle Interferometry algorithm which enables full-field determination of displacements and strains on commodity Graphics Processing Units at high resolution and frame rates. By combining careful control of the average speckle size in a laser speckle pattern with a simple sampling rate conversion scheme, a compact representation of the optical speckle is achieved. This allows for optimal use of Graphics Processing Unit architecture with robust range extension. The optimal mapping of the Computer-Aided Speckle Interferometry algorithm to Graphics Processing Unit architecture is shown in detail, and a straightforward method for disambiguating large displacements is illustrated. Lastly, this paper demonstrates a two-step subimage-tapering modification to the original algorithm that enables robust range enhancement while maintaining resolution. Results from numerical simulations on synthetic speckle patterns are shown, and runtime performance metrics are provided, with performance ranging up to 60 frames per second in some cases. The method is suitable for interactive experimental mechanics research, process and testing or any application where real-time high-resolution displacement-strain monitoring is needed. A .NET Framework class library enabling the incorporation of the algorithm into 3rd -party applications is available for download.

Efficient hearing aid algorithm using DCT with uniformly re-sampled and recursively modified audiogram values

People with the hearing problems have different listening preferences and characteristics in hearing loss. So, hearing aids need algorithms that provide amplification based on frequency, so that the hearing-impaired persons can use hearing aids comfortably for a long duration. In this paper, a new algorithm is proposed for hearing aids in order to compensate for sensorineural and conductive hearing loss using discrete cosine transform (DCT). DCT coefficients of the input audio signal are multiplied with uniformly resampled and recursively modified audiogram values to compensate for hearing loss. This algorithm comprised of 4 stages namely precomputation to calculate gain values from audiogram, DCT, gain adjustment, and inverse DCT. In the above stated stages except precomputation, each stage requires only one matrix multiplication, which makes the proposed algorithm computational efficient. Performance of the proposed algorithm is compared with uniform filter banks, non-uniform filter banks, variable filter bank and reconfigurable filter banks. The algorithm is tested using audiograms with four different hearing loss cases. It is proved that the proposed algorithm provides less complexity, minimized delay and better matching with all types of audiograms, further, it also avoids degradation of audio signal due to sampling rate conversions in variable and reconfigurable filter banks.

Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

Nonuniform Sampling Rate Conversion:An Efficient Approach

We present a discrete-time algorithm for nonuniform sampling rate conversion that presents low computational complexity and memory requirements. It generalizes arbitrary sampling rate conversion by accommodating time-varying conversion ratios, i.e., it can efficiently adapt to instantaneous changes of the input and output sampling rates. This approach is based on appropriately factorizing the time-varying discrete-time filter used for the conversion. Common filters that satisfy this factorization property are those where the underlying continuous-time filter consists of linear combinations of exponentials, e.g., those described by linear constant-coefficient differential equations. This factorization separates the computation into two parts: one consisting of a factor solely depending on the output sampling instants and the other consists of a summation -- that can be computed recursively -- whose terms depend solely on the input sampling instants and its number of terms is given by a relationship between input and output sampling instants. Thus, nonuniform sampling rates can be accommodated by updating the factors involved and adjusting the number of terms added. When the impulse response consists of exponentials, computing the factors can be done recursively in an efficient manner.

A Novel Approach for Optimal Design of Sample Rate Conversion Filter Using Linear Optimization Technique

This paper presents a sample rate conversion filter for decimation with flat passband. The proposed linear programming optimization (LPO) technique improves the magnitude response of filter with least computational complexity. Computational complexity has been a major factor in selection of decimation filter. Simulation results indicate that the proposed filter shows passband droop less than 0.007 dB with 50.5% decrease in computational complexity. The proposed filter eliminates the need of compensator.

Heuristic Analysis of CIC Filter Design for Next-Generation Wireless Applications

This paper describes a novel multistage CIC filter which plays a vital role in software-defined radio (SDR) applications. In order to operate the baseband signal, wireless networking standards demand different sample rates. As a result, sample rate conversion (SRC) turns out as a pivotal method of SDR. Thus, cascaded integrator comb (CIC) filter is a distinct kind of linear-phase FIR filter which can be used as a decimation filter for SRC operation. The architecture of this filter is multiplierless with low passband droop; hence, it requires less area in contrast to other decimation filters. In this brief, the fundamental structure of CIC filter is examined with various parallel prefix adders and also the significant parameters of the CIC filter for different adders are exemplified. The proposed CIC filter with various parallel prefix adders has been designed in Verilog HDL using Xilinx ISE 14.7 and implemented on Kintex7 FPGA. The schemed CIC filter design is compared with the traditional CIC filter in view of area, speed and power consumption. Based on the obtained results on Kintex7 FPGA, the CIC filter with Brent Kung adder outperforms in terms of LUTs by 41.67% and power by 34.78% compared with the classical CIC filter and among the CIC filters using other parallel prefix adders. The proposed CIC uses new polynomial method which provides 33.33% reduction in passband droop and 41.14% reduction in stopband ripple compared to the existing sharpened CIC.

A Resampling Method Based on Filter Designed by Window Function Considering Frequency Aliasing

Resampling technology is becoming increasingly critical, as different frequency components are required to be measured in one device. In this paper, a resampling method based on filter designed by window function is proposed to satisfy the requirements of different sampling rates. The frequency responses of the filter in the resampling model based on the Farrow structure are investigated, and the design criterion of the filter in the resampling model is proposed. A fractional delay filter design model based on window function method is established. A fractional delay filter coefficient matrix, which is expressed by a polynomial form, is constructed. Then, the expression related to the subfilter coefficients is obtained and subfilter coefficients are solved by the least-square method. The simulation results show that the filter designed by the proposed method has better performance when used for resampling as compared those designed by existing methods, and can efficiently prevent the occurrence of frequency aliasing and mirroring components in the process of sampling rate conversion. Therefore, the proposed method meets the conditions for application to existing measurement devices.

Comprehensive Survey of FIR-Based Sample Rate Conversion

Sample rate conversion (SRC) is ubiquitous and critical function of software defined radio and other signal processing systems (speech coding and synthesis, computer simulation of continuous-time systems, etc..). In this paper, we present a survey on linear phase finite impulse response (FIR) based sampling rate conversion. Many different FIR-based SRC solutions exist, such as classical FIR, polyphase, Farrow, cascaded-integrator-comb, and Newton structures. Each one of these solutions is presented differently in the literature, and SRC reference books introducing the subject are often missing hardware implementation aspects. The main objective of this paper is to provide a simple and comprehensive overview of main FIR-based SRC techniques from theoretical to hardware implementation aspects. The state of the art of FIR-based SRC filters is summed-up through a concise derivation of the different solutions from a common root: linear phase FIR filters. Each SRC solution is presented from both theoretical and practical implementation points of view. The paper provides a succinct tutorial that introduces SRC, and helps identifying and implementing the appropriate FIR-based SRC architecture for any given applications.

A Crystal View on the Design of FIR Filter

In audio and video signal processing main element is the FIR filter. This paper presents complete information regarding the FIR filters. It also focuses on the design of FIR filters which provide low-area, energy-delay, low-power consumption, high-speed, low critical path, and low complexity. Implementation of FIR filters with different methods like memory-based VLSI architecture, filters for sampling rate conversion, linear phase FIR filters, optimal hybrid form FIR filters, Nyquist filters, hybrid multiplier less FIR filters, low complexity FIR filters, variable partition hybrid form FIR filters, area efficiency FIR filters are discussed in this paper. The objective of this paper to provide all related information regarding FIR filters at one platform.

An Architecture for Real-Time Arbitrary and Variable Sampling Rate Conversion With Application to the Processing of Harmonic Signals

The paper presents a new solution for sampling rate conversion and processing of harmonic signals with known but possibly varying fundamental frequency. This problem is commonly found in particle accelerators, for tracking the beam signals whose revolution frequency varies during the acceleration ramp. It is also common among many other fields such as speech and music processing, removal of mechanical noises, filtering of biomedical recordings, active crack imaging, etc. The key element in the proposed solution is a new architecture for a Farrow-based resampler, in which the resampling ratio can take any value and can be modified continuously to follow the signal fundamental frequency. The combination of two complementary resamplers creates a processing region where signal synchronous processing is performed. The resampler architecture is optimized for modern FPGA features. It decouples the processing and sampling clocks, and uses a single processing (hardware) clock whose frequency remains fixed. The functional model was migrated to Xilinx System Generator and the overall performance is evaluated with an application that filters a periodic signal whose frequency follows a known linear ramp in the presence of additive white noise.

고속 표본율을 위한 임의의 SRC 구조

이 논문은 고속 표본율을 발생시키기 위한 임의의 표본율 변환기(SRC)의 구조를 제안하고 시뮬레이션을 통해 성능을 결과로 나타낸다. 통신 시스템에서 다양한 데이터율의 신호를 송수신하기 위해서는 임의의 표본율을 사용해야 한다. 기존의 SRC 구조는 시스템이 복잡하고 소모되는 자원이 많다. 또한, 통신 시스템의 경우 데이터율과 표본율의 동기화가 필요한데 이를 고려하여 설계하려면 외부 클럭이 필요해진다. 그래서 우리는 데이터율과 표본율 사이의 동기화가 필요하지 않은 임의의 SRC 구조를 제안하였다. 이 논문에서는 제안한 구조의 성능과 성능을 충족시키기 위한 필터의 조건을 결과로 보여준다.

A novel hybrid narrowband/wideband networking waveform physical layer for multiuser multiband transmission and reception in software defined radio

Increasing demands of adaptability and reconfigurability impose many challenges on the design of Software Defined Radio (SDR) waveforms for highly heterogeneous wireless networks. Usually, narrowband waveforms provide robustness and work for longer distances but lack in providing higher throughput, whereas wideband waveforms provide much higher throughput but they are not much robust and operate for smaller distances. A heterogeneous SDR network having diverse Quality of Service (QoS) and range requirements, and channel conditions cannot fully rely on one of the narrowband or wideband waveform. In this paper, a novel hybrid narrowband/wideband networking waveform physical layer is proposed. The proposed waveform is based on simultaneous transmission and reception of signals having multiple bandwidths through minimal changes in the existing analog wideband front end. A digital front end architecture is proposed where sample rate conversion and channelization of multiple signals at the digital front end formulate a composite signal which is then transmitted by using the wideband RF front end settings of a wideband waveform. At the receiver, the composite signal is received by using the wideband RF front end configured to wideband mode. Individual downconversion and filtering of each of the respective signal is done digitally. In this way, multiple signals having bandwidths as per their QoS and range requirements can be transmitted/received through the same wideband front end. As a proof of concept, the proposed idea is validated on actual SDR platform by taking actual dumps from FPGA and DSP. The presented results show the viability of the proposed hybrid SDR waveform.

Lattices sampling and sampling rate conversion of multidimensional bandlimited signals in the linear canonical transform domain

The linear canonical transform (LCT) has been shown to be a powerful tool for optics and signal processing. Many theories for this transform are already known, but the uniform sampling theorem, as well as the sampling rate conversion theory about arbitrary lattices sampling in the LCT domain are still to be determined. Focusing on these issues, this paper carefully investigates arbitrary lattices sampling, the sampling with separable matrices and nonseparable matrices, to obtain uniform sampling theorem and the sampling rate conversion theory in the LCT domain. Firstly, the spectral expression of the discrete-time signal sampled via arbitrary lattice is deduced in the LCT domain. Based on it we propose the alias-free sampling relationship between two matrices and present the perfect reconstruction expressions for bandlimited signals in the LCT domain. Secondly, for further research on discrete signals to obtain sampling rate conversion theory, we define the multidimensional discrete time linear canonical transform (MDTLCT), as well as the convolution for the MDTLCT. Thirdly, the formulas of multidimensional interpolation and decimation via integer matrices in the LCT domain are derived. Then, based on the results of interpolation and decimation, we make analyses of the sampling rate conversion via rational matrices in the LCT domain, including spectral analyses and the formulas in time domain. Finally, simulation results and the potential applications of the theories are also presented.

Experimental Demonstration of a Real-Time Digital Filter Multiple Access PON With Low Complexity DSP-Based Interference Cancellation

A four-channel, upstream, digital filter multiple access (DFMA) passive optical network (PON) is experimentally demonstrated for the first time in a 26 km single mode fiber (SMF) intensity modulation and direct detection system employing real-time optical network units (ONUs) and optical line terminal (OLT), which are dynamically reconfigurable in terms of channel spectral allocation and signal modulation parameters. To combat physical channel frequency response-induced cross channel interference (CCI) between spectrally overlaid orthogonal channels, a real-time, reconfigurable CCI cancellation (CCIC) function implemented in the OLT receiver digital signal processing (DSP), is demonstrated to significantly improve the DFMA PON performance and robustness in terms of significant reductions in total channel bit error rates (BERs) and individual subcarrier BERs, substantial increases in channel capacities, considerably reduced sensitivity to ONU synchronization, and excellent transparency to the interfering channel's signal modulation format. The tradeoff between the complexity of the CCIC function's filter, in terms of tap count (multiplier elements) and the DFMA PONs performance is optimized to determine the optimum tradeoff. It is shown that the CCIC filter only requires as few as 42 taps to achieve excellent CCIC performance. We also fully analyze the DSP complexity of the transmit and receive DFMA filters and the CCIC filters for varying DFMA channel counts and varying ratios of AD/DA converter sample rate to digital logic clock rate (parallelization factor). It is shown that DFMA filter complexity is independent of channel count and furthermore that for channel counts ≥ 4 the CCIC filter only needs to process ~10 interference-inducing samples per wanted signal sample, resulting in only ~10 multipliers per parallel filter in the CCIC filter. We have therefore successfully demonstrated an ultra-low complexity, real-time CCIC function, which considerably enhances the performance and robustness of DFMA PONs.