Sample-hold Circuit Research Articles

Input currents of CMOS SAR ADC in microcontroller, their measurement and behavior model from users point of view

The article introduces the possible issue of internal CMOS Successive Approximation Register microcontroller’s Analog-to-Digital Converters (ADC) input currents. It describes the nature of the ADC input current and its dependence on the sampling frequency but also explains the issue when the ADC input appears to the user as a voltage source. Methods for measurement of parameters such as input charge, residual voltage, and equivalent capacitance of sample-hold circuits are presented and used in the proposed simplified model of ADC input behavior. These parameters, which are not listed in the datasheets, if not respected in the data acquisition design, can adversely affect how the ADC is used when measuring signal sources with non-negligible internal resistance. The article also explains how to solve a voltage measurement on a source with high internal resistance even in a situation where, according to datasheets, it should already have limitations. If the microcontroller contains a dynamically switched multiplexer, it can lead to other consequences, such as changing the input current or residual voltage. The proposed simplified CMOS SAR ADC input behavior model in an MCU can help users in an MCU-based data acquisition system design.

Error Detection of Data Conversion in Flash ADC using Code Width Based Technique

Abstract The high integration density of the complex electronic system requires the multi-functional testing facility to ensure the accuracy of the circuit function. In addition, the wide population of submicron technologies results in the persistent requirements of high precision analog and mixed-signal (AMS) circuits. In the complex, high-density circuits, observing the correctness of output are limited due to the limitations of input and output pins which develop the AMS circuit test as very difficult and expensive. A digital built-in self-test (BIST) scheme has been presented in this paper for testing an analog to digital converter (ADC) in the time domain. The testing scheme consists of the linear analog ramp generator, ADC as a circuit under test, output response analyzer and a BIST controller. Bootstrap linear ramp generator is used to generate the linear analog ramp signal which is applied to ADC to develop the digital word sequence for testing. Among various types of ADCs, here a Flash ADC has used since it is fastest and accurate in digital conversion. A Flash ADC has been designed with the seven-bit resolution and tested using the proposed digital BIST scheme. The ADC comprises a sample-hold circuit, 2N -1 comparator, XOR gates, and encoder block. The output response analyzer verifies the digital output sequence to validate the static test parameters of ADC called monotonicity, missing codes, DNL, and INL error. The BIST controller generates the control signals to control the test sequence. The complete test sequence of ADC BIST has simulated in Tanner EDA with TSMC 0.18um technology. ORA is used to analyze the presence of monotonicity, missing codes, DNL and INL error in the ADC output.

Analog Neural Circuit and Hardware Design of Deep Learning Model

Abstract In the neural network field, many application models have been proposed. Previous analog neural network models were composed of the operational amplifier and fixed resistance. It is difficult to change the connecting weight of a network. In this study, we used analog electronic multiple and sample hold circuits. The connecting weights describe the input voltage. It is easy to change the connection coefficient. This model works only on analog electronic circuits. It can finish the learning process in a very short time and this model will enable more flexible learning. However, the structure of this model includes only one input and one output network. We improved the number of unit and network layers. Moreover, we suggest the possibility of the realization the hardware implementation of the deep learning model.

Theoretical Design and Circuit Implementation of Integer Domain Chaotic Systems

In this paper, a new approach for constructing integer domain chaotic systems (IDCS) is proposed, and its chaotic behavior is mathematically proven according to Devaney's definition of chaos. Furthermore, an analog-digital hybrid circuit is also developed for realizing the designed basic IDCS. In the IDCS circuit design, chaos generation strategy is realized through a sample-hold circuit and a decoder circuit so as to convert the uniform noise signal into a random sequence, which plays a key role in circuit implementation. The experimental observations further validate the proposed systematic methodology for the first time.

Development of an ASIC for Si/CdTe detectors in a radioactive substance visualizing system

We report on the recent development of a 64-channel analog front-end ASIC for a new gamma-ray imaging system designed to visualize radioactive substances. The imaging system employs a novel Compton camera which consists of silicon (Si) and cadmium telluride (CdTe) detectors. The ASIC is intended for the readout of pixel/pad detectors utilizing Si/CdTe as detector materials, and covers a dynamic range up to 1.4MeV. The readout chip consists of 64 identical signal channels and was implemented with X-FAB 0.35μm CMOS technology. Each channel contains a charge-sensitive amplifier, a pole-zero cancellation circuit, a low-pass filter, a comparator, and a sample-hold circuit, along with a Wilkinson-type A-to-D converter. We observed an equivalent noise charge of ~500 e− and a noise slope of ~5 e−/pF (r.m.s.) with a power consumption of 2.1mW per channel. The chip works well when connected to Schottky CdTe diodes, and delivers spectra with good energy resolution, such as ~12keV (FWHM) at 662keV and ~24keV (FWHM) at 1.33MeV.

Analog Learning Neural Network using Two-Stage Mode by Multiple and Sample Hold Circuits

In the neural network field, many application models have been proposed. A neuro chip and an artificial retina chip are developed to comprise the neural network model and simulate the biomedical vision system. Previous analog neural network models were composed of the operational amplifier and fixed resistance. It is difficult to change the connection coefficient. In this study, we used analog electronic multiple and sample hold circuits. The connecting weights describe the input voltage. It is easy to change the connection coefficient. This model works only on analog electronic circuits. It can finish the learning process in a very short time and this model will enable more flexible learning.

Time-synchronized continuous wave laser-induced fluorescence on an oscillatory xenon discharge

A novel approach to time-synchronizing laser-induced fluorescence measurements to an oscillating current in a 60 Hz xenon discharge lamp using a continuous wave laser is presented. A sample-hold circuit is implemented to separate out signals at different phases along a current cycle, and is followed by a lock-in amplifier to pull out the resulting time-synchronized fluorescence trace from the large background signal. The time evolution of lower state population is derived from the changes in intensity of the fluorescence excitation line shape resulting from laser-induced fluorescence measurements of the 6s(')[1/2](1)(0)-6p(')[3/2](2) xenon atomic transition at λ = 834.68 nm. Results show that the lower state population oscillates at twice the frequency of the discharge current, 120 Hz.

An Ultra-Low Power OTA-C Bandpass Filter Design for ECG Application

An ultra-low power OTA-C bandpass filter is presented in this paper. An 1-150 Hz 4-th order OTC-C bandpass filter is design which is suitable for ECG application. A subthreshold region OTA is designed with current cancellation technology to achieve a very small transconductance. The OTA-C filter is design with TSMC 0.18μm CMOS process. The MIM capacitor is used in this design. The supply of the proposed circuit is 1V. The total power consumption is only 245nW. I. I NTRODUCTION The development of portable heart monitoring system is not only useful in long-term healthcare, but also demanded in an increasing number of researches in the biomedical file (1). Filters is continually a critical block of biopotential acquisition systems for enhancing the signal quality (2). However, for low frequency biomedical applications, realizing filter circuits with large time constant under an acceptable capacitor's value isn't an easy task (3). Switching-capacitor circuit is a popular technique used in implementing filter circuit. Due to the leakage problem of the advanced process, the sample-hold circuits of the switch-based topologies are not suitable for applications requiring large time constant. Compared with the switching-capacitor filters, continuous-time OTA-C filter has their benefits of lower power consumption and freeing the system from switching noise. The cut-off frequency is proportional to the transconductance (g m ) of the OTA; this allows a low-power implementation for low frequency biopotential signals. In OTA-based circuits, OTA will dominate the performance of the filter circuit, while the ratio of the capacitor to the small transconductance determines the time constant of OTA-C integrators. Thus, an OTA in which the transistors are operated in the subthreshold region is needed to save more power and realize a very low transconductance. A 4-order Butterworth bandpass is presented in this paper. The bandwidth of this filter is 1-150Hz. A subthreshold OTA is used to achieve the 1Hz cut-off frequency. The transconductance is below 1nA/V. The performance of the OTA is based on the behavior of MOS devices operating in the subthreshold region. The channel current of subthreshold region is:(3)

Analysis of Tracking Distortion in Bootstrapped Gate MOSFET Sample-hold Circuits and a Method for its Minimization

A theory for the analysis of tracking distortion using the Volterra series is developed for bootstrapped gate sample-hold circuits with arbitrary signal AC gain applied at the gate. It is shown that second (HD2) and third (HD3) harmonic distortion show zeroes (minima) with respect to bootstrap gain whose location depends upon gate and substrate bias. Furthermore, the HD2 minimum occurs when the body-effect is compensated by applying a gain equal to the subthreshold slope factor of the MOSFET. These results are verified by using simple physics-based strong-inversion and surface-potential models as well as the PSP compact model. The cases of distortion and phase-lag in the bootstrap gate path are also considered. Measured second harmonic distortion on a discrete prototype shows reasonable agreement against simulation results using extracted MOSFET model parameters.

Voltage stress effect on class AB power amplifier and mixed-signal sample-hold circuit

Abstract The effects of gate and drain voltage stress and breakdown location on the class AB power amplifier and mixed-signal sample-hold circuit have been studied. The soft breakdown has minor effect on the performance of the power amplifier and sample-hold circuit, while the hard breakdown at the drain side reduces the power efficiency of the class AB power amplifier and degrades the signal to noise ratio of the sample-hold circuit significantly. Also, hot electron effect reduces the linearity of the class AB power amplifier.

A Signal Detection Circuit for 8b/10b 2.5 Gb/s Serial Data Communication System in 90 nm CMOS

This paper presents a CMOS signal detection circuit for 2.5Gb/s serial data communication system over FR-4 backplane. This overcomes characteristics deviation of full-wave rectifier-based simple power detection circuits due to data pattern and temperature by using an edge detector and a sample-hold circuit.

A current-mode buck DC-DC controller with adaptive on-time control

A current-mode buck DC-DC controller based on adaptive on-time (AOT) control is presented. The on-time is obtained by the techniques of input feedforward and output feedback, and the adaptive control is achieved by a sample-hold and time-ahead circuit. The AOT current-mode control scheme not only obtains excellent transient response speed, but also achieves the independence of loop stability on output capacitor ESR. In addition, the AOT current-mode control does not have subharmonic oscillation phenomenon seen in fixed frequency peak current-mode control, so there is no need of the slope compensation circuit. The auto-skip pulse frequency modulation (PFM) mode improves the conversion efficiency of light load effectively. The controller has been fabricated with UMC 0.6-μm BCD process successfully and the detailed experimental results are shown.

A 1.8-V 3.1 mW successive approximation ADC in system-on-chip

This paper describes a 10-bit 2.5 Msample/s successive approximation analog-to-digital converter (ADC) for SoC system. Based on conventional successive approximation ADC architecture a new and faster solution is used. The new solution consists of bootstrap switch, capacitors for sample-hold (S/H) circuit and DAC, using an offset cancellation method and there is no need for any active element. Together with an added bit and an offset compensation comparator the speed and accuracy is increased. The ADC exhibits higher 9 effective number of bits (ENOB) for sample rate to 2.5 Ms/s. The ADC consumes 3.1 mW from a 1.8 V supply and occupies about 0.25 mm2. The measured SNR is 56.05 dB.

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE

A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER<10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> was significantly increased with the use of DFE for short- to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally

EXPERIMENTAL REALIZATION OF CONTROLLING CHAOS IN THE PERIODICALLY SWITCHED NONLINEAR CIRCUIT

This letter presents an experimental confirmation of controlling the chaotic behavior of a target unstable periodic orbit when the periodically switched nonlinear circuit has a chaotic attractor. The pole assignment for the corresponding discrete system derived from such a nonautonomous system via Poincaré mapping works effectively, and the control unit is easily realized by the window comparator, sample-hold circuits, and so on.

Impact of Gate-to-Source/Drain Overlap Length on 80-nm CMOS Circuit Performance

In this paper, we perform rigorous mixed-mode simulations on two-stage inverter circuit and sample-hold circuits, representative of digital, and analog applications, respectively. The impact of gate-source/drain overlap length on circuit performance in an 80-nm CMOS circuit is evaluated by varying the overlap length between 0 to 20 nm, while keeping the subthreshold leakage current constraint at 1, 10, and 100 nA//spl mu/m. Process variations about the nominal overlap length have also been accounted for. The stage delay and switch error are used as the performance metrics. The lateral peak electric field is used as the metric for the hot carrier reliability. It is demonstrated that the overlap length should be made as small as possible, in spite of the increase in series resistance, in order to get the best circuit performance and reliability.

Linearity performance comparison of cascode current source and single-device current source IDPs; analyses, simulations and measurements

The input differential pair (IDP) is usually a major source of nonlinear distortion in any op-amp. This is especially true if the input signal has a large common-mode component, as is the case when an op-amp functions as a unity-gain buffer or as part of a single-ended sample-hold (S/H) circuit. In this paper, we analyse the distortion of the commonly used cascode current source IDP structure and explain the sources of its nonlinear behaviour. Next, a special design technique is proposed which enhances the linearity of IDPs. The circuit uses a single device current source that has the same channel length while its width is double those of IDP devices. Theoretical analysis, as well as simulation and experimental results, is given to confirm the improved linearity of a unity gain buffer. Simulations predict improvements up to 20 dB. 15 dB total harmonic distortion (THD) reduction was also achieved for a 15 MHz input signal based on measurement of a test chip. The method is valuable as power supply voltages shrink, and the design offers extra voltage headroom at input.

Digitally programmable switched-current FIR filter for low-voltage applications

In this paper, we describe a switched-current (SI) finite-impulse response (FIR) filter, suitable for equalizer architectures. The basic cell of the FIR filter is a SI sample-hold (S/H) circuit, appropriate for low-voltage operation. The programmability of the FIR filter structure is achieved via MOSFET-only current dividers. The FIR filter has been designed and implemented using a 0.8 /spl mu/m CMOS process and operates at a power-supply voltage of 2 V.

A charge conserving non-quasi-state (NQS) MOSFET model for SPICE transient analysis

An analytic charge-conserving non-quasi-static (NQS) model is derived for long-channel MOSFETs and has been implemented in SPICE3. The model is based on approximate solutions to the transient current continuity equation, an analytic equations are derived for node charges using the charge-sheet formulation. The NQS effects in several test circuits, which include a pass transistor, a CMOS inverter chain, and a differential sample-hold circuit, are stimulated. Excellent agreements have been observed among this work, PISCES (2-D device simulation), the 1-D numerical simulation, the multiple lump model, and CODECS (a mixed device and circuit simulation). However, large differences have been observed between this work and conventional quasi-static (QS) models. The model computation time of this work implemented in SPICE3 is about 2-3 times larger than those of QS models (BSIM, Level-2 Meyer) in SPICE3.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Alternative robust servo-control system and its digital control

An alternative approach to the design of a servomechanism for a continuous system is presented and its digital control is considered. The proposed design of the digital control system is based on the quadratic criterion function for a continuous system, and a smooth control input is given as the output of a high-order sample-hold circuit, which is derived from the characteristics of the reference signal and disturbances.