RX Mode Research Articles

A Fully Integrated 60-GHz 5-Gb/s QPSK Transceiver With T/R Switch in 65-nm CMOS

A fully integrated 60-GHz 5-Gb/s quadrature phase-shift keying (QPSK) transceiver with the transmit/receive (T/R) switch in 65-nm CMOS is presented. By utilizing the co-design of the T/R switch with the power amplifier (PA)/low-noise amplifier, π-type wideband passive network technique, as well as the modified distributed-amplifier-based PA, the RF bandwidth of the transmitter (TX)/receiver (RX) is extended to 5 GHz. An inductorless wideband programmable gain amplifier with negative capacitive neutralization, consisting of two modified Cherry-Hooper amplifier stages, provides 18-dB variable gain range with enough bandwidth. Due to the proposed bandwidth extension techniques, the measured double-side link bandwidth of the TX/RX is wider than 5 GHz so that 5-Gb/s QPSK communication could be supported. A direct QPSK modulator and mixed-signal QPSK demodulator are integrated to avoid the high-power high-complexity analog-digital converter/digital-analog converter and high-speed digital baseband processing. Together with the integrated T/R switch, the power consumption and the cost of the transceiver are significantly lowered while achieving up to 5-Gb/s data rate. The local oscillating signals and various clocks are provided by a fully differential phase-locked loop frequency synthesizer with -97.2-dBc/Hz phase noise at 1-MHz offset from a 40-GHz carrier. The measured error vector magnitude of the TX is -21.9 dB, while the bit error rate of the RX with a -52-dBm sine-wave input is below 8e-7 when transmitting/receiving 5-Gb/s data. The transceiver is powered by 1.0- and 1.2-V supply (except the phase-frequency detector and charge-pump in the frequency synthesizer, which are powered by a 2.5-V supply) and consumes 135 mW in the TX mode and 176 mW in the RX mode, with a chip area of 3 mm × 2 mm.

A 900 MHz Zero-IF RF Transceiver for IEEE 802.15.4g SUN OFDM Systems

This paper presents a 900 MHz zero-IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a fractional-N frequency synthesizer. In the RF front end, re-use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current-driven passive mixer in Rx and voltage-mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty-cycle in local oscillator clocks. The overall Rx-baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of -2 dBm, a sensitivity level of -103 dBm at 100 Kbps with PER of -11 dBm, and an Rx input IP3 of -2.3 dBm.

3D NoC with Inductive-Coupling Links for Building-Block SiPs

A wireless 3D NoC architecture is described for building-block SiPs, in which the number of hardware components (or chips) in a package can be changed after chips have been fabricated. The architecture uses inductive-coupling links that can connect more than two examined dies without wire connections. Each chip has data transceivers for the uplink and downlink in order to communicate with its neighboring chips in the package. These chips form a vertical unidirectional ring network so as to fully exploit the flexibility of the wireless approach that enables us to add, remove, and swap the chips in the ring. To avoid protocol and structural deadlocks in the ring, we use bubble flow control, which does not rely on the conventional VC-based deadlock avoidance mechanism. In addition, we propose a bidirectional communication scheme to form a bidirectional ring network by using the inductive-coupling transceivers that can dynamically change the communication modes, such as TX, RX, and Idle modes. This paper illustrates the inductive-coupling transceiver circuits, which can carry high data transfer rates of up to 8 Gbps per channel, for the wireless 3D NoC. It also illustrates an implementation of a wireless 3D NoC that has on-chip routers and transceivers implemented with a 65 nm process in order to show the feasibility of our proposal. The vertical bubble flow control and conventional VC-based approach on the uni- and bidirectional ring networks are compared with the vertical broadcast bus in terms of throughput, hardware amount, and application performance using a full system multiprocessor simulator. The results show that the proposed bidirectional communication scheme efficiently improves application performance without adding any inductive-coupling transceivers. In addition, the proposed vertical bubble flow network outperforms the conventional VC-based approach by 7.9-12.5 percent with a 33.5 percent smaller router area for building-block SiPs connecting up to eight chips.

Power-aware transceiver design for half-duplex bidirectional chip-to-chip optical interconnects

A power-aware transceiver for half-duplex bidirectional chip-to-chip optical interconnects has been designed and fabricated in a 0.13 μm complementary metal–oxide–semiconductor (CMOS) technology. The transceiver can detect the presence and absence of received signals and saves 55% power in Rx enabled mode and 45% in Tx enabled mode. The chip occupies an area of 1.034 mm2 and achieves a 3-dB bandwidth of 6 GHz and 7 GHz in Tx and Rx modes, respectively. The disabled outputs for the Tx and Rx modes are isolated with 180 dB and 139 dB, respectively, from the enabled outputs. Clear eye diagrams are obtained at 4.25 Gbps for both the Tx and Rx modes.

A Fully Integrated 60-GHz CMOS Transceiver Chipset Based on WiGig/IEEE 802.11ad With Built-In Self Calibration for Mobile Usage

This paper presents a fully integrated transceiver chipset based on the WiGig/IEEE 802.11ad standard targeting mobile usage. The chipset is developed for single-carrier (SC) modulation, which is suitable for reduced power consumption. However, the SC modulation is sensitive to in-band amplitude variations, mainly made worse by the gain variations of analog circuits and multipath delay spread. In order to compensate for these gain variations, the proposed chipset employs built-in TX in-band calibration and an RX frequency domain equalizer (FDE). The proposed techniques relax the requirement for high speed analog circuits, leading to less power consumption while minimizing the increase of hardware size. The test chip achieves 1.8 Gb/s MAC throughput for up to 40 cm and 1.5 Gb/s for up to 1 m while consuming 788 mW in TX and 984 mW in RX mode.

A 90 - 100-GHz 4 x 4 SiGe BiCMOS Polarimetric Transmit/Receive Phased Array With Simultaneous Receive-Beams Capabilities

This paper presents a 4 × 4 transmit/receive (T/R) SiGe BiCMOS phased-array chip at 90-100 GHz with vertical and horizontal polarization capabilities, 3-bit gain control (9 dB), and 4-bit phase control. The 4 × 4 phased array fits into a 1.6×1.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> grid, which is required at 94 GHz for wide scan-angle designs. The chip has simultaneous receive (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> ) beam capabilities (V and H) and this is accomplished using dual-nested 16:1 Wilkinson combiners/divider with high isolation. The phase shifter is based on a vector modulator with optimized design between circuit level and electromagnetic simulation and results in 1 dB and gain and phase error, respectively, at 85-110 GHz. The behavior of the vector modulator phase distortion versus input power level is investigated and measured, and design guidelines are given for proper operation in a transmit (Tx) chain. The V and H Rx paths result in a gain of 22 and 25 dB, respectively, a noise figure of 9-9.5 (max. gain), and 11 dB (min. gain) measured without the T/R switch, and an input P1 dB of -31 to -26 dBm over the gain control range. The measured output P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> is ~ -5 dBm per channel, limited by the T/R switch loss. Measurements show ±0.6- and ±0.75-dB variation between the 4 × 4 array elements in the Tx mode (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) and Rx mode, respectively, and 40-dB coupling between the different channels on the chip. The chip consumes 1100 mA from a 2-V supply in both the Tx and Rx modes. The design can be scaled to >10 000 elements using polyimide redistribution layers on top of the chip and the application areas are in W-band radars for landing systems.

An IEEE 802.15.4g sun compliant MR-OFDM RF CMOS transceiver for smart grid and CES

This paper proposes an IEEE 802.15.4g SUN OFDM-based 920 MHz RF CMOS transceiver. It can be adopted in energy saving intelligent green homes, which are related to Smart Grid, as well as universal remote controller, building automation, which is related to CEs (Consumer Electronics), and other areas. With the proposed SUN OFDM-based RF transceiver, wireless connectivity among CE devices or among electric metering systems can considerably save electronic energy and make our lives more comfortable. The proposed RF transceiver consists of a RF front-end with an on-chip RF switch, a Tx BBA (Baseband Analog), a Rx BBA, and a PLL. The proposed RF transceiver is implemented in 0.18-μm CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. With the fabricated RF transceiver chip, two successful public demonstrations have been carried out, which show the possibility of its use in commercial products.

4-Slot, 8-Drop Impedance-Matched Bidirectional Multidrop DQ Bus With a 4.8-Gb/s Memory Controller Transceiver

In this paper, we introduce an impedance-matched bidirectional multidrop (IMBM) DQ bus, together with a 4.8-Gb/s transceiver for a memory controller that supports this bus. Reflective ISI is eliminated at each stub of the IMBM DQ bus by resistive unidirectional impedance matching. A prototype memory controller transceiver is designed and fabricated in a 0.13- $\mu{\rm m}$ CMOS process and operates with a 1.2-V supply voltage. Its effectiveness is shown on various multidrop channel configurations. At 4.8 Gb/s, this transceiver with a 4-slot, 8-drop IMBM DQ bus has an eye opening of 0.39 UI in TX mode and 0.58 UI in RX mode, at a threshold of $10^{-9}$ BER, whereas a comparable transceiver with a conventional 4-slot, 8-drop stub series terminated logic has no timing margin under the same test conditions. Our transceiver consumes 14.25 mW/Gb/s per DQ in TX mode, and 13.69 mW/Gb/s per DQ in RX mode.

A Low-Power Fast-Settling Bond-Wire Frequency Synthesizer With a Dynamic-Bandwidth Scheme

This paper presents a low-power fast-settling phase-locked loop (PLL) frequency synthesizer working at 1.72–1.74 GHz for a 100 kb/s Gaussian frequency shift keying (GFSK) based transceiver suitable for wireless sensor network (WSN) applications. We propose several new techniques for lowering the power consumption in the frequency synthesizer. Resistor-based electro-static discharge protection (ESD-P) and automatic frequency calibration (AFC) are introduced to the bond-wire voltage-controlled oscillator (VCO) to deal with the inaccuracy of bond-wire inductors and uncertain parasitics. A multi-stage power-scaling scheme is developed for classical phase-switching prescaler. A dynamic-bandwidth scheme is proposed to speed up the settling time and improve the energy efficiency in a time-division WSN system. Implemented in 0.18 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\hbox {m}}$</tex></formula> CMOS technology, the measurement results show that the PLL consumes 10.6 mW under 1.8 V supply voltage and settles within 18 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\mu{\hbox {s}}$</tex></formula> including the AFC process. The phase noise is <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex> </formula> 89.8 dBc/Hz@10 kHz and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex> </formula> 119.3 dBc/Hz@1 MHz under receiving (Rx) mode; from receiving (Rx) state to transmitting (Tx) state, the out-band fractional- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$N$</tex></formula> phase noise is increased by 2.7 dB, whereas the in-band noise is lowered by 2.1 dB.

A CMOS Bidirectional 32-Element Phased-Array Transceiver at 60 GHz With LTCC Antenna

Fully integrated 32-element symmetrical TX/RX 60-GHz RF integrated circuit (RFIC) with built-in self-test is presented. The RF bidirectional power-combining architecture with shared blocks and less than 1-dB millimeter-wave transmit/receive (T/R) switch loss achieves record size and power consumption. The RFIC features an 8-dB noise figure and - 28-dBm IP1 dB in RX mode, 10-dB power gain, and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</b> of +3.5 dBm per chain in TX mode. Further included are a 2-bit phase shifter, an IF converter to/from 12 GHz, and an integrated frac- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> synthesizer with push-push voltage-controlled oscillator having a-93 dBc@1-MHz phase noise at 48-GHz local oscillator port. A novel high dynamic range phase and power detector is presented with 2° and ±1-dB accuracy over PVT in phase and power. A detailed analysis of both phase quantization and power distribution is presented. Array impairments such as mismatch and coupling were compared for different topologies. The RFIC is packaged on alumina for testing and on low-temperature co-fired ceramic (LTCC) for antenna integration. The 6 × 6 patch antenna on LTCC including four dummies achieves a gain of 19 dBi with scanning of ± 30°. The total root mean square amplitude and phase error of the array is 0.8 dB and 6 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> , respectively, resulting in a maximum array beam degradation of 1.4 dB for 2-bit quantization. The RFIC area is 29 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and it consumes 1.2 W/0.85 W at TX/RX, with a 29-dBm effective isotropic radiated power at -19-dB error vector magnitude.

능동형 RFID 시스템에서 태그의 Overhearing을 제거하기 위한 에너지 절약 프로토콜

Reducing the energy that consumed by tag is a key requirement for the wider acceptance of the active RFID systems that use battery constrained tags. When the reader is not interrogating, the active RFID standard protocols try to reduce energy consumption of tags by using sleep mode. On sleep mode tags is active by receiving a specific signals from reader, until tag receive a sleep mode command from the reader, a tag waste energy for remaining in RX mode. Overhearing is a state of a tag in which it wastes energy for maintaining active RX state while there is no frame destined to it. According to our analysis, the amount of energy consumed by a tag due to overhearing is several time larger than that consumed by the effective communication. We propose RANO(Reservation Aloha for No Overhearing) that is designed to inform a tag of its effective communication intervals to eliminate overhearing problem in active RFID communication. The performance of the proposed protocol was evaluated through the real world by changing the number of tags and size of data. The result of an experiment, the proposed protocol performed saving about 22 times less than the standard protocol did.

Complete SOC Transceiver in 0.18 $\mu$m CMOS Using Q-Enhanced Filtering, Sub-Sampling and Injection Locking

Portable audio products have not yet seen a wireless headphone solution that has been widely accepted. The main reason for this is that power consumption for current solutions is too high. We present a solution the uses a sub-sampling receiver combined with Q-enhanced RF filtering and injection-locked LO generation to provide high performance with low power consumption. This paper describes in detail the transceiver architecture, frequency plan, tuning algorithms and obtained performance. The transceiver is fabricated in TSMC 0.18 μm CMOS. The analog and RF sections of the transceiver consume peak currents of 5.2 mA in RX mode and 20.3 mA in TX mode.

60-GHz transmit/receive switch using a p–n diode and MOS transistors in 130-nm CMOS

A single-pole-double-throw transmit/receive switch using a shunt p–n diode and shunt NMOS transistors in 130-nm CMOS technology that operates around 60GHz is reported. The switch exhibits insertion loss of ∼2 and 3dB for TX and RX mode, respectively at 60GHz. The diode has ∼6X lower parasitic capacitance for given on resistance compared to NMOS transistors in the CMOS technology, which results in lower insertion loss. Furthermore, the p–n diode has greater than 11-V breakdown voltage, which enables the switch to attain higher than 18-dBm measured input 1-dB compression point. This is the highest among CMOS millimeter-wave switches reported up to date. Transmit to receive port isolation of the switch is ∼20dB at 60GHz.

A 2-Gb/s 130-nm CMOS RF-Correlation-Based IR-UWB Transceiver Front-End

This paper presents a carrierless RF-correlation-based impulse radio ultra-wideband transceiver (TRX) front-end in a 130-nm CMOS process. Timing synchronization and coherent demodulation are implemented directly in the RF domain, targeting applications such as short-range energy-efficient wireless communication at gigabit/second data rates. The 6-10-GHz band is exploited to achieve higher data rate. Binary phase-shift keying modulated impulse is generated by edge combining the delayed clock signal at a lower frequency of 2 GHz to avoid a more power-hungry phase-locked loop at higher frequency (e.g., 8 GHz). An on-chip pulse shaper inside the pulse generator is designed to provide filtering for an edge-combined signal to comply with the Federal Communications Commission spectrum emission mask. In order to achieve 25-ps delay accuracy and 500-ps delay range for the proposed two-step RF synchronization, a template-based digital delay generation scheme is proposed, which delays the locally generated trigger pulse instead of the wideband pulse itself. Occupying 6.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of chip area, the TRX achieves a maximum data rate of 2 Gb/s and a receiver (RX) sensitivity of -64 dBm with a bit error rate of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> , while requiring only 51.5 pJ/pulse in the transmitter mode and 72.9 pJ/pulse in the RX mode.

Negative charge-pump based antenna switch controller using 0.18 µm SOI CMOS technology

An antenna switch controller integrated with single-pole-multi-throw RF switches is presented. It is implemented in a 0.18 µm CMOS thin-film silicon-on-insulator (SOI) process. The proposed switch controller generates a negative voltage to enhance the linearity and power-handling capability of CMOS antenna switches, resulting in excellent RF performances. The size of the controller is 0.35 mm2 and the power consumption is 2 µA for stand-by mode and 50 µA for Rx mode.

Theoretical constraints on the generation mechanism of auroral medium frequency burst radio emissions

[1] Auroral medium frequency (MF) burst is an impulsive auroral radio emission observed at ground level between ∼1.3 and 4.5 MHz for a few minutes at substorm onsets. Despite multiple suggested theories, the exact generation mechanism for MF burst remains unknown. The foremost theory suggests that MF burst originates from Langmuir or upper hybrid waves excited over a range of altitudes in the bottomside or topside F region, which linearly mode convert to the electromagnetic LO mode, gaining access to ground level. Analysis of plasmas with two electron components implies the existence of additional normal modes, commonly referred to as the electron acoustic (EA) and electron cyclotron sound (ECS) modes, which have been suggested to potentially play a role in the generation of MF burst. Analytical calculations using Waves in Homogeneous, Anisotropic Multicomponent Plasmas, or WHAMP, and other dispersion-solving calculations are applied to applicable ionospheric normal modes (RX, LO, Langmuir or upper hybrid, EA, and ECS), compared to previous results, and applied to MF burst and the auroral plasma environment. Computation of resonant parallel energies suggests that, in the presence of an auroral electron distribution, instability of EA, ECS, LX, and Langmuir or upper hybrid modes is possible. The same analysis suggests that LO and RX modes are unlikely to be directly excited. Excitation of the EA or ECS mode in the frequency range applicable to MF burst is found to be more favorable for higher ionospheric plasma densities (fpe/fce > 2.36) and higher secondary electron temperatures (Th ≈ 100s of eV). Growth rate calculations suggest that growth of the EA or ECS mode is excitable by the auroral electron beam with higher growth rates for the ECS mode.

A Low-power and Low-complexity Baseband Processor for MIMO-OFDM WLAN Systems

This paper presents an energy-efficient design and the implementation results of a high speed two transmitter--two receiver multi-input multi-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN baseband processor. The proposed processor includes a bit-parallel processing physical layer convergence procedure (PLCP) processor which lowers system clock frequency. A cost-efficient MIMO spatial multiplexing (SM) symbol detector is also proposed in a physical medium dependent (PMD) processor. The proposed symbol detection algorithm is based on a sorted QR decomposition (SQRD) scheme followed by a maximum-likelihood (ML) test. The proposed algorithm shows enhanced performance compared to the conventional algorithms such as SQRD and ordered successive interference cancellation (OSIC) algorithms. The proposed baseband processor supports a maximum data rate of 130 Mbps at a 40 MHz operation frequency. The power consumptions of the PLCP processor are 27 mW and 93 mW for TX and RX modes, respectively, which are reduced by 70% compared with that of a common bit-serial architecture. The complexity of the symbol detector in the PMD processor is reduced by 18% compared with that of the conventional hardware architecture.

A 3–5-GHz UWB Front-End for Low-Data Rate WPANs in 90-nm CMOS

A 3-5-GHz ultra-wideband front-end for low-data rate wireless personal area networks is presented in this paper. The circuit, fabricated in a 90-nm CMOS technology, includes a Gaussian-envelope carrier-based transmitter, a direct-conversion down-converter, and an LO frequency synthesizer. A highly accurate Gaussian pulse shape is achieved by using a nonlinear pulse-forming approach, which provides a spectral efficiency of 38%. Moreover, a side-lobe rejection higher than 27 dB is reached without external filters. The transmitter achieves a peak pulse repetition frequency of 500 MHz supporting both pulse-position modulation and binary phase-shift-keying modulation schemes. It includes a baseband digital modulator, which implements spreading and time-hopping functions, and can be easily programmed to support different data rates, mean pulse repetition frequencies, and modulation timing parameters. The down-converter exploits a single-ended low-noise amplifier to avoid the off-chip wideband balun and minimize power consumption. It provides a 29-dB conversion gain and 5.2-dB noise figure while drawing only 8 mA. Operating from a 1.2-V supply, the overall front-end dissipates 42 pJ/pulse in RX mode and 56 pJ/pulse in TX mode.

Single and Four-Element $Ka$-Band Transmit/Receive Phased-Array Silicon RFICs With 5-bit Amplitude and Phase Control

Ka-band SiGe BiCMOS single- and four-element phased arrays capable of both transmit and receive operation with 5-bit phase and amplitude control are presented. The design is based on the All-RF architecture with RF phase shifters and attenuators, and a 4:1 passive power combining/dividing network. The four-element array results in an average gain of ~ 0 dB per channel and a noise figure of 9.0 dB, and is designed to be placed behind III-V T/R modules. The rms phase error is 5.6° (5-bit operation) and < 12.5° (4-bit operation) over a 2 or 5 GHz instantaneous bandwidth, respectively, centered at around 36.5 GHz. In the receive mode, the input P1dB is -16 dBm per channel (IIP3 of - 5.9 dBm), and in the transmit mode, the output P1dB is +4-5 dBm, all at 35-36 GHz. The measured isolation between the channels is better than 30 dB. The array maintained excellent phase characteristics up to 100°C with no change in the rms phase error. Also, ten different four-element phased arrays were tested (40 channels) and result in an rms gain variation of 0.5 dB at 34-39 GHz. The four-element array consumes 171 and 142 mW in the Tx and Rx modes from 1.8 V, and occupies an area of 2.0 × 2.02 mm2. To our knowledge, this is the smallest and lowest power consumption on-chip K ?-band phased-array to-date.

능동 위상 배열 SAR 안테나를 위한 X-대역 송수신 모듈의 설계 및 제작

본 논문에서는 능동 위상 배열 안테나를 가지는 SAR(Synthetic Aperture Radar)용 X-대역 T/R(Transmit/Receive) 모듈을 설계, 제작하였다. T/R 모듈은 X-대역에서 800 MHz 이상 대역폭을 가지며 이중 편파 운용이 가능하다. 송신 출력 7 W 이상에 잡음지수 3.9 dB 이하를 가진다. 위상과 이득은 6비트 위상변위기와 6비트 디지털 감쇠기에 의해 각각 제어된다. 게다가 제작된 T/R 모듈은 방향성 결합기와 전력분배기로 연결되는 성능 점검/보정 포트를 가진다. LTCC 다층 기판을 사용하여 고직접화 T/R 모듈이 가능하게 하였다. 모든 동작 주파수 대역에서 수신시 RMS 이득 오차는 최대 0.8 dB 이하이고, 송/수신시 RMS 위상 오차는 최대 <TEX>$4^{\circ}$</TEX> 이하로 측정되었고, 또한 시험 결과 T/R 모듈은 요구되는 전기적인 성능을 만족하였다. 이 구조는 능동 위상 배열 SAR용 안테나에 적용될 수 있음을 확인하였다. In this paper, a X-Band T/R-module for SAR(Synthetic Aperture Radar) systems based on active phased array antennas is designed and fabricated. The T/R modules have a and width of more than 800 MHz centered at X-Band and support dual, switched polarizations. The output power of the module is 7 watts over a wide bandwidth. The noise figure is as low as 3.9 dB. Phase and amplitude are controlled by a 6-bit phase shifter and a 6-bit digital attenuator, respectively. Further the fabricated T/R module has est and calibration port with directional coupler and power divider. Highly integrated T/R module is achieved by using LTCC(Low Temperature Co-fired Ceramic) multiple layer substrate. RMS gain error is less than 0.8 dB max. in Rx mode, and RMS phase error is less than <TEX>$4^{\circ}$</TEX> max. in Rx/Tx phase under all operating frequency band, or the T/R module meet the required electrical performance m test. This structure an be applied to active phase array SAR Antennas.