RX Chain Research Articles

TD-SCDMA/HSDPA Transceiver and Analog Baseband Chipset in 0.18- $\mu\hbox{m}$ CMOS Process

A dual-band time-division synchronous code-division multiple access chipset supporting 2.8-Mb/s high-speed downlink packet access has been demonstrated in 0.18-μm CMOS technology. The receiver adjacent channel selectivity requirement for the transceiver is relaxed by utilizing a high-dynamic-range analog-to-digital converter that allows selectivity improvement in analog baseband and digital baseband. The RX chain achieves 2.8-dB noise figure, -9.4-dBm total third-order input-referred intercepted point, and 5.7% error vector magnitude (EVM). TX delivers 5.0-dBm power, 88-dB gain control, and 4.5% EVM. The TX digital communication system band noise floor is 3 dB below the standard without using a surface acoustic wave filter. Both RX and TX from-idle-to-on switching times are less than 4 μS. Two chips consume 274 and 164 mW on transmitting and receiving, respectively, under a 1.8-V power supply.

High Sensitivity 900-MHz ISM Band Transceiver

Integrated 900-MHz ISM band transceiver LSI for analog cordless telephone has been realized by cost-effective process technology with sufficient performance. This LSI consisted of fully integrated transceiver, from RF-LNA to audio amplifier for RX chain, from microphone's amplifier to RF-PA for TX chain, and integrated RX- and TX-LO consisting of PLLs and VCOs. In view of narrow signal bandwidth with analog modulation, extremely low phase noise at low offset frequency from carrier was required for integrated VCO. Also, in view of fully duplex operations, signal isolation between TX and RX was required. Despite such a high integration and high performance, chip cost had to be minimized for low-cost applications. The 12-dB SINAD RX sensitivity was -111.2 dBm, the output power of TX was +3 dBm, and the phase noise of integrated VCO was -77 dBc/Hz at 3 kHz offset away from carrier. The current consumption at fully duplex operation was 76 mA at 3.6 V power supply. The chip was realized by 0.8 μm standard silicon BiCMOS process.