Runtime Support Research Articles

Runtime support for CPU-GPU high-performance computing on distributed memory platforms

IntroductionHardware heterogeneity is here to stay for high-performance computing. Large-scale systems are currently equipped with multiple GPU accelerators per compute node and are expected to incorporate more specialized hardware. This shift in the computing ecosystem offers many opportunities for performance improvement; however, it also increases the complexity of programming for such architectures.MethodsThis work introduces a runtime framework that enables effortless programming for heterogeneous systems while efficiently utilizing hardware resources. The framework is integrated within a distributed and scalable runtime system to facilitate performance portability across heterogeneous nodes. Along with the design, this paper describes the implementation and optimizations performed, achieving up to 300% improvement on a single device and linear scalability on a node equipped with four GPUs.ResultsThe framework in a distributed memory environment offers portable abstractions that enable efficient inter-node communication among devices with varying capabilities. It delivers superior performance compared to MPI+CUDA by up to 20% for large messages while keeping the overheads for small messages within 10%. Furthermore, the results of our performance evaluation in a distributed Jacobi proxy application demonstrate that our software imposes minimal overhead and achieves a performance improvement of up to 40%.DiscussionThis is accomplished by the optimizations at the library level and by creating opportunities to leverage application-specific optimizations like over-decomposition.

LACT: Liveness-Aware Checkpointing to reduce checkpoint overheads in intermittent systems

Intermittent computing supports execution of the systems experiencing frequent power failures, such as battery-less devices powered by energy-harvesting. In such systems, checkpoint and recovery is a commonly adopted technique, where volatile system states are regularly saved to Non-Volatile Memory (NVM), to preserve computing progress between power cycles. Since checkpoint involves a large number of NVM accesses, which is expensive in terms of both latency and energy, reducing its overhead has been a significant research challenge. In this paper, we present LACT (Liveness-Aware CheckpoinTing), a compiler optimization technique to minimize checkpoint overhead in intermittent systems. At the time of checkpoint execution, there exist dead values in general, which will not be used or overwritten in the future. LACT examines such liveness information, especially in arrays, based on compile-time analysis and excludes the dead values from the checkpoint to reduce required checkpoint data, which is a previously unexplored optimization opportunity. Our evaluation shows that LACT can reduce 46.4% of required checkpoint data without any runtime support, leading to reduction of 31.5% in execution time and a 5.2% decrease in power consumption on average. Our experiments in real energy-harvesting environment demonstrates that such improvement translates to a 31.6% improvement in end-to-end execution time.

MOBILE ATTENDANCE SYSTEM USING GPS AND FACIAL AUTHENTICATION

Student attendance in any educational institutions is a critical content of the administration of school and the major task of the course lecturer who maintain attendance. The conventional method of monitoring students' attendance in the classroom typically involves requiring students to physically record their attendance. Initially, this process was carried out manually using pen and paper. However, as the student population grows, this approach becomes increasingly burdensome, time-consuming, and susceptible to mistakes. To avoid these challenges, this paper proposes a Mobile attendance system using GPS locator and facial authentication algorithm to monitor students’ attendance using android mobile devices. The mobile attendance app is based on Client-Server Architecture where the server is hosted in the cloud and clients are with mobile devices with in-built GPS Locator. To secure the integrity of the attendance, the GPS locator helps in locating the precise geographical position of the students present, a mock detector is also integrated into the app to detect fake location of the students in the classroom meeting and the facial image used by the student at runtime support startup camera.

Flock: Towards Multitasking Virtual Machines for Function-as-a-Service

FaaS, or function as a service, promises unprecedented cost-efficiency and elasticity thanks to its on-demand and fine-grained execution nature. However, modern FaaS platforms mainly adopt virtual machines (VMs) or containers as a computing abstraction, which incurs costs like high startup latency, large memory footprint, and high communication overhead. Multi-tasking virtual machines (MVMs), which allow co-executing multiple functions in the same managed language runtime, are appealing for FaaS due to their lightweight nature. Unfortunately, existing MVMs are not designed for FaaS. The proposed abstraction of MVMs does not provide specialized support for fine-grained, latency-sensitive functions and their chain-like execution patterns. Meanwhile, the underlying runtime still contains many global modules and lacks essential support for function-level resource accounting and isolation. To this end, this work proposes <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Flock</i> , a retrofitted MVM for FaaS execution, which provides FaaS-aware abstractions named <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">funclets</i> and enhanced runtime support for isolation. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Flock</i> is implemented atop the HotSpot JVM of OpenJDK 8. Performance evaluation shows that <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Flock</i> results in up to three orders of magnitude performance improvement over state-of-the-art FaaS platforms like OpenWhisk while providing sufficient isolation support for FaaS functions.

Compute units in OpenMP: Extensions for heterogeneous parallel programming

SummaryThis article evaluates the current support for heterogeneous OpenMP 5.2 applications regarding the simultaneous activation of host and device computing units (e.g., CPUs, GPUs, or FPGAs). The article identifies limitations in the current OpenMP specification and describes the design and implementation of novel OpenMP extensions and runtime support for heterogeneous parallel programming. The Compute Unit (CUs) abstraction is introduced in the OpenMP programming model. The Compute Unit abstraction is defined in terms of an aggregation of computing elements (e.g., CPUs, GPUs, FPGAs). On top of CUs, the article describes dynamic work sharing constructs and schedulers that address the inherent differences in compute power of host and device CUs. New constructs and the corresponding runtime support are described for the new abstractions. The article evaluates the case of a hybrid multilevel parallelization of the NPB‐MZ benchmark suite. The implementation exploits both coarse‐grain and fine‐grain parallelism, mapped to CUs of different nature (GPUs and CPUs). All CUs are activated using the new extensions and runtime support. We compare hybrid and nonhybrid executions under two state‐of‐the‐art work‐distribution schemes (Static and Dynamic Task schedulers). On a computing node composed of one AMD EPYC 7742 @ 2.250GHz (64 cores and 2 threads/core, totalling 128 threads per node) and 2 GPU AMD Radeon Instinct MI50 with 32GB, hybrid executions present speedups from 1.08 up to 3.18 with respect to a nonhybrid GPU implementation, depending on the number of activated CUs.

Heterogeneous programming using OpenMP and CUDA/HIP for hybrid CPU-GPU scientific applications

Hybrid computer systems combine compute units (CUs) of different nature like CPUs, GPUs and FPGAs. Simultaneously exploiting the computing power of these CUs requires a careful decomposition of the applications into balanced parallel tasks according to both the performance of each CU type and the communication costs among them. This paper describes the design and implementation of runtime support for OpenMP hybrid GPU-CPU applications, when mixed with GPU-oriented programming models (e.g. CUDA/HIP). The paper describes the case for a hybrid multi-level parallelization of the NPB-MZ benchmark suite. The implementation exploits both coarse-grain and fine-grain parallelism, mapped to compute units of different nature (GPUs and CPUs). The paper describes the implementation of runtime support to bridge OpenMP and HIP, introducing the abstractions of Computing Unit and Data Placement. We compare hybrid and non-hybrid executions under state-of-the-art schedulers for OpenMP: static and dynamic task schedulings. Then, we improve the set of schedulers with two additional variants: a memorizing-dynamic task scheduling and a profile-based static task scheduling. On a computing node composed of one AMD EPYC 7742 @ 2.250 GHz (64 cores and 2 threads/core, totalling 128 threads per node) and 2 × GPU AMD Radeon Instinct MI50 with 32 GB, hybrid executions present speedups from 1.10× up to 3.5× with respect to a non-hybrid GPU implementation, depending on the number of activated CUs.

Improving performance of SYCL applications on CPU architectures using LLVM‐directed compilation flow

SummaryThe wide adoption of SYCL as an open‐standard API for accelerating C++ software in domains such as HPC, automotive, artificial intelligence, machine learning, and other areas necessitates efficient compiler and runtime support for a growing number of different platforms. Existing SYCL implementations provide support for various devices like CPUs, GPUs, DSPs, FPGAs and so forth, typically via OpenCL or CUDA backends. While accelerators have increased the performance of user applications significantly, employing CPU devices for further performance improvement is beneficial due to the significant presence of CPUs in existing data‐centers. SYCL applications on CPUs, currently go through an OpenCL backend. Though an OpenCL backend is valuable in supporting accelerators, it may introduce additional overhead for CPUs since the host and device are the same. Overheads like a run‐time compilation of the kernel, transferring of input/output memory to/from the OpenCL device, invoking the OpenCL kernel and so forth, may not be necessary when running on the CPU. While some of these overheads (such as data transfer) can be avoided by modifying the application, it can introduce disparity in the SYCL application's ability to achieve performance portability on other devices. In this article, we propose an alternate approach to running SYCL applications on CPUs. We bypass OpenCL and use a CPU‐directed compilation flow, along with the integration of whole function vectorization to generate optimized host and device code together in the same translation unit. We compare the performance of our approach—the CPU‐directed compilation flow, with an OpenCL backend for existing SYCL‐based applications, with no code modification for BabelStream benchmark, Matmul from the ComputeCpp SDK, N‐body simulation benchmarks and SYCL‐BLAS (Aliaga et al. Proceedings of the 5th International Workshop on OpenCL; 2017.), on CPUs from different vendors and architectures. We report a performance improvement of up to on BabelStream benchmarks, up to on Matmul, up to on the N‐body simulation benchmark and up to 16% on SYCL‐BLAS.

Vector Extensions in COTS Processors to Increase Guaranteed Performance in Real-Time Systems

The need for increased application performance in high-integrity systems such as those in avionics is on the rise as software continues to implement more complex functionalities. The prevalent computing solution for future high-integrity embedded products is multi-processor systems-on-chip (MPSoC) processors. MPSoCs include central processing unit (CPU) multicores that enable improving performance via thread-level parallelism. MPSoCs also include generic accelerators (graphics processing units [GPUs]) and application-specific accelerators. However, the data processing approach (DPA) required to exploit each of these underlying parallel hardware blocks carries several open challenges to enable the safe deployment in high-integrity domains. The main challenges include the qualification of its associated runtime system and the difficulties in analyzing programs deploying the DPA with out-of-the-box timing analysis and code coverage tools. In this work, we perform a thorough analysis of vector extensions (VExts) in current commercial off-the-shelf (COTS) processors for high-integrity systems. We show that VExts prevent many of the challenges arising with parallel programming models and GPUs. Unlike other DPAs, VExts require no runtime support, prevent design race conditions that might arise with parallel programming models, and have minimum impact on the software ecosystem, enabling the use of existing code coverage and timing analysis tools. We develop vectorized versions of neural network kernels and show that the NVIDIA Xavier VExts provide a reasonable increase in guaranteed application performance of up to 2.7x. Our analysis contends that VExts are the DPA approach with arguably the fastest path for adoption in high-integrity systems.

Bringing Cell Subpopulation Discovery on a Cloud-HPC Using rCASC and StreamFlow.

The idea behind novel single-cell RNA sequencing (scRNA-seq) pipelines is to isolate single cells through microfluidic approaches and generate sequencing libraries in which the transcripts are tagged to track their cell of origin. Modern scRNA-seq platforms are capable of analyzing up to many thousands of cells in each run. Then, combined with massive high-throughput sequencing producing billions of reads, scRNA-seq allows the assessment of fundamental biological properties of cell populations and biological systems at unprecedented resolution.In this chapter, we describe how cell subpopulation discovery algorithms, integrated into rCASC, could be efficiently executed on cloud-HPC infrastructure. To achieve this task, we focus on the StreamFlow framework which provides container-native runtime support for scientific workflows in cloud/HPC environments.

Enabling Far-Edge Intelligent Services with Network Applications: The Automotive Case

The fifth generation of mobile networks (5G) is rapidly reaching deployment across the globe, promising a series of advances for vertical service providers, both in terms of performance and in terms of operational capabilities. In this context, the 5G-IANA Network Application platform focuses on the rapidly advancing domain of intelligent, data centric, Artificial Intelligence/Machine Learning (AI/ML)-enabled applications, with a particular focus on the automotive domain. In this article, we present the key functional features designed for the support of such services including the integration of (mobile) far-edge resources, as well as ML-aware orchestration primitives. This includes novel features such as decision support for the optimal distribution of end-to-end ML pipelines, as well as run-time support for client selection in Federated Learning setups, far-edge failure handling and distribution drift aware lifecycle management. Such features come to address a series of limitations associated with legacy 5G management & orchestration systems, such as resource consumption of data centric services and privacy support. In this context, we further discuss the new opportunities arising for service provisioning and corresponding business models in the automotive ecosystem, with a particular emphasis on the implications of the emerging data and/or ML-model sharing schemes.

Research on internetware: Review and prospect

<p indent="0mm">Software is the core component of IT industry and an important “infrastructure” that supports social operations in the digital economy era. Since the 21st century, the internet has evolved into a global ubiquitous computing environment and open platform. Its open, dynamic, and uncontrollable nature requires the corresponding changes in the basic form and characteristics of software, the conceptual framework, and the logical connotation, and thus leads to substantial challenges to software theory, methods, and technologies. In 2000, researchers from China proposed the term “internetware”, which indicates a new software paradigm for the internet computing. After more than <sc>20 years</sc> of efforts, a series of important research achievements have been made in aspects of the basic model, development methodology, runtime support, quality assessment and assurance of internetware, and resulted in systematic innovation results and produced a wide range of academic and industrial impacts. In internetware, the software model consists of a set of autonomous software entities distributed and/or decentralized over the internet and other extensions like internet of things and 4G/5G, together with a set of connectors for enabling collaborations among these entities in various ways. Internetware software entities are able to sense dynamic changes of the underlying environments, and continuously adapt to these changes by means of structural and behavioral maintenance and evolution. From the micro perspective, internetware software entities collaborate with each other on demand and on the fly. From the macro perspective, the entities can self-organize to form an application or community of interest and even decentralized autonomous organizations. As a result, the development and evolution of a software application with internetware can be viewed as continuous and iterative composition of various “disordered” resources into “ordered” software applications. Thus, software development with internetware is a process being bottom-up, inside-out, spiral, and to some extent, similar with the complex adaptive systems. For example, the internetware paradigm proposed the theory of software architecture modeling (called ABC methodology) covering the whole life-cycle, where the core artifacts and activities of every single stage are unified into the software architecture model and its iterative refinement and transformation. In this way, the internetware paradigm greatly improves the efficiency and quality of software development and evolution. In addition, the internetware paradigm expands the software architecture from the development phase to the runtime, by proposing the concept of runtime software architecture (RSA). The RSA has been widely applied for a large number of information “silo” systems to enable the functionality and data interoperability. This solution is a significantly disruptive technical invention, or namely the “black box” mode, based on the client-driven resource reflection mechanism to achieve automatic recovery of the system runtime architecture and automatic generation of data access interfaces. Compared to the traditional “white box” interoperability solution, the internetware paradigm eliminates the need of accessing source code, documentation, and original development team, and improves the interoperability efficiency between information silos, with more than 100X acceleration. This article reviews the research and practice of internetware from the perspective of software paradigm, following the internet computing environment and its extensions as a clue. It also discusses the future research outlook of internetware, especially for the ubiquitous computing environments and data centric technologies.

Runtime Support for Accelerating CNN Models on Digital DRAM Processing-in-Memory Hardware

Processing-in-memory (PIM) provides promising solutions to the main memory bottleneck by placing computational logic in or near memory devices to reduce data movement overheads. Recent work explored how commercial DRAM can feature digital PIM logic while meeting fab-level energy and area constraints, and showed a significant speedup in the inference time of data-intensive deep learning models. However, convolutional neural network (CNN) models were not considered as main targets for the commercial DRAM-PIM due to their compute-intensive convolution layers. Moreover, recent studies revealed that the area and power constraints on memory die prevent DRAM-PIM from competing with GPUs and specialized accelerators in accelerating them. Recently, mobile CNN models have increasingly adopted a composition of depthwise and pointwise convolutions instead of such compute-intensive convolutions to reduce computation cost without accuracy drop. In this paper, we show that 1x1 convolution can be offloaded for PIM acceleration with integrated runtime support and without any hardware or algorithm changes. We provide further speedup with parallel execution on GPU and DRAM-PIM and code generation optimizations. Our solution achieves up to 35.2% (31.6% on average) speedup for all 1x1 convolutions for mobile CNN models against GPU.

Joint synthesis and registration network for deformable MR-CBCT image registration for neurosurgical guidance

Objective. The accuracy of navigation in minimally invasive neurosurgery is often challenged by deep brain deformations (up to 10 mm due to egress of cerebrospinal fluid during neuroendoscopic approach). We propose a deep learning-based deformable registration method to address such deformations between preoperative MR and intraoperative CBCT. Approach. The registration method uses a joint image synthesis and registration network (denoted JSR) to simultaneously synthesize MR and CBCT images to the CT domain and perform CT domain registration using a multi-resolution pyramid. JSR was first trained using a simulated dataset (simulated CBCT and simulated deformations) and then refined on real clinical images via transfer learning. The performance of the multi-resolution JSR was compared to a single-resolution architecture as well as a series of alternative registration methods (symmetric normalization (SyN), VoxelMorph, and image synthesis-based registration methods). Main results. JSR achieved median Dice coefficient (DSC) of 0.69 in deep brain structures and median target registration error (TRE) of 1.94 mm in the simulation dataset, with improvement from single-resolution architecture (median DSC = 0.68 and median TRE = 2.14 mm). Additionally, JSR achieved superior registration compared to alternative methods—e.g. SyN (median DSC = 0.54, median TRE = 2.77 mm), VoxelMorph (median DSC = 0.52, median TRE = 2.66 mm) and provided registration runtime of less than 3 s. Similarly in the clinical dataset, JSR achieved median DSC = 0.72 and median TRE = 2.05 mm. Significance. The multi-resolution JSR network resolved deep brain deformations between MR and CBCT images with performance superior to other state-of-the-art methods. The accuracy and runtime support translation of the method to further clinical studies in high-precision neurosurgery.

VR-PRUNE: Decidable Variable-Rate Dataflow for Signal Processing Systems

The dataflow concept has been successfully used for modeling and synthesizing signal processing applications since decades, and recently, dataflow has also been discovered to match the computation model of machine learning applications, leading to extremely successful dataflow based application design frameworks. One of the most attractive features of dataflow, especially for signal processing, is related to its formal nature: when properly defined, a dataflow-based application model can be analytically verified for correctness at the stage of application design. This paper proposes VR-PRUNE, a novel dataflow model of computation that is aimed for design of high-performance signal processing software, together with runtime support that allows efficient application deployment to heterogeneous GPU-equipped platforms. Compared to prior work, VR-PRUNE features variable token rate processing, which enables designing adaptive signal processing applications, and implementing solutions that, e.g., allow trading-off between power consumption and filtering bandwidth at runtime. The paper presents the formal concepts of VR-PRUNE, as well as four application examples from domains related to signal processing, accompanied with quantitative results, which show that using VR-PRUNE enables, for example, application power-performance scaling, and on the other hand describing adaptive application behavior with 59% fewer dataflow graph components compared to previous work.

Runtime Support for Openmp Hybrid Cpu-Gpu Applications

Runtime Support for Openmp Hybrid Cpu-Gpu Applications

Компилятор с языка программирования EL: усовершенствование и развитие

The implementation of the new multi-paradigm (functionally- imperative) programming language El, developed at the Department of Computer Science of the Novosibirsk State Technical University, in the form of a compiler is associated with the need to find ways to solve a number of complex problems. The current version of the compiler does implement only partially functionality of the language and generates far from optimal executable codes. In this paper, we consider the problem of an efficient compilation of an El-program, taking into account the need to implement new high-level data structures (two-sided lists, vectors with special forms of access, and a number of others) and control structures of the language, which make it possible to uniformly define cyclic and branching computational processes, as well as those laid down in the language a mechanism for explicitly controlling the mutability of variables. The tasks of improving and developing a compiler organized according to the classical multi-platform scheme are briefly considered, in which the front-end (lexical, syntactic, and semantic analyzers) converts the program to be translated into pseudocode of a single format, and used efficient infrastructure for building LLVM compilers as a back-end that turns pseudocode into executable code for different platforms. Execution of all possible operations on elements of high-level data structures (lists, tuples, vectors), as well as on arbitrary-precision numbers, has been moved to the runtime support library and, accordingly, can be deeply optimized. For this structure, the outlined ways of solving the problem of developing and improving the compiler by deep reforming and optimization of the chain of transformations of the translated program implemented by the front-end are formulated. At the initial stage, it is planned to implement a new compiler for two platforms: Linux and Windows.

Flexible runtime support of business processes under rolling planning horizons

This work has been motivated by the needs we discovered when analyzing real-world processes from the healthcare domain that have revealed high flexibility demands and complex temporal constraints. When trying to model these processes with existing languages, we learned that none of the latter was able to fully address these needs. This motivated us to design TConDec-R, a declarative process modeling language enabling the specification of complex temporal constraints. Enacting business processes based on declarative process models, however, introduces a high complexity due to the required optimization of objective functions, the handling of various temporal constraints, the concurrent execution of multiple process instances, the management of cross-instance constraints, and complex resource allocations. Consequently, advanced user support through optimized schedules is required when executing the instances of such models. In previous work, we suggested a method for generating an optimized enactment plan for a given set of process instances created from a TConDec-R model. However, this approach was not applicable to scenarios with uncertain demands in which the enactment of newly created process instances starts continuously over time, as in the considered healthcare scenarios. Here, the process instances to be planned within a specific timeframe cannot be considered in isolation from the ones planned for future timeframes. To be able to support such scenarios, this article significantly extends our previous work by generating optimized enactment plans under a rolling planning horizon. We evaluate the approach by applying it to a particularly challenging healthcare process scenario, i.e., the diagnostic procedures required for treating patients with ovarian carcinoma in a Woman Hospital. The application of the approach to this sophisticated scenario allows avoiding constraint violations and effectively managing shared resources, which contributes to reduce the length of patient stays in the hospital.

Digital Twin Generation: Re-Conceptualizing Agent Systems for Behavior-Centered Cyber-Physical System Development.

Cyber-Physical Systems (CPS) form the new backbone of digital ecosystems. Upcoming CPS will be operated on a unifying basis, the Internet of Behaviors (IoB). It features autonomous while federated CPS architectures and requires corresponding behavior modeling for design and control. CPS design and control involves stakeholders in different roles with different expertise accessing behavior models, termed Digital twins. They mirror the physical CPS part and integrate it with the digital part. Representing role-specific behaviors and provided with automated execution capabilities Digital twins facilitate dynamic adaptation and (re-)configuration. This paper proposes to conceptualize agent-based design for behavior-based Digital twins through subject-oriented models. These models can be executed and, thus, increase the transparency at design and runtime. Patterns recognizing environmental factors and operation details facilitate the configuration of CPS. Subject-oriented runtime support enables dynamic adaptation and the federated use of CPS components.

Exploiting Mixed Binaries

Unsafe programming systems are still very popular, despite the shortcomings due to several published memory-corruption vulnerabilities. Toward defending memory corruption, compilers have started to employ advanced software hardening such as Control-flow Integrity (CFI) and SafeStack. However, there is a broad interest for realizing compilers that impose memory safety with no heavy runtime support (e.g., garbage collection). Representative examples of this category are Rust and Go, which enforce memory safety primarily statically at compile time. Software hardening and Rust/Go are promising directions for defending memory corruption, albeit combining the two is questionable. In this article, we consider hardened mixed binaries, i.e., machine code that has been produced from different compilers and, in particular, from hardened C/C++ and Rust/Go (e.g., Mozilla Firefox, Dropbox, npm, and Docker). Our analysis is focused on Mozilla Firefox, which outsources significant code to Rust and is open source with known public vulnerabilities (with assigned CVE). Furthermore, we extend our analysis in mixed binaries that leverage Go, and we derive similar results. The attacks explored in this article do not exploit Rust or Go binaries that depend on some legacy (vulnerable) C/C++ code. In contrast, we explore how Rust/Go compiled code can stand as a vehicle for bypassing hardening in C/C++ code. In particular, we discuss CFI and SafeStack, which are available in the latest Clang. Our assessment concludes that CFI can be completely nullified through Rust or Go code by constructing much simpler attacks than state-of-the-art CFI bypasses.

Design and Implementation of a Criticality- and Heterogeneity-Aware Runtime System for Task-Parallel Applications

Heterogeneous multiprocessing (HMP) is an emerging technology for high-performance and energy-efficient computing. While task parallelism is widely used in various computing domains, such as embedded, big-data, and machine-learning computing domains, it still remains unexplored to investigate the efficient runtime support that effectively utilizes the criticality of the tasks of the target application and the heterogeneity of the underlying HMP system with full resource management. To bridge this gap, we propose CHRT, a criticality- and heterogeneity-aware runtime system for task-parallel applications. CHRT dynamically estimates the performance and power consumption of the target task-parallel application and robustly manages the full HMP system resources (i.e., core types, counts, and voltage/frequency levels) to maximize the overall efficiency. Our quantitative evaluation based on widely-used task parallel benchmarks and two full HMP systems (i.e., the XU3 and HiKey970 HMP systems) demonstrates the effectiveness of CHRT in that CHRT achieves significantly higher energy (e.g., 60.4 and 57.2 percent on average on the XU3 system) and energy-delay product (e.g., 52.2 and 44.0 percent on average on the HiKey970 system) efficiency than the baseline runtime system that employs the breadth-first scheduler and the state-of-the-art criticality-aware runtime system and incurs low performance overheads.